KR19990057892A - Contact formation method of semiconductor device - Google Patents
Contact formation method of semiconductor device Download PDFInfo
- Publication number
- KR19990057892A KR19990057892A KR1019970077971A KR19970077971A KR19990057892A KR 19990057892 A KR19990057892 A KR 19990057892A KR 1019970077971 A KR1019970077971 A KR 1019970077971A KR 19970077971 A KR19970077971 A KR 19970077971A KR 19990057892 A KR19990057892 A KR 19990057892A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- region
- polysilicon film
- peripheral circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 폴리사이드 구조의 전도막을 갖는 주변 회로 지역에서의 콘택 형성에 있어서, 상부 전도막과 하부 전도막의 콘택 저항을 감소시킬 수 있는 반도체 소자의 콘택 형성 방법에 관한 것으로서, 주변 회로 지역 및 셀 영역을 갖는 반도체 소자 제조 방법에 있어서, 제1폴리실리콘막과 실리사이드막이 적층된 게이트 전극을 상기 주변회로지역 및 상기 셀 지역 반도체 기판상에 각각 형성하는 제1단계; 노출된 상기 반도체 기판상에 엘리베이티드 소스 및 드레인 영역을 형성하는 제2단계; 상기 제2단계가 완료된 결과물을 평탄화 하는 층간절연막을 형성하는 제3단계; 상기 주변 회로 지역의 상기 실리사이드막과 상기 셀 지역이 상기 엘리베이티드 소스 또는 드레인영역을 오픈시키기 위하여 상기 층간절연막을 선택식각하는 제4단계; 상기 오픈된 실리사이드막을 제거하여 상기 제1폴리실리콘막을 노출시키는 제5단계; 및 상기 노출된 제1폴리 실리콘막과 콘택되는 제2폴리실리콘막을 형성하는 제6단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device capable of reducing contact resistance between an upper conductive film and a lower conductive film in forming a contact in a peripheral circuit region having a conductive film having a polyside structure. A semiconductor device manufacturing method comprising: a first step of forming a gate electrode on which a first polysilicon film and a silicide film are stacked on the peripheral circuit region and the cell region semiconductor substrate, respectively; Forming an elevated source and drain region on the exposed semiconductor substrate; A third step of forming an interlayer insulating film to planarize the resultant product of which the second step is completed; A fourth step of selectively etching the interlayer dielectric layer so that the silicide layer and the cell region of the peripheral circuit region open the elevation source or drain region; A fifth step of exposing the first polysilicon film by removing the open silicide film; And a sixth step of forming a second polysilicon film in contact with the exposed first polysilicon film.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 폴리사이드 구조의 전극과 폴리사이드 도전막 사이의 콘택 저항을 감소시키기 위한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for reducing contact resistance between an electrode having a polyside structure and a polyside conductive film.
잘 알려진 바와 같이, 소자의 고집적화 및 소형화에 따라 전도막의 전도성 향상이 새로운 이슈로 대두되고 있는 추세이며, 이를 충족하기 위해 폴리실리콘막 상부에 고융점 금속의 실리사이드막을 형성하여 폴리사이드 구조의 전극을 형성하는 기술이 상용화되고 있는 실정이다.As is well known, as the integration and miniaturization of the device is increasing the conductivity of the conductive film is emerging as a new issue, to meet this, to form a polysilicon electrode by forming a silicide film of a high melting point metal on top of the polysilicon film This technology is being commercialized.
도1은 종래 기술에 따른 콘택 형성 방법을 나타내는 단면도로서, 메모리 소자의 주변 회로 지역의 단면도이다.1 is a cross-sectional view showing a contact formation method according to the prior art, which is a cross-sectional view of a peripheral circuit region of a memory element.
먼저, 소정 공정이 완료된 실리콘 기판(11) 상부에 게이트 산화막, 제1폴리실리콘막(12), 제1텅스텐 실리사이드막(13)을 형성한 후, 패터닝하여 게이트 전극 패턴을 형성한 후, 이러한 게이트 전극 패턴의 수직 구조 측면에 산화막 스페이서(14)를 형성한다. 그리고, 층간절연막(16)을 형성하여 평탄화를 이룬다.First, a gate oxide film, a first polysilicon film 12, and a first tungsten silicide film 13 are formed on a silicon substrate 11 on which a predetermined process is completed, and then patterned to form a gate electrode pattern. An oxide spacer 14 is formed on the side of the vertical structure of the electrode pattern. Then, the interlayer insulating film 16 is formed to planarize.
이어서, 층간절연막(16)을 선택적으로 식각하여 제1텅스텐 실리사이드막(13)을 노출시키는 콘택홀을 형성한 후, 제2폴리실리콘막(17)을 형성한 후, 제2텅스텐 실리사이드막(18)을 형성한다.Subsequently, the interlayer insulating layer 16 is selectively etched to form a contact hole for exposing the first tungsten silicide layer 13, and then the second polysilicon layer 17 is formed, followed by the second tungsten silicide layer 18. ).
그러나, 이러한 제2텅스텐 실리사이드막(18)을 형성하기 위한 고온 공정에서 제2폴리실리콘막(17) 내의 도펀트가 콘택되는 제1텅스텐 실리사이드막(13)으로 확산되어 콘택 저항을 증가시키는 문제점이 유발된다.However, in the high temperature process for forming the second tungsten silicide layer 18, the dopant in the second polysilicon layer 17 diffuses into the first tungsten silicide layer 13 to be contacted, thereby causing a problem of increasing contact resistance. do.
또한 전술한 공정중 노출되는 제1텅스텐 실리사이드막(13)의 표면에 쉽게 텅스텐 산화막이 형성되어 제2폴리실리콘막(17) 형성 전의 세정 공정에서도 제거되지 않고 남아 콘택 저항을 증가시킨다.In addition, the tungsten oxide film is easily formed on the surface of the first tungsten silicide film 13 exposed during the above-described process, so that it is not removed even in the cleaning process before the second polysilicon film 17 is formed, thereby increasing the contact resistance.
따라서 이러한 문제점을 극복할 수 있는 반도체 소자의 콘택 형성 방법의 개발이 필요하게 되었다.Therefore, it is necessary to develop a contact forming method of a semiconductor device that can overcome such a problem.
전술한 바와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 실리사이드막 상에 폴리 실리콘막을 콘택 함에 있어, 상부 폴리실리콘막과 하부 실리사이드막의 콘택 저항을 감소시켜 소자특성을 향상시킬 수 있는 반도체 소자 제조 방법을 제공함을 그 목적으로 한다.In order to solve the above problems, the present invention provides a method of manufacturing a semiconductor device in which a contact resistance between an upper polysilicon film and a lower silicide film is improved in contacting a polysilicon film on a silicide film. To provide that purpose.
도1은 종래 기술에 따른 콘택 형성 방법을 나타내는 단면도.1 is a cross-sectional view showing a contact forming method according to the prior art.
도2a 내지 도2d는 본 발명의 일실시예에 따른 콘택 형성 방법을 나타내는 공정 단면도.2A to 2D are cross-sectional views illustrating a method for forming a contact according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 간단한 설명* Brief description of the main parts of the drawing
21 : 실리콘 기판 22 : 제1폴리 실리콘막21 silicon substrate 22 first polysilicon film
23 : 제1텅스텐 실리사이드막 24 :산화막 스페이서23: first tungsten silicide film 24: oxide film spacer
25 : 엘리베이티드 소스 및 드레인25: elevated source and drain
26 : 층간절연막26: interlayer insulating film
27 : 제2폴리 실리콘막27: second polysilicon film
28 : 제2텅스텐 실리사이드막28: second tungsten silicide film
상기와 같은 목적을 달성하기 위하여 본 발명의 반도체 소자 제조 방법은, 주변 회로 지역 및 셀 영역을 갖는 반도체 소자 제조 방법에 있어서, 제1폴리실리콘막과 실리사이드막이 적층된 게이트 전극을 상기 주변회로지역 및 상기 셀 지역 반도체 기판상에 각각 형성하는 제1단계; 노출된 상기 반도체 기판상에 엘리베이티드 소스 및 드레인 영역을 형성하는 제2단계; 상기 제2단계가 완료된 결과물을 평탄화 하는 층간절연막을 형성하는 제3단계; 상기 주변 회로 지역의 상기 실리사이드막과 상기 셀 지역이 상기 엘리베이티드 소스 또는 드레인영역을 오픈시키기 위하여 상기 층간절연막을 선택식각하는 제4단계; 상기 오픈된 실리사이드막을 제거하여 상기 제1폴리실리콘막을 노출시키는 제5단계; 및 상기 노출된 제1폴리 실리콘막과 콘택되는 제2폴리실리콘막을 형성하는 제6단계를 포함하여 이루어진다.In order to achieve the above object, the semiconductor device manufacturing method of the present invention is a semiconductor device manufacturing method having a peripheral circuit region and a cell region, wherein the gate electrode in which the first polysilicon film and the silicide film are laminated is formed in the peripheral circuit region and A first step of forming each on said cell area semiconductor substrate; Forming an elevated source and drain region on the exposed semiconductor substrate; A third step of forming an interlayer insulating film to planarize the resultant product of which the second step is completed; A fourth step of selectively etching the interlayer dielectric layer so that the silicide layer and the cell region of the peripheral circuit region open the elevation source or drain region; A fifth step of exposing the first polysilicon film by removing the open silicide film; And a sixth step of forming a second polysilicon film in contact with the exposed first polysilicon film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도2a 내지 도2d는 본 발명의 일실시예에 따른 콘택 형성 방법을 나타내는 공정 단면도로서, 주변 회로 지역(A)과 셀 영역(B)으로 구분하여 나타낸 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a contact according to an embodiment of the present invention, and are divided into peripheral circuit regions A and cell regions B. Referring to FIG.
먼저, 도2a에 도시된 바와 같이, 소정 공정이 완료된 하부층을 구비하는 실리콘 기판(21) 상부에 게이트 산화막, 제1폴리실리콘막(22), 제1텅스텐 실리사이드막(23)을 차례로 형성한다. 그리고, 제1텅스텐 실리사이드막(23), 제1폴리실리콘막(22), 게이트 산화막을 식각하여 게이트 전도막 패턴을 형성한 후, 이러한 수직 패턴 측면에 산화막 스페이서(24)를 형성한다. 그리고, 노출되는 실리콘 기판(21) 상부에 예컨대 선택적 증착 방법으로 실리콘막과 같은 엘리베이티드(elevated) 소스 및 드레인 영역(25)을 형성한다. 이러한 엘리베이티드 소스 및 드레인 영역(25)은 추후 진행되는 식각 공정에서의 식각제로부터 실리콘 기판(21)이 손상되는 것을 방지하기 위하여 형성하는 것이다. 즉, 실리콘과 텅스텐 실리사이드의 식각선택비가 1:1이므로 추후 진행되는 텅스텐 실리사이드막의 식각시 얕은 접합의 소스 및 드레인이 식각되므로써 접합 누설 전류 등이 발생하기 때문에 이를 방지하기 위하여 엘리베이티드 소스 및 드레인 영역을 형성하는 것이다. 따라서, 텅스텐 실리사이드막의 식각 후에도 이러한 엘리베이티드 소스 및 드레인 영역은 충분히 잔류되어 있어야 소자특성에 나쁜 영향을 미치지 못한다.First, as shown in FIG. 2A, a gate oxide film, a first polysilicon film 22, and a first tungsten silicide film 23 are sequentially formed on the silicon substrate 21 having the lower layer where a predetermined process is completed. After the first tungsten silicide layer 23, the first polysilicon layer 22, and the gate oxide layer are etched to form a gate conductive layer pattern, an oxide spacer 24 is formed on the side of the vertical pattern. Then, an elevated source and drain region 25 such as a silicon film is formed on the exposed silicon substrate 21 by, for example, a selective deposition method. The elevated source and drain regions 25 are formed to prevent the silicon substrate 21 from being damaged from the etchant in a subsequent etching process. That is, since the etching selectivity of silicon and tungsten silicide is 1: 1, the source and drain of the shallow junction are etched during the subsequent etching of the tungsten silicide layer, so that the junction leakage current is generated. To form. Therefore, even after etching of the tungsten silicide layer, the elevated source and drain regions must remain sufficiently so as not to adversely affect the device characteristics.
다음으로, 도2b에 도시된 바와 같이, 전체 구조 상부에 층간절연막(26)을 형성하여 평탄화를 이룬 후, 셀 영역(B)의 엘리베이티드 소스(또는 드레인)영역(25)과 주변 회로 지역(A)의 상기 제1텅스텐 실리사이드막(23)을 노출시키는 선택 식각공정을 진행한다.Next, as shown in FIG. 2B, an interlayer insulating film 26 is formed over the entire structure to planarize, and then the elevated source (or drain) region 25 and the peripheral circuit region (in the cell region B) are formed. A selective etching process of exposing the first tungsten silicide layer 23 of A) is performed.
다음으로, 종래와 같이 상부전도막을 형성하는 것이 아니라, 도2c에 도시된 바와 같이, 노출된 주변 회로 지역(A)의 상기 제1텅스텐 실리사이드막(23)을 Cl2/O2플라즈마에 의해 식각하여 주변 회로 지역(A)의 제1폴리실리콘막(22)을 노출시킨다. 이렇게 함으로써 후속으로 형성되는 제2폴리실리콘막으로부터 제1텅스텐 실리사이드막(23)으로 도펀트 확산을 효과적으로 차단할 수 있고, 제1텅스텐 실리사이드막(23) 표면에 텅스텐 산화막이 생기는 문제를 해결할 수 있다. 이러한 식각공정으로 셀 영역(B)의 엘리베이티드 소스(또는 드레인)영역(25)이 함께 식각 되지만 셀 영역(B)의 실리콘 기판(21)은 손상되지 않는다.Next, as shown in FIG. 2C, the first tungsten silicide layer 23 of the exposed peripheral circuit region A is etched by Cl 2 / O 2 plasma instead of forming an upper conductive layer as in the prior art. This exposes the first polysilicon film 22 in the peripheral circuit region A. FIG. This effectively prevents dopant diffusion from the subsequently formed second polysilicon film to the first tungsten silicide film 23 and solves the problem of a tungsten oxide film being formed on the surface of the first tungsten silicide film 23. In this etching process, the elevated source (or drain) region 25 of the cell region B is etched together, but the silicon substrate 21 of the cell region B is not damaged.
마지막으로, 도2d에 도시된 바와 같이, 제2폴리실리콘막(27)을 콘택홀에 매립함으로써 셀 영역(B)의 엘리베이티드 소스(또는 드레인)영역(25)과 주변 회로 지역(A)의 상기 제1폴리실리콘막(22)과 콘택 되도록 하고, 그 상부에 제2텅스텐 실리사이드막(28)을 형성한다.Finally, as shown in FIG. 2D, the second polysilicon film 27 is buried in the contact hole, so that the elevated source (or drain) region 25 and the peripheral circuit region A of the cell region B are filled. The first polysilicon layer 22 is in contact with the second tungsten silicide layer 28.
전술한 바와 같이 이루어지는 본 발명은, 셀 영역에서 제1폴리실리콘막의 전도성을 향상시키기 위하여 형성되는 텅스텐 실리사이드막이 주변 회로 지역에서는 콘택 저항을 증가시키는 요인으로 작용하므로, 주변 회로 지역의 이러한 텅스텐 실리사이드막을 제거하고, 이에 따라 발생되는 소스 및 드레인 영역의 손상 문제점을 엘리베이티드 소스 및 드레인을 형성함으로써 충분히 극복하여 콘택 저항을 증가시키기 않는 우수한 콘택을 형성한다.According to the present invention made as described above, since the tungsten silicide film formed to improve the conductivity of the first polysilicon film in the cell region acts as a factor of increasing the contact resistance in the peripheral circuit area, the tungsten silicide film in the peripheral circuit area is removed. In addition, the problem of damage to the source and drain regions generated thereby is sufficiently overcome by forming the elevated source and drain to form an excellent contact that does not increase the contact resistance.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은, 하부전도막의 텅스텐 실리사이드막이 그 상부에 형성되는 상부 폴리실리콘막과의 큰 콘택 저항을 갖는 문제점을 극복하기 위하여, 하부전도막의 텅스텐 실리사이드막을 제거하여 하부 폴리실리콘막과 상부 폴리실리콘막이 직접 콘택 되도록 함으로써 콘택 저항을 충분히 감소시킬 수 있고, 결과적으로 소자의 수율 및 신뢰성을 향상시킨다.The present invention made as described above, in order to overcome the problem that the tungsten silicide film of the lower conductive film has a large contact resistance with the upper polysilicon film formed thereon, by removing the tungsten silicide film of the lower conductive film, the lower polysilicon film and the upper By making the polysilicon film directly contact, the contact resistance can be sufficiently reduced, and consequently, the yield and reliability of the device are improved.
또한 본 발명은, 전술한 바와 같은 공정을 진행함에 있어서, 실리콘 기판 상부에 엘리베이티드 소스 및 드레인 영역을 형성함으로써 실리콘 기판의 소스 및 드레인 영역이 손상되는 것을 충분히 방지하여 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 한다.In addition, according to the present invention, an elevation of the source and drain regions of the silicon substrate is sufficiently prevented by forming the elevated source and drain regions on the silicon substrate, thereby improving the characteristics and reliability of the semiconductor device. And thereby high integration of the semiconductor device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970077971A KR100263673B1 (en) | 1997-12-30 | 1997-12-30 | Method for forming contact of semiconductor derive |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970077971A KR100263673B1 (en) | 1997-12-30 | 1997-12-30 | Method for forming contact of semiconductor derive |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990057892A true KR19990057892A (en) | 1999-07-15 |
| KR100263673B1 KR100263673B1 (en) | 2000-09-01 |
Family
ID=19529716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970077971A KR100263673B1 (en) | 1997-12-30 | 1997-12-30 | Method for forming contact of semiconductor derive |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100263673B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100323720B1 (en) * | 1999-12-31 | 2002-02-19 | 박종섭 | Elevated semiconductor layer and method for forming the same |
| KR100461334B1 (en) * | 1997-12-31 | 2005-05-03 | 주식회사 하이닉스반도체 | Contact hole formation method of semiconductor device |
| KR100512904B1 (en) * | 1999-12-24 | 2005-09-07 | 주식회사 하이닉스반도체 | Fabricating method for semiconductor device |
-
1997
- 1997-12-30 KR KR1019970077971A patent/KR100263673B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100461334B1 (en) * | 1997-12-31 | 2005-05-03 | 주식회사 하이닉스반도체 | Contact hole formation method of semiconductor device |
| KR100512904B1 (en) * | 1999-12-24 | 2005-09-07 | 주식회사 하이닉스반도체 | Fabricating method for semiconductor device |
| KR100323720B1 (en) * | 1999-12-31 | 2002-02-19 | 박종섭 | Elevated semiconductor layer and method for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100263673B1 (en) | 2000-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR19990057892A (en) | Contact formation method of semiconductor device | |
| KR100261329B1 (en) | Manufacturing method of semiconductor device | |
| KR100694996B1 (en) | Method for manufacturing capacitor in semiconductor device | |
| KR20000008404A (en) | Fabricating method of semiconductor device | |
| KR100277905B1 (en) | Manufacturing Method of Semiconductor Memory Device | |
| KR100578117B1 (en) | Method for forming interconnection of semiconductor device | |
| KR100505101B1 (en) | Method of forming contact for semiconductor device | |
| KR100743622B1 (en) | Method for manufacturing bit line contact of semiconductor device | |
| KR100745057B1 (en) | Method for fabricating of semiconductor device | |
| KR100230735B1 (en) | Process for fabricating semiconductor device | |
| KR19990016224A (en) | Manufacturing method of semiconductor device having dummy bit line under plate electrode | |
| KR100310542B1 (en) | Manufacturing method of semiconductor device | |
| KR100400322B1 (en) | A method for forming of a semiconductor device | |
| KR20000044673A (en) | Fabrication method of dram | |
| KR0139575B1 (en) | Method of manufacture in semiconductor device | |
| KR100679941B1 (en) | Method for fabricating contacts of semiconductor device | |
| KR19990015448A (en) | Manufacturing Method of Semiconductor Device | |
| KR20080029605A (en) | Method for fabricating semiconductor device | |
| KR20070003033A (en) | Method for fabricating semiconductor device | |
| KR19990057372A (en) | Manufacturing method of semiconductor device | |
| KR19980031105A (en) | Manufacturing Method of Semiconductor Device and Layout Diagram | |
| KR20030001085A (en) | Method for fabricating semiconductor device | |
| KR20020050916A (en) | Method for manufacturing capacitor in semiconductor device | |
| KR20030043138A (en) | Semiconductor device and Method for fabricating the same | |
| KR20020058259A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080425 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |