KR20020058259A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A fabrication method of semiconductor devices is provided to prevent a short between a second metal wire and a lower conductive layer by restraining an over-etching. CONSTITUTION: A plurality of bit lines(47) having a hard mask(49) and an insulating spacer(51) are formed on a lower structure(41) defined by a cell and a peripheral region. A plug(53a) is formed between the bit lines of a metal wire contact formation portion for connecting an upper electrode(61) of the peripheral region and a lower electrode(57) of the cell region. A capacitor is formed at the cell region to connect the plug(53a), and a conductive layer is formed on a second oxide layer(56). After forming an interlayer dielectric(63) on the resultant structure, a contact hole(65) connected to the upper electrode of the peripheral region is formed by selectively etching the interlayer dielectric, the second oxide layer and the conductive layer.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to form a semiconductor layer contacting an upper electrode of a capacitor after forming an anti-etching plug layer at the bottom thereof to manufacture a semiconductor device that improves yield and reliability of the device. It is about a method.

The method of manufacturing a semiconductor device according to the related art is a barrier metal layer 15 on a lower structure 11 insulated with a first insulating film 13 and defined with a cell region and a peripheral region, as shown in FIG. 1A. ), A tungsten (W) layer 17, a hard mask layer 19, and a first photosensitive film (not shown) are sequentially formed.

After selectively exposing and developing the first photoresist film so as to remain only at a portion where a bit line is to be formed, the hard mask layer 19 and a tungsten layer using the selectively exposed and developed first photoresist film as a mask. (17) and the barrier metal layer 15 are selectively etched, and then the first photosensitive film is removed.

Here, a bit line is formed of the barrier metal layer 15 and the tungsten layer 17.

Subsequently, a second insulating film is formed on the entire surface including the bit line and etched back to form second insulating film sidewalls 21 on both sides of the bit line.

The first insulating layer 13 is selectively removed using the hard mask layer 19 and the second insulating layer sidewall 21 as a mask.

Subsequently, the first polysilicon layer 23 is formed on the entire surface including the second insulating layer sidewall 21.

As shown in FIG. 1B, a second photoresist film (not shown) is applied on the first polycrystalline silicon layer 23, and then the second photoresist film is removed only at a portion where the lower electrode contact of the capacitor of the cell region is to be formed. It is selectively exposed and developed as much as possible.

The first polycrystalline silicon layer 23 is selectively etched using the selectively exposed and developed second photoresist film to form a plug layer 23a, and then the second photoresist film is removed.

Subsequently, the plug layer 23a is flatly etched by a chemical mechanical polishing method using the hard mask layer 19 as an etching end point.

As shown in FIG. 1C, the first oxide film 24 is formed on the entire surface including the plug layer 23a, and the hard mask layer 19 is etched to the end point by the chemical mechanical polishing method. Etch a flat surface.

After the nitride film 25 and the second oxide film 26 are sequentially formed on the entire surface including the first oxide film 24, the planarization process is performed.

Subsequently, after applying a third photoresist film (not shown) on the second oxide film 26, the third photoresist film is selectively exposed and developed to be removed only at a portion where the lower electrode of the capacitor of the cell region is to be formed. The second oxide layer 26 and the nitride layer 25 are selectively etched using the selectively exposed and developed third photoresist layer as a mask to form a first contact hole, and the third photoresist layer is removed.

A liner TiN layer is formed on the exposed plug layer 23a and the second oxide layer 26.

Thereafter, the TiN layer is flat-etched by a chemical mechanical polishing method using the second oxide layer 26 as an etching end point, and the lower portion separated from each other by the second oxide layer 26 and electrically connected to the plug layer 23a. The electrode 27 is formed.

The dielectric film 29 and the fourth photoresist film (not shown) are sequentially formed on the entire surface, and then the fourth photoresist film is selectively exposed and developed so as to remain only in the cell region.

Subsequently, the dielectric layer 29 of the peripheral region is etched using the selectively exposed and developed fourth photoresist layer, and the fourth photoresist layer is removed.

Here, the dielectric layer 29 is formed of TaON.

Thereafter, the upper electrode 31 of the capacitor is formed on the entire surface including the dielectric layer 29.

As shown in FIG. 1D, an interlayer insulating film 33 and a fifth photoresist film (not shown) are sequentially formed on the upper electrode 31, and then the metal wirings in which the fifth photoresist film is contacted with the upper electrode of the peripheral region. It is selectively exposed and developed to be removed only at the site where the contact hole is to be formed.

Subsequently, the interlayer insulating layer 33, the upper electrode 31, the second oxide layer 26, the nitride layer 25 and the first oxide layer 24 are selectively etched using the selectively exposed and developed fifth photoresist layer as a mask. A second contact hole 35 is formed, and the fifth photosensitive film is removed.

In the conventional method of manufacturing a semiconductor device, the step height of the device is increased due to the high integration of the device. Therefore, a step of 10 times occurs between the bit line wiring contact hole in the peripheral region and the upper electrode wiring contact hole of the capacitor. In the process of forming the first metal wiring contacting the upper electrode of the capacitor of the peripheral region and the second metal wiring contacting the bit line, the upper electrode has no etch selectivity with the oxide film, and thus the lower structure in the first metal wiring. Since the over-etched to the conductive layer of the excessive contact hole is generated to generate a short (Short) between the first metal wiring and the semiconductor substrate has a problem that the yield and reliability of the device is lowered.

The present invention has been made to solve the above problems, and since the etch preventing plug layer is first formed on the lower portion of the first metal wiring in the peripheral region contacted with the upper electrode of the capacitor, the first metal wiring is formed on the upper side thereof. And a transient contact caused by an excessive etching from the second metal wiring contact hole to the conductive layer of the lower structure by forming the plug layer in the process of forming the second metal wiring contacting the first metal wiring and the bit line of the peripheral region. It is an object of the present invention to provide a method for manufacturing a semiconductor device for preventing holes.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

11, 41: Substructure 13, 43: First insulating film

15, 45: barrier metal layer 17, 47: bit line

19 and 49: hard mask layers 21 and 51: second insulating film sidewalls

23, 53: first polycrystalline silicon layer 23a, 53a: plug layer

24, 54: first oxide film 25, 55: nitride film

26. 56: second oxide film 27, 57: lower electrode

29, 59: dielectric film 31, 61: upper electrode

33, 63: interlayer insulating film 35, 65: upper electrode wiring contact hole

In the method of manufacturing a semiconductor device of the present invention, the method comprises: forming a lower structure in which a plurality of bit lines having a hard mask layer and an insulating layer spacer are formed and defining a cell region and a peripheral region, and a lower electrode contact of a capacitor of the cell region; Forming a plug layer between the bit lines of the portion where the metal wiring contact to be formed in contact with the upper electrode of the capacitor in the peripheral region, and forming a first interlayer insulating film between the other bit lines, and forming a second interlayer insulating film on the entire surface Forming a capacitor electrically connected to the plug layer in the cell region, forming a conductive layer for the upper electrode of the capacitor on the second interlayer insulating layer in the peripheral region, and forming a third interlayer insulating layer on the entire surface And the third insulating layer, the conductive layer, and the second insulating layer using the plug layer as an etch stop layer. By selecting etching, including the step of forming a metal wiring contact hole contacts the upper electrode of the peripheral region is characterized by true.

When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and FIGS. 3A to 3E are cross-sectional views illustrating a manufacturing method of a semiconductor device in accordance with a second embodiment of the present invention. to be.

In the method of manufacturing a semiconductor device according to the first embodiment of the present invention, as shown in FIG. 2A, the barrier metal layer 45 is insulated from the first insulating layer 43 and the lower structure 41 in which the cell region and the peripheral region are defined. , A tungsten layer 47, a hard mask layer 49, and a first photosensitive film (not shown) are sequentially formed.

And selectively exposing and developing the first photoresist film so as to remain only in a portion where a bit line is to be formed, and then using the selectively exposed and developed first photoresist film as a mask, the hard mask layer 49, tungsten layer 47, and After the barrier metal layer 45 is selectively etched, the first photoresist layer is removed.

Here, a bit line is formed of the barrier metal layer 45 and the tungsten layer 47.

Subsequently, a second insulating film is formed on the entire surface including the bit line and etched back to form second insulating film sidewalls 51 on both sides of the bit line.

The first insulating layer 43 is selectively removed using the hard mask layer 49 and the second insulating layer sidewall 51 as a mask.

Next, a first polycrystalline silicon layer 53 is formed on the entire surface including the second insulating layer sidewall 51.

As shown in FIG. 2B, a second photosensitive film (not shown) is coated on the first polycrystalline silicon layer 53, and then the second photosensitive film is applied to the lower electrode contact of the capacitor of the cell region and the capacitor of the peripheral region. It is selectively exposed and developed so as to be removed only at the portion where the upper electrode wiring contact is to be formed.

The first polycrystalline silicon layer 53 is selectively etched using the selectively exposed and developed second photoresist layer to form a plug layer 53a, and then the second photoresist layer is removed.

Subsequently, the plug layer 53a is etched flat by the chemical mechanical polishing method with the hard mask layer 49 as an etching end point.

As shown in FIG. 2C, the first oxide film 54 is formed on the entire surface including the plug layer 53a, and the hard mask layer 49 is etched to the end point by the chemical mechanical polishing method. Etch a flat surface.

Subsequently, the nitride film 55 and the second oxide film 56 are sequentially formed on the entire surface including the first oxide film 54, and then the planarization process is performed.

After applying a third photoresist film (not shown) on the second oxide film 56, the third photoresist film is selectively exposed and developed to be removed only at a portion where the lower electrode of the capacitor in the cell region is to be formed. The second oxide film 56 and the nitride film 55 are selectively etched using the selectively exposed and developed third photoresist film as a mask to form a first contact hole, and the third photoresist film is removed.

Subsequently, a liner TiN layer is formed on the exposed plug layer 53a and the second oxide layer 56.

In addition, the TiN layer may be flatly etched by the chemical mechanical polishing method using the second oxide film 56 as an etching end point, and the lower electrode may be separated from each other by the second oxide film 56 and electrically connected to the plug layer 53a. Form 57.

Thereafter, the dielectric film 59 and the fourth photoresist film (not shown) are sequentially formed on the entire surface, and then the fourth photoresist film is selectively exposed and developed so as to remain only in the cell region.

Subsequently, the dielectric layer 59 of the peripheral region is etched using the selectively exposed and developed fourth photoresist layer, and the fourth photoresist layer is removed.

Here, the dielectric film 59 is formed of TaON.

The upper electrode 61 of the capacitor is formed on the entire surface including the dielectric layer 59.

As shown in FIG. 2D, an interlayer insulating layer 63 and a fifth photoresist film (not shown) are sequentially formed on the upper electrode 61, and then the metal wirings in which the fifth photoresist film is contacted with the upper electrode of the peripheral region. It is selectively exposed and developed to be removed only at the site where the contact hole is to be formed.

Subsequently, the interlayer insulating layer 63, the upper electrode 61, and the second oxide layer 56 are selectively etched using the selectively exposed and developed fifth photoresist layer as a mask and the plug layer 53a as an etch stop layer. 2 contact holes 65 are formed, and the fifth photosensitive film is removed.

In the method of manufacturing a semiconductor device according to the second exemplary embodiment of the present invention, as shown in FIG. 3A, the barrier metal layer 45 is insulated from the first insulating layer 43 and on the lower structure 41 in which the cell region and the peripheral region are defined. , A tungsten layer 47, a hard mask layer 49, and a first photosensitive film (not shown) are sequentially formed.

And selectively exposing and developing the first photoresist film so as to remain only in a portion where a bit line is to be formed, and then using the selectively exposed and developed first photoresist film as a mask, the hard mask layer 49, tungsten layer 47, and After the barrier metal layer 45 is selectively etched, the first photoresist layer is removed.

Here, a bit line is formed of the barrier metal layer 45 and the tungsten layer 47.

Subsequently, a second insulating film is formed on the entire surface including the bit line and etched back to form second insulating film sidewalls 51 on both sides of the bit line.

The first insulating layer 43 is selectively removed using the hard mask layer 49 and the second insulating layer sidewall 51 as a mask.

Next, a first polycrystalline silicon layer 53 is formed on the entire surface including the second insulating layer sidewall 51.

As shown in FIG. 3B, a second photosensitive film (not shown) is coated on the first polycrystalline silicon layer 53, and then the second photosensitive film is applied to the lower electrode contact of the capacitor of the cell region and the capacitor of the peripheral region. It is selectively exposed and developed so as to be removed only at the portion where the upper electrode wiring contact is to be formed.

The first polycrystalline silicon layer 53 is selectively etched using the selectively exposed and developed second photoresist layer to form a plug layer 53a, and then the second photoresist layer is removed.

Subsequently, the plug layer 53a is etched flat by the chemical mechanical polishing method with the hard mask layer 49 as an etching end point.

A first oxide film 54 is formed on the entire surface including the plug layer 53a, and the first oxide film 54 is flat-etched by a chemical mechanical polishing method using the hard mask layer 49 as an etching end point. .

Subsequently, the nitride film 55 and the second oxide film 56 are sequentially formed on the entire surface including the first oxide film 54, and then the planarization process is performed.

3C, after applying a third photoresist film (not shown) on the second oxide film 56, and selectively exposing and developing the third photoresist film so as to be removed only above the plug layer 53a. By using the selectively exposed and developed third photoresist film as a mask, the second oxide film 56 and the nitride film 55 are selectively etched to form a first contact hole, and the third photoresist film is removed.

As described above, the first contact hole is also formed above the plug layer 53a in the peripheral region.

Subsequently, a liner TiN layer is formed on the exposed plug layer 53a and the second oxide layer 56.

In addition, the TiN layer may be flatly etched by the chemical mechanical polishing method using the second oxide film 56 as an etching end point, and the lower electrode may be separated from each other by the second oxide film 56 and electrically connected to the plug layer 53a. Form 57.

Thereafter, the dielectric film 59 is formed on the entire surface, and then the upper electrode 61 of the capacitor is formed on the entire surface including the dielectric film 59.

Here, the dielectric film 59 is formed of TaON.

As shown in FIG. 3D, an interlayer insulating layer 63 and a fourth photoresist film (not shown) are sequentially formed on the upper electrode 61, and then the fourth photoresist film is contacted with the upper electrode wiring of the peripheral region. It is selectively exposed and developed so as to be removed only at the site where the wiring contact hole is to be formed.

Subsequently, the interlayer insulating layer 63 is selectively etched using the selectively exposed and developed fourth photoresist layer as the mask, the upper electrode 61 as an etch stop layer, and the second contact hole 65 is formed. Remove the photoresist.

In the method of manufacturing a semiconductor device of the present invention, since an etch-preventive plug layer is first formed on the lower portion of the first metal wire in the peripheral region contacted with the upper electrode of the capacitor, and then the first metal wire is formed on the upper side thereof, the first metal wire is formed. In the process of forming the second metal wiring contacting the metal wiring and the bit line of the peripheral region, the formation of the plug layer prevents the excessive contact hole caused by the excessive etching from the second metal wiring contact hole to the lower conductive layer. Since the occurrence of short between the two metal wirings and the lower conductive layer is suppressed, there is an effect of improving the yield and reliability of the device.

Claims (2)

Providing a lower structure in which a plurality of bit lines including a hard mask layer and an insulating layer spacer are formed, and a cell region and a peripheral region are defined; A plug layer is formed between the lower electrode contact of the capacitor of the cell region and the bit line of the portion where the metal wiring contact to be contacted to the upper electrode of the capacitor of the peripheral region is formed, and a first interlayer insulating layer is formed between the other bit lines. step; Forming a second interlayer insulating film on the entire surface; Forming a capacitor electrically connected to the plug layer in the cell region, and forming a conductive layer for the upper electrode of the capacitor on the second interlayer insulating layer in the peripheral region; Forming a third interlayer insulating film on the entire surface; And etching the third interlayer insulating layer, the conductive layer, and the second interlayer insulating layer by using the plug layer as an etch stop layer to form a metal wiring contact hole contacting the upper electrode of the peripheral region. Method of manufacturing the device. Providing a lower structure in which a plurality of bit lines including a hard mask layer and an insulating layer spacer are formed, and a cell region and a peripheral region are defined; Forming a plug layer between bit lines of a portion where the lower electrode contact of the capacitor of the cell region is to be formed, and forming a first interlayer insulating layer between the other bit lines; Forming a second interlayer insulating film on the entire surface; Removing a second interlayer insulating layer between a portion where a lower electrode contact of the capacitor of the cell region is to be formed and a portion where a metal wiring contact that is to contact the upper electrode of the capacitor of the peripheral region is to be formed; Forming a capacitor electrically connected to the plug layer in the cell region, and a first conductive layer for a lower electrode on a portion where the second interlayer insulating layer of the peripheral region is removed and a second interlayer insulating layer according to the process of forming the capacitor; Forming a second conductive layer for the dielectric film and the upper electrode; Forming a third interlayer insulating film on the entire surface; And etching the third interlayer insulating layer using the second conductive layer as an etch stop layer to form a metal wiring contact hole in contact with an upper electrode of the peripheral region.