KR100395907B1 - Method for forming the line of semiconductor device - Google Patents
Method for forming the line of semiconductor device Download PDFInfo
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- KR100395907B1 KR100395907B1 KR10-2001-0027052A KR20010027052A KR100395907B1 KR 100395907 B1 KR100395907 B1 KR 100395907B1 KR 20010027052 A KR20010027052 A KR 20010027052A KR 100395907 B1 KR100395907 B1 KR 100395907B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 배선 형성방법에 관한 것으로, 특히 반도체소자들 간의 연결을 위한 배선 형성 방법에 있어서, 상위층 콘택홀과 하위층 콘택홀이 적층 구조로 연결 시, 이중 다마신 (Dual Damascene) 기술을 사용하여, 상기 두 콘택홀 사이의 패드 금속층을 형성하지 않고 콘택홀 플러그 형태로서만 연결함으로써 단위면적당 패턴의 밀집도를 향상시켜 칩 면적의 증가를 방지하고 반도체소자를 고집적화 시킬 수 있는 매우 유용하고 효과적인 장점을 지닌 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device. In particular, in a method of forming a wiring for connecting semiconductor devices, a dual damascene technique is used when an upper layer contact hole and a lower layer contact hole are connected in a stacked structure. By using only the contact hole plug form without forming the pad metal layer between the two contact holes, the density of the pattern per unit area can be improved to prevent the increase of the chip area and the high integration of the semiconductor device. It relates to an invention having.
Description
본 발명은 반도체소자의 배선 형성방법에 관한 것으로, 보다 상세하게는 상위층 콘택홀과 하위층 콘택홀이 적층 구조로 연결 시, 이중 다마신 (Dual Damascene) 기술을 사용하여, 상기 두 콘택홀 사이의 패드 금속층을 형성하지 않고 콘택홀 플러그 형태로서만 연결하는 반도체소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and more particularly, when a upper layer contact hole and a lower layer contact hole are connected in a stacked structure, a pad between the two contact holes using a dual damascene technique. The present invention relates to a method for forming a wiring of a semiconductor device in which only a contact hole plug is connected without a metal layer.
최근 반도체소자가 점차적으로 고집적화 됨에 따라 배선과 배선 사이의 고집적화가 진행됨에 따라 콘택홀 형성 뿐만 아니라 반도체 기판 상에 배선의 넓이에 관한 문제가 크게 대두되고 있다.In recent years, as semiconductor devices have been increasingly integrated, as the integration between the wirings and the wiring proceeds, not only the contact hole formation but also the problem of the width of the wiring on the semiconductor substrate is increasing.
도 1a 내지 도 1e는 종래 반도체소자의 금속배선 형성방법을 순차적으로 나타낸 단면도이다.1A through 1E are cross-sectional views sequentially illustrating a method of forming metal wirings of a conventional semiconductor device.
도 1a에 도시된 바와 같이, 소정의 하부구조를 가지고 있는 반도체기판(10) 상에 콘택홀이 형성되기 전에 제1산화막(20)과 질화막(30) 및 제2산화막(40)을 순차적으로 적층한다.As shown in FIG. 1A, before the contact hole is formed on the semiconductor substrate 10 having a predetermined substructure, the first oxide film 20, the nitride film 30, and the second oxide film 40 are sequentially stacked. do.
그리고, 도 1b에 도시된 바와 같이, 상기 제2산화막(40) 상부에 텅스텐 배선 형성부위와 텅스텐 패드 형성부위가 형성되도록 제1감광막(50)을 도포하여 제2산화막(40)을 식각한다.As shown in FIG. 1B, the second oxide film 40 is etched by applying the first photoresist film 50 to form a tungsten wiring forming portion and a tungsten pad forming portion on the second oxide film 40.
이어서, 도 1c에 도시된 바와 같이, 상기 제1감광막(50)을 제거한 후, 제2감광막(55)을 도포하여 콘택홀 식각공정을 진행함으로써 콘택홀(58)을 형성한다.Subsequently, as shown in FIG. 1C, after the first photoresist film 50 is removed, the second photoresist film 55 is applied to form a contact hole 58 by performing a contact hole etching process.
도 1d에 도시된 바와 같이, 상기 제2감광막(55)을 제거한 후, 결과물 전체에제1장벽금속층(60)과 제1텅스텐막(70)을 순차적으로 적층한다.As shown in FIG. 1D, after the second photosensitive film 55 is removed, the first barrier metal layer 60 and the first tungsten film 70 are sequentially stacked on the entire product.
그리고, 상기 제2산화막(40) 상부까지 화학기계적 연마공정을 진행하여 제1텅스텐배선(75)과 제1텅스텐 패드(70)를 형성한다.In addition, a chemical mechanical polishing process is performed to the upper portion of the second oxide film 40 to form the first tungsten wiring 75 and the first tungsten pad 70.
계속하여, 도 1e에 도시된 바와 같이, 상기 결과물 상에 제3산화막(80)을 적층한 후 콘택식각 공정을 진행하여 콘택홀(미도시함)을 형성한다.Subsequently, as shown in FIG. 1E, after the third oxide layer 80 is stacked on the resultant, a contact etching process is performed to form a contact hole (not shown).
그리고, 상기 결과물 상에 콘택홀(미도시함)에 제2장벽금속층(90)과 제2텅스텐(95)이 매립되도록 적층함으로써 상부 전극을 형성하여 하부 전극인 제1텅스텐배선과 제1텅스텐 패드가 "A"와 같이 연결된다In addition, the upper electrode is formed by stacking the second barrier metal layer 90 and the second tungsten 95 in the contact hole (not shown) on the resultant to form the upper electrode and the first tungsten wiring and the first tungsten pad. Is connected as "A"
그런데, 상기와 같은 종래 반도체소자의 배선 형성방법을 이용하게 되면, 상부 전극과 하부의 콘택홀이 서로 접하는 부위가 "A"와 같이 제1텅스텐 패드가 후속 포토레지스트 공정에 있어서, 콘택 정렬 시, 오차를 고려하여 제1텅스텐 패드를 넓게 형성하였으며, 그 결과 단위면적당 패턴의 밀집도가 낮아져 칩 면적이 증가되는 문제점이 있었다.However, when the above-described conventional method for forming a semiconductor device wiring is used, the first tungsten pad may be contacted in the subsequent photoresist process, such as "A", where the upper electrode and the lower contact hole contact each other. The first tungsten pad was formed in consideration of the error, and as a result, the density of the pattern per unit area was lowered, resulting in an increase in chip area.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 반도체소자들 간의 연결을 위한 배선 형성 방법에 있어서, 이중 다마신 (Dual Damascene) 기술을 사용하여 상위층 콘택홀과 하위층 콘택홀이 적층 구조로 연결할 때, 상기 두 콘택홀 사이의 패드 금속층을 형성하지 않고 콘택홀 플러그 형태로서만 연결함으로써 단위면적당 패턴의 밀집도를 향상시켜 칩 면적의 증가를 방지하고 반도체소자를 고집적화 시키는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a wiring for connection between semiconductor devices, using a dual damascene technology to form upper layer contact holes and lower layer contacts. When holes are connected in a stacked structure, the pad metal layer is not formed between the two contact holes, but only in the form of contact hole plugs, thereby improving the compactness of the pattern per unit area, thereby preventing an increase in chip area and increasing integration of semiconductor devices. to be.
도 1a 내지 도 1e는 종래 반도체소자의 금속배선 형성방법을 순차적으로 나타낸 단면도이다.1A through 1E are cross-sectional views sequentially illustrating a method of forming metal wirings of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 배선 형성방법을 순차적으로 나타낸 단면도이다.2A to 2E are cross-sectional views sequentially illustrating a wiring forming method of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
110 : 반도체기판 120 : 제1산화막110: semiconductor substrate 120: first oxide film
130 : 식각정지막 140 : 제2산화막130: etch stop film 140: second oxide film
150 : 제1감광막 155 : 제2감광막150: first photosensitive film 155: second photosensitive film
160 : 제1장벽금속층 170 : 금속플러그160: first barrier metal layer 170: metal plug
175 : 제1텅스텐배선 180 : 제3산화막175: first tungsten wiring 180: third oxide film
190 : 제2장벽금속막 195 : 제2텅스텐막190: second barrier metal film 195: second tungsten film
상기 목적을 달성하기 위하여, 본 발명은 반도체기판 상에 제1산화막과 식각정지막 및 제2산화막을 순차적으로 적층하는 단계와; 상기 제2산화막 상부에 텅스텐 배선 형성부위가 형성되도록 제1감광막을 도포하여 제2산화막을 식각하는 단계와; 상기 제1감광막을 제거한 후, 제2감광막을 도포하여 콘택홀 식각공정을 진행함으로써 하위층 콘택홀을 형성하는 단계와; 상기 제2감광막을 제거한 후, 상기 하위층 콘택홀이 매립되도록 상기 결과물 전체에 장벽금속층과 제1텅스텐막을 순차적으로 적층한 후, 화학기계적 연마공정을 진행하여 평탄화하는 단계와; 상기 결과물 상에 제3산화막을 적층한 후 콘택식각 공정을 진행하여 상위층 콘택홀을 형성하여 상기 하위층 콘택홀과 연결하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 배선 형성방법을 제공한다In order to achieve the above object, the present invention comprises the steps of sequentially stacking a first oxide film, an etch stop film and a second oxide film on a semiconductor substrate; Etching the second oxide film by applying a first photosensitive film to form a tungsten wiring forming portion on the second oxide film; Removing the first photoresist film and then applying a second photoresist film to form a lower layer contact hole by performing a contact hole etching process; Removing the second photoresist film, sequentially depositing a barrier metal layer and a first tungsten film on the entire product to fill the lower layer contact hole, and then performing a chemical mechanical polishing process to planarize the film; And depositing a third oxide film on the resultant to perform a contact etching process to form an upper layer contact hole and to connect the lower layer contact hole to the interconnection forming method of the semiconductor device.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 배선 형성방법을 순차적으로 나타낸 단면도이다.2A to 2E are cross-sectional views sequentially illustrating a wiring forming method of a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 소정의 하부구조를 가지고 있는 반도체기판(110) 상에 콘택홀을 형성하기 전에 절연체로서 제1산화막(120)과 식각정지막(130) 및제2산화막(140)을 순차적으로 적층한다.As shown in FIG. 2A, before forming contact holes on the semiconductor substrate 110 having a predetermined substructure, the first oxide layer 120, the etch stop layer 130, and the second oxide layer 140 are formed as insulators. Laminate sequentially.
그리고, 도 2b에 도시된 바와 같이, 상기 제2산화막(140) 상부에 텅스텐 배선 형성부위가 형성되도록 제1감광막(150)을 도포한 후, 상기 제1감광막(150)을 마스크로 하여 제2산화막(140)을 식각한다.As shown in FIG. 2B, after the first photosensitive film 150 is coated to form a tungsten wiring forming portion on the second oxide film 140, the second photosensitive film 150 is used as a mask. The oxide film 140 is etched.
이때, 상기 제2산화막(140) 식각 시, 하부 식각정지막(130)에 의하여 식각정지막(130)까지만 식각되어 제1산화막(120)이 오버 식각되는 것이 방지된다.In this case, when the second oxide layer 140 is etched, only the etch stop layer 130 is etched by the lower etch stop layer 130, thereby preventing over-etching of the first oxide layer 120.
이어서, 도 2c에 도시된 바와 같이, 상기 제1감광막(150)을 제거한 후, 제1감광막(150)이 제거된 결과물 상에 제2감광막(155)을 도포한다.Subsequently, as shown in FIG. 2C, after the first photoresist film 150 is removed, the second photoresist film 155 is coated on the resultant from which the first photoresist film 150 is removed.
그리고, 상기 제2감광막(155)을 마스크로 하여 반도체기판(110) 상부까지 하위층 콘택홀 식각공정을 진행하여 하위층 콘택홀(158)을 형성한다.The lower layer contact hole 158 is formed by etching the lower layer contact hole to the upper portion of the semiconductor substrate 110 using the second photoresist layer 155 as a mask.
도 2d에 도시된 바와 같이, 상기 제2감광막(155)을 제거한 후, 제2감광막(155)이 제거된 결과물 전체에 제1장벽금속층(160)과 제1텅스텐막(미도시함)을 순차적으로 하위층 콘택홀(158)을 매립하여 하위층 금속플러그(170)와 제1텅스텐배선(175)을 형성한다.As shown in FIG. 2D, after the second photoresist film 155 is removed, the first barrier metal layer 160 and the first tungsten film (not shown) are sequentially disposed on the entire product from which the second photoresist film 155 is removed. The lower layer contact hole 158 is buried to form the lower layer metal plug 170 and the first tungsten wiring 175.
그리고, 상기 결과물에서 상기 하위층 금속플러그(170) 상부까지 화학기계적 연마공정을 진행하여 금속플러그(170)와 제1텅스텐배선(175)이 평탄하게 대기에 노출되도록 한다.In addition, a chemical mechanical polishing process is performed to the upper portion of the lower layer metal plug 170 so that the metal plug 170 and the first tungsten wiring 175 are flatly exposed to the atmosphere.
계속하여, 도 2e에 도시된 바와 같이, 상기 결과물 상에 상위층 콘택홀을 형성하기 위하여 제3산화막(180)을 적층한 후 콘택식각 공정을 진행하여 상위층 콘택홀(미도시함)을 형성한다.Subsequently, as shown in FIG. 2E, the third oxide layer 180 is stacked to form the upper layer contact hole on the resultant, and then a contact etching process is performed to form the upper layer contact hole (not shown).
이때, 상기 상위층 콘택홀 식각(미도시함)에 있어서, 하위층 금속플러그(170)을 벗어나 식각 될 때, 상기 하부 식각정지막(130)인 질화막에 의하여 식각이 정지되어 하위층 금속플러그(170)과 후속 공정에 의해 형성될 상위층 금속플러그를 연결할 때, 여분의 패드 금속층을 형성하지 않고서 불량을 방지 할 수 있다.At this time, in the upper layer contact hole etching (not shown), when the etching is out of the lower layer metal plug 170, the etching is stopped by the nitride film which is the lower etch stop layer 130 and the lower layer metal plug 170 and When connecting the upper layer metal plug to be formed by the subsequent process, failure can be prevented without forming an extra pad metal layer.
그리고, 상기 결과물 상에 제2장벽금속막(190)과 제2텅스텐막(미도시함)을 적층함으로써 상위층 금속플러그(195)를 형성하여 하위층 금속플러그(170)와 상위층 금속플러그(195)이 "A"와 같이 종래에 형성되던 패드 금속층을 형성하지 않고 상·하위층 금속플러그 형태로서만 연결한다.In addition, by stacking the second barrier metal film 190 and the second tungsten film (not shown) on the resultant, the upper metal plug 195 is formed to form the lower metal plug 170 and the upper metal plug 195. It connects only in the form of upper and lower metal plugs without forming the pad metal layer conventionally formed as "A".
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 배선 형성방법을 이용하게 되면, 이중 다마신 (Dual Damascene) 기술을 사용하여 상위층 콘택홀과 하위층 콘택홀이 적층 구조로 연결할 때, 상기 두 콘택홀 사이의 패드 금속층을 형성하지 않고 콘택홀 플러그 형태로서만 연결함으로써 단위면적당 패턴의 밀집도를 향상시켜 칩 면적의 증가를 방지하고 반도체소자를 고집적화 시킬 수 있다.Therefore, as described above, when the method for forming a wiring of a semiconductor device according to the present invention is used, when the upper layer contact hole and the lower layer contact hole are connected in a stacked structure by using a dual damascene technique, the two contacts are stacked. By connecting only in the form of a contact hole plug without forming a pad metal layer between the holes, the density of the pattern per unit area can be improved to prevent an increase in chip area and to increase the integration of semiconductor devices.
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|---|---|---|---|---|
| US5635423A (en) * | 1994-10-11 | 1997-06-03 | Advanced Micro Devices, Inc. | Simplified dual damascene process for multi-level metallization and interconnection structure |
| KR19990062003A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Method of forming multilayer metal wiring in semiconductor device |
| KR100223284B1 (en) * | 1995-05-04 | 1999-10-15 | 김영환 | Semiconductor element metal line manufacturing method |
| JP2001053151A (en) * | 1999-08-17 | 2001-02-23 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method of the same |
| KR20010112688A (en) * | 2000-06-10 | 2001-12-21 | 황인길 | Method for forming metal line |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635423A (en) * | 1994-10-11 | 1997-06-03 | Advanced Micro Devices, Inc. | Simplified dual damascene process for multi-level metallization and interconnection structure |
| KR100223284B1 (en) * | 1995-05-04 | 1999-10-15 | 김영환 | Semiconductor element metal line manufacturing method |
| KR19990062003A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Method of forming multilayer metal wiring in semiconductor device |
| JP2001053151A (en) * | 1999-08-17 | 2001-02-23 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method of the same |
| KR20010112688A (en) * | 2000-06-10 | 2001-12-21 | 황인길 | Method for forming metal line |
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