KR100315849B1 - a forming method of a contact for multi-level interconnects - Google Patents

a forming method of a contact for multi-level interconnects Download PDF

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KR100315849B1
KR100315849B1 KR1019990016820A KR19990016820A KR100315849B1 KR 100315849 B1 KR100315849 B1 KR 100315849B1 KR 1019990016820 A KR1019990016820 A KR 1019990016820A KR 19990016820 A KR19990016820 A KR 19990016820A KR 100315849 B1 KR100315849 B1 KR 100315849B1
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film
layer
contact
pattern
buffer insulating
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KR20000073502A (en
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박태희
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황인길
아남반도체 주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]

Abstract

제1 배선층 위에 층간 절연막을 형성하고 평탄화한 다음, 이를 패터닝하여 제1 배선층의 일정 영역이 드러나도록 콘택 홀을 형성한다. 다음, 베리어 금속층을 형성하고, 플러그용 텅스텐막과 질화막을 연속적으로 증착한 다음, 질화막 또는 산화막 등의 버퍼층을 형성한다. 그 위에 감광막을 도포하고 패터닝하여, 콘택 홀에 대응되는 부분의 질화막 위에 감광막 패턴을 형성한다. 이 감광막 패턴을 식각 마스크로 하여 버퍼층을 등방성 건식 식각하여 테이퍼 형태의 버퍼층 패턴을 콘택 홀 상부에 형성한다. 이후, 감광막 패턴을 제거하고, 버퍼층 패턴과 그 하부의 텅스텐막을 베리어 금속층이 드러날 때까지 에치 백한다. 이때, 버퍼층 패턴은 제거되고 콘택부에서의 텅스텐막의 표면은 베리어 금속층의 표면과 평행이 되도록 함으로써, 이후 상부 제2 배선층과의 접촉이 안정적으로 이루어질 수 있도록 한다.An interlayer insulating layer is formed and planarized on the first wiring layer, and then patterned to form a contact hole so that a predetermined region of the first wiring layer is exposed. Next, a barrier metal layer is formed, a tungsten film for plug and a nitride film are deposited successively, and a buffer layer such as a nitride film or an oxide film is formed. The photoresist film is applied and patterned thereon to form a photoresist pattern on the nitride film of the portion corresponding to the contact hole. Using the photoresist pattern as an etch mask, the buffer layer is isotropically dry-etched to form a tapered buffer layer pattern over the contact hole. Thereafter, the photoresist layer pattern is removed, and the buffer layer pattern and the tungsten layer under it are etched back until the barrier metal layer is exposed. At this time, the buffer layer pattern is removed and the surface of the tungsten film in the contact portion is parallel to the surface of the barrier metal layer, thereby allowing stable contact with the upper second wiring layer.

Description

다층 배선의 콘택 형성 방법{a forming method of a contact for multi-level interconnects}A forming method of a contact for multi-level interconnects}

본 발명은 다층 배선의 콘택(contact) 형성 방법에 관한 것으로서, 보다 상세하게는 서로 다른 층에 위치하는 실리콘 기판과 배선, 또는 배선과 배선을 전기적으로 연결시켜 주기 위한 콘택 또는 비아(via)의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact of a multi-layered wiring, and more particularly, to forming a silicon substrate and wiring located on different layers or a contact or via for electrically connecting the wiring and the wiring. It is about a method.

최근, 반도체 집적회로가 고집적화 됨에 따라 제한된 면적 내에서 배선과 배선을 효과적으로 연결하는 방법들이 제시되고 있다. 그 중, 집적 회로에서의 배선을 다층화하는 다층 배선 방법이 주로 사용되고 있는데, 반도체 소자간에 배선이 통과되는 공간을 고려할 필요가 없기 때문에 반도체 소자의 크기를 작게 가져갈 수있다. 이러한 다층 배선 구조에서는 각 층 간에 존재하는 콘택 또는 비아의 수가 매우 많으며, 이들은 서로 도통하므로, 아주 낮은 콘택 저항값을 가지고 있어야 한다.Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. Since it is not necessary to consider a space through which wiring passes between semiconductor elements, the size of the semiconductor element can be reduced. In such a multi-layered wiring structure, the number of contacts or vias existing between the layers is very large, and since they are conductive with each other, they must have a very low contact resistance value.

그러면, 도 1a 내지 도 1c를 참고로 하여 종래의 기술에 따른 콘택 형성 방법에 대하여 설명한다. 여기서는 편의상, 배선 간의 연결부인 비아(via)를 콘택의 범위에 포함시켜 콘택으로 지칭하여 설명하겠다.Next, a contact forming method according to the related art will be described with reference to FIGS. 1A to 1C. For convenience, a via, which is a connection portion between wirings, is included in a range of a contact and will be referred to as a contact.

먼저, 실리콘 웨이퍼(10) 위에 제1 배선층(20)을 형성하고, 그 위에 TEOS(thetraethyle orthosilicate)막 및/또는 BPSG막 등으로 층간 절연막(30)을 형성한 다음, 기계 화학적 연막(chemical mechanical polishing)을 실시하여 층간 절연막(30)을 평탄화한다. 다음, 층간 절연막(30)을 패터닝하여 제1 배선층(20)의 일정 영역이 드러나도록 콘택 홀(contact hole)을 형성한다.First, the first wiring layer 20 is formed on the silicon wafer 10, an interlayer insulating film 30 is formed thereon with a tetraethyle orthosilicate (TEOS) film and / or a BPSG film, and then a mechanical mechanical polishing ) To planarize the interlayer insulating film 30. Next, the interlayer insulating layer 30 is patterned to form a contact hole so that a predetermined region of the first wiring layer 20 is exposed.

이후, 도 1a에 도시한 바와 같이, 티타늄(Ti)/질화티타늄(TiN)을 증착하여 베리어 금속층(40)을 형성하고, 플러그(plug)용 금속막인 텅스텐막(50)을 연속적으로 형성한다.Thereafter, as shown in FIG. 1A, a barrier metal layer 40 is formed by depositing titanium (Ti) / titanium nitride (TiN), and a tungsten film 50 that is a plug metal film is continuously formed. .

다음, 도 1b에 도시한 바와 같이, 텅스텐막(50)을 에치 백(etch back)하여 플러그(51)를 형성한다. 이때, 하부 막질인 베리어 금속층(40)이 충분히 드러나도록 하기 위해 텅스텐막(50)을 오버 에치(over etch)하므로, 플러그(51)가 콘택홀 안쪽으로 우묵하게 패이는 현상인 리세스(recess)가 발생한다.Next, as shown in FIG. 1B, the tungsten film 50 is etched back to form a plug 51. At this time, since the tungsten film 50 is over etched so that the lower barrier metal layer 40 is sufficiently exposed, the plug 51 recesses into the contact hole. Occurs.

따라서, 도 1c에서와 같이, 제2 배선층을 형성하기 위해 알루미늄(Al)막(60)을 증착할 경우, 플러그(51)의 리세스가 발생한 부근에서 알루미늄막(60)의 적층프로파일(profile)이 불량해진다.Therefore, as shown in FIG. 1C, when the aluminum (Al) film 60 is deposited to form the second wiring layer, a lamination profile of the aluminum film 60 near the recess of the plug 51 occurs. This becomes bad.

플러그(51)의 리세스가 심한 경우에는, 도 2에 도시한 바와 같이, 알루미늄막(60)에 보이드(void)가 발생하기도 한다.When the recess of the plug 51 is severe, voids may occur in the aluminum film 60, as shown in FIG.

이상에서 설명한 바와 같이, 종래의 기술에 따른 반도체 소자의 콘택 형성 방법에서는, 플러그의 리세스에 의해 상부의 배선층의 적층 프로파일이 나쁘게 형성되기 때문에, 접촉이 불안정해지고 저항이 증가하여 직류 파라미터 (DC parameter) 측정 시에 저항이 기준치를 벗어나게 된다. 결국, 반도체 칩(chip)이 작동하지 않게 된다.As described above, in the conventional method for forming a contact of a semiconductor device, since the laminated profile of the upper wiring layer is badly formed by the recess of the plug, the contact becomes unstable and the resistance increases, so that the DC parameter (DC parameter In the measurement, the resistance is out of the reference value. As a result, the semiconductor chip does not work.

본 발명은 이러한 문제점을 해결하기 위한 것으로서, 그 과제는 콘택 근처에서의 배선층의 프로파일을 개선하여 저항치를 감소시키는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and its task is to reduce the resistance by improving the profile of the wiring layer near the contact.

본 발명의 다른 과제는 미스 얼라인 발생이 콘택 형성 및 이후 콘택 특성에 영향을 미치지 않도록 공정 마진을 확보하는 것이다.Another object of the present invention is to secure process margins so that misalignment does not affect contact formation and subsequent contact characteristics.

도 1a 및 도 1c는 종래의 기술에 따른 다층 배선의 콘택 형성 방법을 공정 순서에 따라 도시한 단면도이고,1A and 1C are cross-sectional views illustrating a method for forming a contact of a multilayer wiring according to a prior art according to a process sequence;

도 2는 종래의 기술에 따른 다층 배선의 콘택을 나타낸 단면도이고,2 is a cross-sectional view showing a contact of a multilayer wiring according to the prior art,

도 3a 내지 도 3d, 그리고 도 4a 및 도 4b는 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 도시한 단면도이다.3A to 3D and FIGS. 4A and 4B are cross-sectional views illustrating a method for forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention.

이러한 과제를 해결하기 위해서, 본 발명에 따른 다층 배선의 콘택 형성 방법에서는 콘택 홀 및 그 상부의 베리어 금속층이 형성되어 있는 전체 구조 상에 플러그용 금속막과 버퍼 절연막을 연속하여 증착하고, 버퍼 절연막을 등방성 건식 식각 방식으로 패터닝하여 콘택홀 상부에 가장자리가 경사진 테이퍼 형태의 버퍼 절연막 패턴을 형성한 다음, 버퍼 절연막 패턴 및 플러그용 금속막을 에치 백하여 버퍼 절연막 패턴은 제거하고 플러그용 금속막은 그 표면이 베리어 금속층의 표면과평행하게 일치하는 정도까지 식각함으로써, 표면 프로파일이 양호한 플러그를 형성한다.In order to solve such a problem, in the contact forming method of the multilayer wiring according to the present invention, the plug metal film and the buffer insulating film are successively deposited on the entire structure in which the contact hole and the barrier metal layer thereon are formed, and the buffer insulating film is Patterned by an isotropic dry etching method to form a tapered buffer insulating film pattern on the top of the contact hole, and then etched back the buffer insulating film pattern and the plug metal film to remove the buffer insulating film pattern and the surface of the plug metal film By etching to a degree parallel to the surface of the barrier metal layer, a plug having a good surface profile is formed.

여기에서, 플러그를 통해 하부 제1 도전층과 연결되는 상부 제2 도전층을 플러그 상부에 형성할 수 있다.Here, an upper second conductive layer connected to the lower first conductive layer through the plug may be formed on the upper portion of the plug.

플러그의 표면을 베리어 금속층의 표면과 일치시키기 위해, 버퍼 절연막과 플러그용 금속막의 선택비에 따라 버퍼 절연막의 두께를 조절하는 것이 바람직하다. 이때, 베리어 금속층으로는 Ti/TiN으로 형성할 수 있다.In order to match the surface of the plug with the surface of the barrier metal layer, it is preferable to adjust the thickness of the buffer insulating film in accordance with the selection ratio between the buffer insulating film and the plug metal film. In this case, the barrier metal layer may be formed of Ti / TiN.

또한, 버퍼 절연막은 질화막 또는 산화막으로 형성할 수 있는데, 질화막인 경우는 등방성 건식 식각에 SF6계열의 식각 기체를 사용하고, 산화막인 경우는 CF4또는 C4F8의 식각 기체를 사용할 수 있다.In addition, the buffer insulating film may be formed of a nitride film or an oxide film. In the case of the nitride film, SF 6 series etching gas may be used for isotropic dry etching, and in the case of the oxide film, CF 4 or C 4 F 8 etching gas may be used. .

그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Next, a method of forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the contact.

도 3a 내지 도 3d는 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 공정 순서에 따라 도시한 단면도이다.3A to 3D are cross-sectional views illustrating a method for forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention in a process sequence.

먼저, 종래의 기술에서와 마찬가지로, 실리콘 웨이퍼(10) 위에 제1 배선층(20)을 형성하고, 그 위에 TEOS막 및/또는 BPSG막 등으로 층간 절연막(30)을 형성한 다음, 기계 화학적 연막을 실시하여 층간 절연막(30)을 평탄화한다. 다음, 감광막(도시하지 않음)을 도포하고, 층간 절연막(30)을 패터닝하여 제1 배선층(20)의 일정 영역이 드러나도록 콘택 홀을 형성한다.First, as in the prior art, the first wiring layer 20 is formed on the silicon wafer 10, and the interlayer insulating film 30 is formed thereon with a TEOS film and / or a BPSG film. The planarization of the interlayer insulating film 30 is performed. Next, a photoresist film (not shown) is applied, and the interlayer insulating film 30 is patterned to form a contact hole so that a predetermined region of the first wiring layer 20 is exposed.

이후, 도 3a에 도시한 바와 같이, 티타늄(Ti)/질화티타늄(TiN)으로 베리어 금속층(40)을 형성한 다음, 플러그(plug)용 금속막인 텅스텐막(50)과 질화막(70)을 연속적으로 증착한다. 이때, 질화막(70) 대신 산화막을 증착하는 것도 가능하다.Thereafter, as shown in FIG. 3A, the barrier metal layer 40 is formed of titanium (Ti) / titanium nitride (TiN), and then the tungsten film 50 and the nitride film 70, which are plug metal films, are formed. Deposit continuously. In this case, an oxide film may be deposited instead of the nitride film 70.

이어, 감광막을 도포하고 패터닝하여, 도 3b에 도시한 바와 같이, 콘택 홀에 대응되는 부분의 질화막(70) 위에 감광막 패턴(81)을 형성한다.Subsequently, the photosensitive film is coated and patterned to form a photosensitive film pattern 81 on the nitride film 70 in the portion corresponding to the contact hole, as shown in FIG. 3B.

다음, 감광막 패턴(81)을 식각 마스크로 하여 하부에 놓인 질화막(70)을 SF6계열 등의 식각 기체를 이용한 등방성 건식 식각하여, 도 3c에서와 같이 패턴의 가장자리가 경사진 테이퍼(taper) 형태의 질화막 패턴(71)을 콘택 홀 상부에 형성한다. 이후, 감광막 패턴(81)을 스트립(strip) 방식으로 제거한다.Next, an isotropic dry etching of the nitride film 70 disposed below using the photoresist pattern 81 as an etching mask is performed using an etching gas such as SF 6 series, and a tapered shape in which the edge of the pattern is inclined as shown in FIG. 3C. The nitride film pattern 71 is formed on the contact hole. Thereafter, the photoresist pattern 81 is removed by a strip method.

도 3d에 도시한 바와 같이, 질화막 패턴(71)과 그 하부의 텅스텐막(50)을 베리어 금속층(40)이 드러날 때까지 에치 백하여 콘택부의 플러그(52)를 형성한다. 이때, 서로 질화막 패턴(71)과 텅스텐막(50) 사이의 식각 선택비에 따라 질화막 패턴(71)의 두께를 적절히 조절해 주어 텅스텐막(50)이 콘택 홀 안쪽으로 과도하게 식각되지 않도록 하며, 질화막 패턴(71)이 제거되고 콘택부에서의 텅스텐막(50)의 표면이 베리어 금속층(41)의 표면과 평행이 되는 시점에서 식각을 정지하여야 한다. 한편, 식각 시간은 질화막 패턴(71)과 텅스텐막(50)의 식각 선택비에 따라 조절되며, 베리어 금속층(41) 위에는 텅스텐막(50)이 잔류하지 않도록 50% 이상의 오버 에치가 가능하다.As shown in FIG. 3D, the nitride film pattern 71 and the tungsten film 50 under the etch are etched back until the barrier metal layer 40 is exposed to form the plug 52 of the contact portion. At this time, the thickness of the nitride film pattern 71 is appropriately adjusted according to the etching selectivity between the nitride film pattern 71 and the tungsten film 50 so that the tungsten film 50 is not excessively etched into the contact hole. The etching must be stopped when the nitride film pattern 71 is removed and the surface of the tungsten film 50 at the contact portion becomes parallel with the surface of the barrier metal layer 41. On the other hand, the etching time is adjusted according to the etching selectivity of the nitride film pattern 71 and the tungsten film 50, it is possible to over-etch more than 50% so that the tungsten film 50 does not remain on the barrier metal layer 41.

이후, 제2 배선층을 형성하기 위한 알루미늄막(도시하지 않음)을 증착한다.Thereafter, an aluminum film (not shown) for forming the second wiring layer is deposited.

이와 같이 플러그(52)의 표면이 베리어 금속층(41)의 표면과 일치하도록 형성된 콘택부 상부에 제2 배선층을 형성할 경우, 콘택의 저항이 크게 감소한다. 따라서, 반도체 칩의 작동 특성의 저하를 막을 수 있다.Thus, when the second wiring layer is formed on the contact portion formed so that the surface of the plug 52 coincides with the surface of the barrier metal layer 41, the resistance of the contact is greatly reduced. Therefore, the fall of the operating characteristic of a semiconductor chip can be prevented.

또한, 본 발명의 실시예에서와 같이 질화막 패턴(71)을 테이퍼 형태로 형성하는 경우, 공정 마진에 있어서도 유리하다. 이에 대하여, 도 4a 및 도 4b를 참고로 하여, 다음에서 좀 더 설명한다.In addition, in the case of forming the nitride film pattern 71 in the tapered form as in the embodiment of the present invention, it is also advantageous in the process margin. This will be described further below with reference to FIGS. 4A and 4B.

도 4a 및 도 4b는 앞서 설명했던 본 발명의 실시예에 따른 콘택 형성 방법의 감광막 패턴(81)의 형성 단계에서 미스 얼라인먼트가 발생한 경우를 보여주는 단면도이다.4A and 4B are cross-sectional views illustrating a case in which misalignment occurs in the formation of the photoresist pattern 81 of the contact forming method according to the embodiment of the present invention.

반도체 소자가 미세화되고 배치 간격이 좁아지면서 패턴의 미스 얼라인먼트가 자주 발생한다. 도 4a에 도시한 바와 같이, 감광막 패턴(81)이 콘택 홀의 한쪽 가장자리로부터 일정 간격(ΔS1) 만큼 이격되어 패터닝되는 경우라도, 본 발명의 실시예에서와 같이 등방성 건식 식각을 실시하여 하부의 질화막(70)을 식각하면, 도 4b에 도시한 바와 같이, 질화막 패턴(71)이 테이퍼 형태로 패터닝이 되며 질화막 패턴(71)의 아래쪽은 감광막 패턴(81)의 가장자리 보다 일정 간격(ΔS2) 바깥쪽으로 놓이게 된다. 이 간격(ΔS2)은 감광막 패턴(81)이 이격된 간격(ΔS1)과 같거나 넓도록 조절될 수 있다.As semiconductor devices become finer and arrangement intervals become narrower, misalignment of patterns frequently occurs. As shown in FIG. 4A, even when the photoresist pattern 81 is patterned to be spaced apart from one edge of the contact hole by a predetermined interval ΔS1, an isotropic dry etching is performed as in the exemplary embodiment of the present invention to provide a lower nitride film ( When the 70 is etched, as shown in FIG. 4B, the nitride film pattern 71 is patterned in a tapered shape, and the lower portion of the nitride film pattern 71 is positioned outside a predetermined interval ΔS2 from the edge of the photoresist pattern 81. do. The interval ΔS2 may be adjusted to be equal to or wider than the interval ΔS1 in which the photoresist pattern 81 is spaced apart.

다음, 이와 같이 형성된 질화막 패턴(81)과 텅스텐막(40)을 도 3d에서와 동일한 방법으로 에치 백하여 텅스텐 플러그(52)를 형성하고, 그 위에 알루미늄막을증착하여 콘택을 완성한다.Next, the nitride film pattern 81 and the tungsten film 40 thus formed are etched back in the same manner as in FIG. 3D to form a tungsten plug 52, and an aluminum film is deposited thereon to complete the contact.

이처럼 질화막 패턴(71)을 등방성 건식 식각으로 테이퍼 처리하는 본 발명의 실시예에서는, 질화막 패턴(71)의 아래쪽 폭이 상대적으로 넓어지기 때문에 이후의 텅스텐막(70) 및 질화막 패턴(71)의 식각 시에 미스 얼라인된 폭 만큼의 패턴 폭의 보상이 이루어진다.As described above, in the embodiment of the present invention in which the nitride film pattern 71 is tapered by isotropic dry etching, the lower width of the nitride film pattern 71 becomes relatively wider, so that the subsequent etching of the tungsten film 70 and the nitride film pattern 71 is performed. Compensation of the pattern width by the misaligned width at the time is performed.

이상에서와 같이, 본 발명에서는 텅스텐막 상부에 질화막을 두고 질화막을 이방성 건식 식각으로 패터닝하여 테이퍼 처리하며, 이후 질화막 패턴과 텅스텐막을 베리어 금속층 표면에 이루도록 평탄하게 식각함으로써, 콘택 근처에서의 배선층의 형태를 개선하여 접촉 저항치를 감소시킬 뿐만 아니라, 미스 얼라인이 발생하더라도 테이퍼 하부 부분에 의해 공정 마진을 확보되는 효과가 있다. 따라서, 반도체 칩의 불량 발생을 줄일 수 있다.As described above, in the present invention, the nitride film is placed on the tungsten film, and the nitride film is patterned by anisotropic dry etching and tapered. Then, the nitride film pattern and the tungsten film are etched flat to form the surface of the barrier metal layer, thereby forming a wiring layer near the contact. In addition to reducing the contact resistance by improving the, even if the misalignment has an effect of ensuring the process margin by the tapered lower portion. Thus, the occurrence of defects in the semiconductor chip can be reduced.

Claims (9)

(정정)기판 상부의제1 도전층 위에 절연막을 증착하는 단계,(Corrected) depositing a first insulating film on the first conductive layer of the substrate, 상기 절연막을 패터닝하여 상기 제1 도전층의 일부를 드러내는 콘택 홀을 형성하는 단계,Patterning the insulating layer to form a contact hole exposing a portion of the first conductive layer; 상기 콘택 홀이 형성된 전체 구조 상에 베리어 금속층을 형성하는 단계,Forming a barrier metal layer on the entire structure in which the contact hole is formed; 상기 베리어 금속층 상에플러그용 금속막 및 버퍼 절연막을 연속하여 증착하는 단계,Continuously depositing a plug metal film and a buffer insulating film on the barrier metal layer ; 상기 버퍼 절연막 위에 감광막을 도포하는 단계,Applying a photoresist film on the buffer insulating film, 상기 감광막을 패터닝하여 상기 콘택 홀 상부의 상기 버퍼 절연막 위에 감광막 패턴을 형성하는 단계,Patterning the photoresist to form a photoresist pattern on the buffer insulating layer above the contact hole; 상기 감광막 패턴을 마스크로 상기 버퍼 절연막을 등방성 건식 식각하여 가장자리가 경사진 테이퍼 형태의 버퍼 절연막 패턴을 형성하는 단계, 및Isotropic dry etching the buffer insulating layer using the photoresist pattern as a mask to form a tapered buffer insulating pattern having an inclined edge; and 상기 버퍼 절연막 패턴과 상기 플러그용 금속막을 에치 백하여표면이상기 베리어 금속층의 표면과평행한플러그를 형성하는 단계Etching back the buffer insulating layer pattern and the plug metal layer to form a plug having a surface parallel to the surface of the barrier metal layer 를 포함하는 다층 배선의 콘택 형성 방법.Contact formation method of a multilayer wiring comprising a. 제1항에서,In claim 1, 상기 플러그가 형성되어 있는 전체 구조 상에 상부 제2 도전층을 형성하는 단계를 더 포함하는 다층 배선의 콘택 형성 방법.And forming an upper second conductive layer on the entire structure in which the plug is formed. (정정) 제1항에서,(Correction) In paragraph 1, 상기 버퍼 절연막 패턴과 상기 플러그용 금속막을 에치 백할 때, 상기 버퍼 절연막 패턴이 제거되고 상기 플러그용 금속막의 표면이 상기 베리어 금속층의 표면에 평행이 되도록상기 버퍼 절연막과 상기 플러그용 금속막의식각 선택비를 고려하여, 상기 버퍼 절연막의 두께를 조절하는다층 배선의 콘택 형성 방법. When the buffer insulating film pattern and the plug metal film are etched back, the etching selectivity between the buffer insulating film and the plug metal film is removed so that the buffer insulating film pattern is removed and the surface of the plug metal film is parallel to the surface of the barrier metal layer . In consideration of the above, the method for forming a contact of a multilayer wiring for controlling the thickness of the buffer insulating film . 제3항에서,In claim 3, 상기 플러그용 금속막으로 텅스텐막을 사용하는 다층 배선의 콘택 형성 방법.A contact formation method for a multilayer wiring using a tungsten film as said plug metal film. 제4항에서,In claim 4, 상기 버퍼 절연막을 질화막으로 형성하는 다층 배선의 콘택 형성 방법.The contact formation method of the multilayer wiring which forms the said buffer insulating film with a nitride film. 제5항에서,In claim 5, 상기 질화막의 상기 등방성 건식 식각에 SF6계열의 식각 기체를 사용하는 다층 배선의 콘택 형성 방법.And forming an SF 6 series etching gas for the isotropic dry etching of the nitride film. 제4항에서,In claim 4, 상기 버퍼 절연막을 산화막으로 형성하는 다층 배선의 콘택 형성 방법.A contact formation method for a multilayer wiring in which the buffer insulating film is formed of an oxide film. 제7항에서,In claim 7, 상기 산화막의 상기 등방성 건식 식각에 CF4또는 C4F8의 식각 기체를 사용하는 다층 배선의 콘택 형성 방법.And forming an etching gas of CF 4 or C 4 F 8 for the isotropic dry etching of the oxide film. 제3항에서,In claim 3, 상기 베리어 금속층은 Ti/TiN으로 형성하는 다층 배선의 콘택 형성 방법.And the barrier metal layer is formed of Ti / TiN.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177257A (en) * 1992-12-07 1994-06-24 Oki Electric Ind Co Ltd Formation of multilayer wiring for semiconductor element
KR960019522A (en) * 1994-11-30 1996-06-17 김주용 Plug Formation Method for Semiconductor Devices
JPH09148431A (en) * 1995-11-21 1997-06-06 Nec Corp Manufacture of semiconductor device
KR19980030443A (en) * 1996-10-29 1998-07-25 김영환 Metal wiring formation method of semiconductor device
KR19980044102A (en) * 1996-12-05 1998-09-05 김광호 Method for forming contact plug of semiconductor device
KR19980056165A (en) * 1996-12-28 1998-09-25 김영환 Metal wiring formation method of semiconductor device
JPH10340956A (en) * 1997-06-10 1998-12-22 Mitsubishi Electric Corp Semiconductor device and fabrication thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177257A (en) * 1992-12-07 1994-06-24 Oki Electric Ind Co Ltd Formation of multilayer wiring for semiconductor element
KR960019522A (en) * 1994-11-30 1996-06-17 김주용 Plug Formation Method for Semiconductor Devices
JPH09148431A (en) * 1995-11-21 1997-06-06 Nec Corp Manufacture of semiconductor device
KR19980030443A (en) * 1996-10-29 1998-07-25 김영환 Metal wiring formation method of semiconductor device
KR19980044102A (en) * 1996-12-05 1998-09-05 김광호 Method for forming contact plug of semiconductor device
KR19980056165A (en) * 1996-12-28 1998-09-25 김영환 Metal wiring formation method of semiconductor device
JPH10340956A (en) * 1997-06-10 1998-12-22 Mitsubishi Electric Corp Semiconductor device and fabrication thereof

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