KR20040060189A - Method for fabricating tungsten plug - Google Patents
Method for fabricating tungsten plug Download PDFInfo
- Publication number
- KR20040060189A KR20040060189A KR1020020086728A KR20020086728A KR20040060189A KR 20040060189 A KR20040060189 A KR 20040060189A KR 1020020086728 A KR1020020086728 A KR 1020020086728A KR 20020086728 A KR20020086728 A KR 20020086728A KR 20040060189 A KR20040060189 A KR 20040060189A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- etch stop
- tungsten
- stop layer
- forming
- Prior art date
Links
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 42
- 239000010937 tungsten Substances 0.000 title claims abstract description 42
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 78
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 텅스텐 플러그 형성 시 텅스텐층이 평탄하게 하여 접촉 저항의 증가를 방지할 수 있는 텅스텐 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a tungsten plug which can prevent an increase in contact resistance by flattening a tungsten layer when forming a tungsten plug.
최근, 반도체 집적 회로에서는 그 크기가 더욱 감소됨에 따라, 집적 회로에서의 배선을 다층화하고 이 배선들을 연결하는 다층 배선 방법이 주로 사용되고 있다. 일반적으로 배선들을 연결하기 위해 하부 배선층 상부에 접촉구나 비아(via)홀을 형성하고 스퍼터링과 같은 방법으로 알루미늄과 같은 금속을 증착하여 상부 배선층을 형성함으로써 배선을 완성한다. 그러나, 이러한 스퍼터링 방법에 의해 알루미늄과 같은 금속을 증착할 경우 접촉구 내부에 금속이 완전히 메워지지 않아 배선 연결이 제대로 이루어지지 않을 뿐만 아니라 접촉구나 비아 홀 내에서 스텝 커버리지(step coverage)가 불량하게 되어 소자의 수율이 감소하게 된다.In recent years, as the size of semiconductor integrated circuits is further reduced, a multilayer wiring method for multilayering wirings in the integrated circuit and connecting the wirings is mainly used. In general, the wiring is completed by forming a contact or via hole on the lower wiring layer to connect the wirings, and depositing a metal such as aluminum to form the upper wiring layer by sputtering. However, in the case of depositing a metal such as aluminum by this sputtering method, the metal is not completely filled inside the contact hole, so that the wiring connection is not made properly, and the step coverage is poor in the contact or via hole. The yield of the device is reduced.
이러한 이유로 인하여 반도체 소자의 고집적화에 따른 반도체 소자의 배선 연결을 위한 물질로서 접촉구나 비아 홀에서 양호한 스텝 커버리지를 갖는 텅스텐을 이용하여 금속 플러그를 이용하게 되었다.For this reason, metal plugs are used by using tungsten having good step coverage in contacts or via holes as a material for wiring connection of semiconductor devices due to high integration of semiconductor devices.
그러면, 첨부한 도면을 참조하여 종래의 텅스텐 플러그 형성 방법에 대해 설명한다. 도 1a 내지 도 1c는 종래 기술에 의한 텅스텐 플러그 형성 과정을 도시한 공정 단면도이다.Next, a conventional tungsten plug forming method will be described with reference to the accompanying drawings. 1A to 1C are cross-sectional views illustrating a tungsten plug forming process according to the prior art.
먼저, 도 1a에 도시한 바와 같이 반도체 소자(도시하지 않음)를 포함하는 반도체 기판(1) 위에 하부 배선층(2)을 형성한 후, 그 위에 층간 절연막(inter-metal dielectric)(3)을 증착하고 패터닝하여 하부 배선층(2)을 드러내는 비아 홀(4)을 형성한다.First, as shown in FIG. 1A, a lower wiring layer 2 is formed on a semiconductor substrate 1 including a semiconductor element (not shown), and then an inter-metal dielectric 3 is deposited thereon. And patterning to form a via hole 4 exposing the lower wiring layer 2.
다음, 도 1b에 도시한 바와 같이 배리어층(5)을 스퍼터링(sputtering) 방법으로 적층한 후, 텅스텐층(6)을 증착한다. 여기서, 텅스텐층(6)은 비아 홀(4)이 형성되어 있는 부분에서 아래쪽으로 들어간 골 형태를 이루고 있다.Next, as shown in FIG. 1B, the barrier layer 5 is laminated by the sputtering method, and then the tungsten layer 6 is deposited. Here, the tungsten layer 6 has a valley shape that goes down from the portion where the via hole 4 is formed.
다음, 도 1c에 도시한 바와 같이, 화학 기계적 연마 공정(CMP : Chemical Mechanical Polishing, 이하 “씨엠피라고 함”)을 진행하여 층간 절연막(3)이 완전히 드러나도록 텅스텐층(6) 완전히 제거한 후에 폴리싱(polishing)한다. 이러한 씨엠피 공정을 통해 텅스텐 플러그(7)를 형성한다.Next, as shown in FIG. 1C, a chemical mechanical polishing process (CMP: CMP) is performed to completely remove the tungsten layer 6 so that the interlayer insulating film 3 is completely exposed and then polished ( polishing). Through the CMP process, the tungsten plug 7 is formed.
이와 같은 방법에서는 텅스텐층(6)을 화학 기계적 연마 공정으로 제거할 때 텅스텐층(6)의 하부막인 배리어층(5)을 드러내기 위해 오버 씨엠피(over CMP)를 하게 된다. 따라서, 비아 홀(4)에 채워진 텅스텐층(6)은 비아 홀(4) 부분이 우묵하게 들어가 플러그 리세스(plug recess)가 발생하게 되고 그 상부에 형성되는 상부 배선층(도시 생략됨)을 적층하였을 때, 상부 배선층도 비아 홀(4) 부분에서 우묵하게 된다. 이는 상부 배선층과 그 위의 금속막 사이의 접촉 저항 증가시키는 원인이 되는데, 이에 따라 직류 파라미터(DC parameter) 측정 시 저항이 기준치에서 벗어나므로 칩(chip)이 작동하지 않게 된다.In such a method, when the tungsten layer 6 is removed by a chemical mechanical polishing process, an over CMP is performed to reveal the barrier layer 5, which is a lower layer of the tungsten layer 6. Therefore, the tungsten layer 6 filled in the via hole 4 has a recessed portion of the via hole 4 to generate a plug recess, and stacks an upper wiring layer (not shown) formed thereon. In this case, the upper wiring layer is also recessed in the via hole 4. This causes the contact resistance between the upper wiring layer and the metal film thereon to increase. As a result, when the DC parameter is measured, the resistance deviates from the reference value, thereby preventing the chip from operating.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 층간 절연막의 상부에 식각 정지막을 형성하여 텅스텐 씨엠피 공정 시에 식각 정지막을 하드 마스크로하여 텅스텐을 식각함으로써, 텅스텐층이 평탄하게 되어 접촉 저항의 증가를 방지할 수 있는 텅스텐 플러그 형성 방법을 제공하고자 한다.An object of the present invention is to solve such a problem of the prior art, by forming an etch stop layer on top of the interlayer insulating film and etching the tungsten using the etch stop layer as a hard mask during the tungsten CMP process, the tungsten layer is flat To provide a method of forming a tungsten plug that can prevent the increase in contact resistance.
상기와 같은 목적을 달성하기 위하여 본 발명은, 하부 배선층이 형성된 반도체 기판 상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막의 상부에 식각 정지막을 형성하는 단계와, 상기 하부 배선층이 드러나도록 상기 층간 절연막과 식각 정지막을 패터닝하여 비이홀을 형성하는 단계와, 상기 패터닝된 층간 절연막과 식각 정지막을 덮은 배리어층을 형성하는 단계와, 상기 배리어층 상부에 텅스텐층을증착하여 상기 비아홀을 매립하는 단계와, 상기 패터닝된 식각 정지막을 엔드포인트로 하여 상기 식각 정지막이 드러나도록 상기 텅스텐층을 식각하는 단계와, 상기 층간 절연막이 완전히 드러나도록 상기 패터닝된 식각 정지막을 제거하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film on a semiconductor substrate on which a lower wiring layer is formed, forming an etch stop layer on the insulating film, and exposing the lower wiring layer to expose the lower wiring layer. Patterning an insulating layer and an etch stop layer to form a bi-hole; forming a barrier layer covering the patterned interlayer insulating layer and the etch stop layer; depositing a tungsten layer on the barrier layer to fill the via hole; And etching the tungsten layer so that the etch stop layer is exposed using the patterned etch stop layer as an endpoint, and removing the patterned etch stop layer so that the interlayer insulating film is completely exposed.
도 1a 내지 도 1c는 종래 기술에 의한 텅스텐 플러그 형성 과정을 도시한 공정 단면도이고,1A to 1C are cross-sectional views illustrating a process of forming a tungsten plug according to the prior art;
도 2a 내지 도 2e는 본 발명에 따른 텅스텐 플러그 형성 과정을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a tungsten plug forming process according to the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 입력부 200 : 처리부100 input unit 200 processing unit
300 : 제어부300: control unit
이하, 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명한다.Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 텅스텐 플러그 형성 과정을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a tungsten plug forming process according to the present invention.
도 2a에 도시된 바와 같이, 반도체 소자(도시하지 않음)를 포함하는 반도체 기판(100) 위에 하부 배선층(102)을 형성한 후, 그 위에 층간 절연막(inter-metal dielectric)(104)과 식각 정지막(106)을 순차적으로 증착하고, 식각 정지막(106)의 상부에 비아홀을 정의하기 위한 포토레지스트 패턴(108)을 형성한다. 이대 식각 정지막(106)은 실리콘 질화막으로 이루어져 있다.As shown in FIG. 2A, after forming a lower wiring layer 102 on a semiconductor substrate 100 including a semiconductor device (not shown), an inter-metal dielectric 104 and an etch stop are formed thereon. The film 106 is sequentially deposited, and a photoresist pattern 108 for defining a via hole is formed on the etch stop film 106. The large etching stop film 106 is made of a silicon nitride film.
이후, 도 2b에 도시된 바와 같이, 포토레지스트 패턴(108)에 맞춰서 식각 정지막(106) 및 층간 절연막(104)을 하부 배선층(102)이 드러나도록 패터닝하여 비아홀(110)을 형성한 후에 포토레지스트 패턴(104)을 제거한다.Subsequently, as shown in FIG. 2B, the etch stop layer 106 and the interlayer insulating layer 104 are patterned to expose the lower wiring layer 102 in accordance with the photoresist pattern 108 to form the via holes 110. The resist pattern 104 is removed.
도 2c에 도시된 바와 같이, 배리어층(112)을 스퍼터링(sputtering) 방법으로 적층한 후에 텅스텐층(114)을 증착한다. 여기서, 텅스텐층(114)은 비아홀(110)이 형성되어 있는 부분에서 아래쪽으로 들어간 골 형태를 이루고 있다.As shown in FIG. 2C, the tungsten layer 114 is deposited after the barrier layer 112 is stacked by a sputtering method. Here, the tungsten layer 114 has a valley shape that enters downward from a portion where the via hole 110 is formed.
그 다음으로, 도 2d에 도시된 바와 같이, 식각 정지막(106)을엔드포인트(endpoint)로 하는 오버(over) 씨엠피를 진행하여 식각 정지막(106)이 완전히 드러나도록 텅스텐층(114) 완전히 제거한다. 여기서, 오버 화학 기계적 연마 공정을 진행할 때 오버 씨엠피되는 두께는 식각 정지막(106)의 두께에 따라 달라질 수 있다. 오버 씨엠피 공정을 진행한 후에 결과물을 폴리싱(polishing)하여 텅스텐 플러그(114??)를 형성한다.Next, as shown in FIG. 2D, the tungsten layer 114 is subjected to an over CMP using the etch stop film 106 as an endpoint so that the etch stop film 106 is completely exposed. Remove it completely. Here, the thickness of the over CMP when the over chemical mechanical polishing process is performed may vary depending on the thickness of the etch stop layer 106. After the over CMP process, the resultant is polished to form a tungsten plug 114 ??.
이와 같이, 실리콘 질화막으로 이루어진 식각 정지막(106)을 엔드포인트로 하여 텅스턴층(114)을 씨엠피 공정으로 제거함으로써, 씨엠피 공정 마진을 확보할 수 있다.As such, by removing the tungsten layer 114 by the CMP process using the etch stop layer 106 made of the silicon nitride film as an endpoint, it is possible to secure a CMP process margin.
도 2e에 도시된 바와 같이, 전면 식각 또는 습식 식각 공정을 이용하여 층간 절연막(104)의 상부에 증착되어 있는 식각 정지막(106)을 제거한다.As shown in FIG. 2E, the etch stop layer 106 deposited on the interlayer insulating layer 104 is removed by using a front etching process or a wet etching process.
이상 설명한 바와 같이, 본 발명에서는 층간 절연막의 상부에 식각 정지막을 형성하여 텅스텐 씨엠피 공정 시에 식각 정지막을 하드 마스크로하여 텅스텐을 식각함으로써, 텅스텐층이 평탄하게 되어 접촉 저항의 증가를 방지할 수 있기 때문에 반도체 소자의 불량이 발생하는 것을 막을 수 있다.As described above, in the present invention, by forming an etch stop layer on the interlayer insulating film and etching tungsten using the etch stop layer as a hard mask during the tungsten CMP process, the tungsten layer is flattened to prevent an increase in contact resistance. As a result, defects in the semiconductor elements can be prevented from occurring.
또한, 본 발명은 텅스텐 씨엠피 공정 시에 식각 정지막을 엔드포인트로하여 텡스턴층 식각함으로써, 식각 정지막의 두께에 따라 씨엠피 공정에 대한 폭 넓은 마진을 확보할 수 있다.In addition, according to the present invention, a tungsten layer is etched using the etch stop layer as an endpoint during the tungsten CMP process, thereby securing a wide margin for the CMP process according to the thickness of the etch stop layer.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020086728A KR20040060189A (en) | 2002-12-30 | 2002-12-30 | Method for fabricating tungsten plug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020086728A KR20040060189A (en) | 2002-12-30 | 2002-12-30 | Method for fabricating tungsten plug |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040060189A true KR20040060189A (en) | 2004-07-06 |
Family
ID=37352118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020086728A KR20040060189A (en) | 2002-12-30 | 2002-12-30 | Method for fabricating tungsten plug |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040060189A (en) |
-
2002
- 2002-12-30 KR KR1020020086728A patent/KR20040060189A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100457044B1 (en) | Method for manufacturing semiconductor device | |
| KR20040060189A (en) | Method for fabricating tungsten plug | |
| KR100395907B1 (en) | Method for forming the line of semiconductor device | |
| KR100812298B1 (en) | A method for forming a metal-insulator-metal capacitor | |
| KR100383084B1 (en) | Plug forming method of semiconductor devices | |
| KR20020086100A (en) | a forming method of a contact for multi-level interconnects | |
| KR100720518B1 (en) | Semiconductor device and method for fabricating semiconductor device | |
| KR100450241B1 (en) | Method for forming contact plug and semiconductor device has the plug | |
| KR100613384B1 (en) | Method of forming interconnection line for semiconductor device | |
| KR100579856B1 (en) | Metal line formation method of semiconductor device | |
| KR100857989B1 (en) | Metal line formation method of semiconductor device | |
| KR100373706B1 (en) | a manufacturing method for wires of semiconductor devices | |
| KR100607748B1 (en) | Method for forming interconnect of semiconductor device | |
| KR100846993B1 (en) | A manufacturing method for wires of semiconductor devices | |
| KR100422912B1 (en) | Method for forming contact or via hole of semiconductor devices | |
| KR100315849B1 (en) | a forming method of a contact for multi-level interconnects | |
| KR100532749B1 (en) | Method for manufacturing multi-layered metal line of semiconductor device | |
| KR100393968B1 (en) | method for forming dual damascene of semiconductor device | |
| KR100198653B1 (en) | Semiconductor device metallisation method | |
| KR100579858B1 (en) | Method of fabricating mim(metal-insulator-metal) capacitor | |
| KR20020086098A (en) | a contact structure for interconnecting multi-level wires and a method for forming the same | |
| KR20040001459A (en) | Method for forming via hole of semiconductor device | |
| KR20020058429A (en) | A wire in semiconductor device and method for fabricating the same | |
| KR20010057681A (en) | Via hole forming method of semiconductor device | |
| KR20010008605A (en) | Method of forming multi-layered line in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |