KR20020086100A - a forming method of a contact for multi-level interconnects - Google Patents

a forming method of a contact for multi-level interconnects Download PDF

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Publication number
KR20020086100A
KR20020086100A KR1020010025815A KR20010025815A KR20020086100A KR 20020086100 A KR20020086100 A KR 20020086100A KR 1020010025815 A KR1020010025815 A KR 1020010025815A KR 20010025815 A KR20010025815 A KR 20010025815A KR 20020086100 A KR20020086100 A KR 20020086100A
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South Korea
Prior art keywords
plug
contact
film
interlayer insulating
layer
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KR1020010025815A
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Korean (ko)
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박근수
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아남반도체 주식회사
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Priority to KR1020010025815A priority Critical patent/KR20020086100A/en
Publication of KR20020086100A publication Critical patent/KR20020086100A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A contact formation method of multi-layer interconnections is provided to reduce contact resistance by forming a plug that is protruded on an interlayer dielectric. CONSTITUTION: A first interconnection(20) is formed on a substrate(10). An interlayer dielectric(30) and a nitride layer are sequentially formed on the resultant structure. A contact hole(91) is formed to expose the first interconnection(20) by patterning the nitride layer and the interlayer dielectric(30). A metal barrier film(40) is formed in inner walls of the contact hole(91). After depositing a plug metal film, a plug(51) is formed by etching-back the metal barrier film(40) and the plug metal film. After removing the nitride layer, a second interconnection is formed to connect with the first interconnection(20) via the plug(51).

Description

다층 배선의 콘택 형성 방법{a forming method of a contact for multi-level interconnects}A forming method of a contact for multi-level interconnects}

본 발명은 다층 배선의 콘택(contact) 형성 방법에 관한 것으로서, 보다 상세하게는 서로 다른 층에 위치하는 실리콘 기판과 배선, 또는 배선과 배선을 전기적으로 연결시켜 주기 위한 콘택 또는 비아(via)의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact of a multi-layered wiring, and more particularly, to forming a silicon substrate and wiring located on different layers or a contact or via for electrically connecting the wiring and the wiring. It is about a method.

최근, 반도체 집적회로가 고집적화 됨에 따라 제한된 면적 내에서 배선과 배선을 효과적으로 연결하는 방법들이 제시되고 있다. 그 중, 집적 회로에서의 배선을 다층화하는 다층 배선 방법이 주로 사용되고 있는데, 반도체 소자간에 배선이 통과되는 공간을 고려할 필요가 없기 때문에 반도체 소자의 크기를 작게 가져갈 수 있다. 이러한 다층 배선 구조에서는 각 층 간에 존재하는 콘택 또는 비아의 수가 매우 많으며, 이들은 서로 도통하므로, 아주 낮은 콘택 저항값을 가지고 있어야 한다.Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. Since it is not necessary to consider a space through which wiring passes between semiconductor elements, the size of the semiconductor element can be reduced. In such a multi-layered wiring structure, the number of contacts or vias existing between the layers is very large, and since they are conductive with each other, they must have a very low contact resistance value.

그러면, 도 1a 내지 도 1c를 참고로 하여 종래의 기술에 따른 콘택 형성 방법에 대하여 설명한다. 여기서는 편의상, 배선 간의 연결부인 비아(via)를 콘택의 범위에 포함시켜 콘택으로 지칭하여 설명하겠다.Next, a contact forming method according to the related art will be described with reference to FIGS. 1A to 1C. For convenience, a via, which is a connection portion between wirings, is included in a range of a contact and will be referred to as a contact.

먼저, 실리콘 웨이퍼(10) 위에 제1 배선층(20)을 형성하고, 그 위에 TEOS(thetraethyle orthosilicate)막 및/또는 BPSG막 등으로 층간 절연막(30)을 형성한 다음, 기계 화학적 연막(chemical mechanical polishing)을 실시하여 층간 절연막(30)을 평탄화한다. 다음, 층간 절연막(30)을 패터닝하여 제1 배선층(20)의 일정 영역이 드러나도록 콘택 홀(contact hole)을 형성한다.First, the first wiring layer 20 is formed on the silicon wafer 10, an interlayer insulating film 30 is formed thereon with a tetraethyle orthosilicate (TEOS) film and / or a BPSG film, and then a mechanical mechanical polishing ) To planarize the interlayer insulating film 30. Next, the interlayer insulating layer 30 is patterned to form a contact hole so that a predetermined region of the first wiring layer 20 is exposed.

이후, 도 1a에 도시한 바와 같이, 티타늄(Ti)/질화티타늄(TiN)을 증착하여 베리어 금속층(40)을 형성하고, 플러그(plug)용 금속막인 텅스텐막(50)을 연속적으로 형성한다.Thereafter, as shown in FIG. 1A, a barrier metal layer 40 is formed by depositing titanium (Ti) / titanium nitride (TiN), and a tungsten film 50 that is a plug metal film is continuously formed. .

다음, 도 1b에 도시한 바와 같이, 텅스텐막(50)을 에치 백(etch back)하여 플러그(51)를 형성한다. 이때, 하부 막질인 베리어 금속층(40)이 충분히 드러나도록 하기 위해 텅스텐막(50)을 오버 에치(over etch)하므로, 플러그(51)가 콘택홀 안쪽으로 우묵하게 패이는 현상인 리세스(recess)가 발생한다.Next, as shown in FIG. 1B, the tungsten film 50 is etched back to form a plug 51. At this time, since the tungsten film 50 is over etched so that the lower barrier metal layer 40 is sufficiently exposed, the plug 51 recesses into the contact hole. Occurs.

따라서, 도 1c에서와 같이, 제2 배선층을 형성하기 위해 알루미늄(Al)막(60)을 증착할 경우, 플러그(51)의 리세스가 발생한 부근에서 알루미늄막(60)의 적층 프로파일(profile)이 불량해진다.Therefore, as shown in FIG. 1C, when the aluminum (Al) film 60 is deposited to form the second wiring layer, the stacking profile of the aluminum film 60 near the recess of the plug 51 occurs. This becomes bad.

플러그(51)의 리세스가 심한 경우에는, 도 2에 도시한 바와 같이, 알루미늄막(60)에 보이드(void)가 발생하기도 한다.When the recess of the plug 51 is severe, voids may occur in the aluminum film 60, as shown in FIG.

이상에서 설명한 바와 같이, 종래의 기술에 따른 반도체 소자의 콘택 형성 방법에서는, 플러그의 리세스에 의해 상부의 배선층의 적층 프로파일이 나쁘게 형성되기 때문에, 접촉이 불안정해지고 저항이 증가하여, 결과적으로는 반도체 소자의 특성이 저하된다.As described above, in the method for forming a contact of a semiconductor element according to the prior art, since the laminated profile of the upper wiring layer is formed badly by the recess of the plug, the contact becomes unstable and the resistance increases, and consequently, the semiconductor. The characteristics of the device are deteriorated.

본 발명은 이러한 문제점을 해결하기 위한 것으로서, 그 과제는 콘택 부근에서의 배선층의 프로파일을 개선하여 배선의 콘택 저항을 감소시키는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and its task is to reduce the contact resistance of the wiring by improving the profile of the wiring layer in the vicinity of the contact.

본 발명의 다른 과제는 미스 얼라인 발생이 콘택 형성 및 이후 콘택 특성에 영향을 미치지 않도록 공정 마진을 확보하는 것이다.Another object of the present invention is to secure process margins so that misalignment does not affect contact formation and subsequent contact characteristics.

도 1a 및 도 1c는 종래의 기술에 따른 다층 배선의 콘택 형성 방법을 공정 순서에 따라 도시한 단면도이고,1A and 1C are cross-sectional views illustrating a method for forming a contact of a multilayer wiring according to a prior art according to a process sequence;

도 2는 종래의 기술에 따른 다층 배선의 콘택을 나타낸 단면도이고,2 is a cross-sectional view showing a contact of a multilayer wiring according to the prior art,

도 3a 내지 도 3e는 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 도시한 단면도이고,3A to 3E are cross-sectional views illustrating a method for forming a contact for a multilayer wiring according to an embodiment of the present invention.

도 4는 본 발명의 실시예에 따른 다층 배선의 콘택 구조를 도시한 단면도이다.4 is a cross-sectional view illustrating a contact structure of a multilayer wiring according to an embodiment of the present invention.

이러한 과제를 해결하기 위해서, 본 발명에서는 플러그를 층간 절연막의 상부까지 나오도록 형성한다.In order to solve this problem, in the present invention, the plug is formed to extend to the upper portion of the interlayer insulating film.

본 발명에 따른 다층 배선의 콘택 형성 방법에서는, 우선, 기판의 상부에 제1 배선층을 형성하고, 그 상부에 배선층을 덮는 층간 절연막 및 질화막을 차례로 적층한다. 이어, 질화막 및 층간 절연막을 패터닝하여 제1 도전층을 드러내는 콘택 홀을 형성하고, 콘택 홀의 내부에 베리어 금속층을 형성한다. 이어, 플러그용 금속막을 적층하고, 베리어 금속층 및 플러그용 금속막을 에치 백하여 플러그를 형성한다. 이어, 질화막 제거하여 층간 절연막을 드러내고, 플러그를 통하여 제1 배선층과 전기적으로 연결되는 제2 배선층을 형성한다.In the method for forming a contact of a multilayer wiring according to the present invention, first, a first wiring layer is formed on an upper portion of a substrate, and an interlayer insulating film and a nitride film which cover the wiring layer are sequentially stacked on the upper portion. Subsequently, the nitride film and the interlayer insulating film are patterned to form a contact hole exposing the first conductive layer, and a barrier metal layer is formed inside the contact hole. Next, the plug metal film is laminated, and the barrier metal layer and the plug metal film are etched back to form a plug. Next, the nitride film is removed to expose the interlayer insulating film, and a second wiring layer electrically connected to the first wiring layer through a plug is formed.

여기서, 플러그용 금속막은 텅스텐으로 형성할 수 있다. 또한, 베리어 금속층은 Ti/TiN으로 형성하고, 플러그는 층간 절연막 밖으로 돌출되도록 형성하는 것이 바람직하다.Here, the plug metal film may be formed of tungsten. The barrier metal layer is preferably formed of Ti / TiN, and the plug is preferably formed to protrude out of the interlayer insulating film.

그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Next, a method of forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the contact.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 공정 순서에 따라 도시한 단면도이고, 도 4는 본 발명의 실시예에 따른 다층 배선의 콘택 구조를 도시한 단면도이다.3A to 3E are cross-sectional views illustrating a method for forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view illustrating a contact structure of a multilayer wiring according to an embodiment of the present invention.

먼저, 도 3a에서 보는 바와 같이, 종래의 기술에서와 마찬가지로, 규소 기판(10)의 상부에 알루미늄 또는 알루미늄 합금과 같이 저저항을 가지는 도전 물질을 적층하고 패터닝하여 제1 배선층(20)을 형성하고, 그 위에 TEOS막 및/또는 BPSG막 등으로 층간 절연막(30)을 형성한 다음, 기계 화학적 연마를 실시하여 층간 절연막(30)을 평탄화한다..First, as shown in FIG. 3A, as in the related art, the first wiring layer 20 is formed by stacking and patterning a conductive material having a low resistance, such as aluminum or an aluminum alloy, on the silicon substrate 10. The interlayer insulating film 30 is formed on the TEOS film and / or the BPSG film, and then mechanically polished to planarize the interlayer insulating film 30.

이어, 도 3b에서 보는 바와 같이, 층간 절연막(30)의 상부에 화학 기상 증착 방법을 이용하여 질화막(90)을 형성하고, 마스크를 이용한 사진 식각 공정으로 질화막(30) 및 층간 절연막(30)을 패터닝하여 제1 배선층(20)의 일정 영역이 드러내는 콘택 홀(91)을 형성한다.Next, as shown in FIG. 3B, the nitride film 90 is formed on the interlayer insulating film 30 using a chemical vapor deposition method, and the nitride film 30 and the interlayer insulating film 30 are formed by a photolithography process using a mask. Patterning is performed to form a contact hole 91 that exposes a predetermined region of the first wiring layer 20.

이후, 도 3c에 도시한 바와 같이, 콘택부의 접촉 저항을 최소화하고 오버행 등을 방지하기 위하여 티타늄(Ti) 및 질화티타늄(TiN) 등을 차례로 적층하여 베리어 금속층(40)을 형성한 다음, 그 상부에 플러그(plug)용 금속막인 텅스텐막(50)을 연속적으로 증착한다.Then, as shown in Figure 3c, in order to minimize the contact resistance of the contact portion and to prevent overhang, etc. in order to stack the titanium (Ti) and titanium nitride (TiN) and the like to form a barrier metal layer 40, then the upper The tungsten film 50, which is a metal film for plugging, is deposited successively.

이어, 도 3d에 도시한 바와 같이, 텅스텐막(50)과 베리어 금속층(40)을 그 하부의 질화막(90)이 드러날 때까지 에치 백하여 콘택부에 플러그(51)를 형성한다.3D, the tungsten film 50 and the barrier metal layer 40 are etched back until the lower nitride film 90 is exposed to form a plug 51 in the contact portion.

이어, 도 3e에서 보는 바와 같이, 질화막(90)을 식각하여 층간 절연막(30)의 상부로 베리어 금속층(40)과 플러그(51)을 드러낸다.Next, as shown in FIG. 3E, the nitride film 90 is etched to expose the barrier metal layer 40 and the plug 51 on the interlayer insulating film 30.

이어, 도 4에서 보는 바와 같이, 배선용 도전 물질인 알루미늄 또는 알루미늄 합금을 적층하고 패터닝하여 제2 배선층(60)을 형성한다.Next, as shown in FIG. 4, the second wiring layer 60 is formed by stacking and patterning aluminum or an aluminum alloy, which is a conductive material for wiring.

이러한 본 발명의 실시예에 따라 완성된 다층 배선의 콘택 구조는, 기판(10)의 상부에 제1 배선층(20)이 형성되어 있고, 제1 배선층(20)을 덮는 층간 절연막(30)이 형성되어 있다. 층간 절연막(30)은 제1 배선층(20)을 드러내는 콘택 홀(91)이 형성되어 있으며, 콘택 홀(91)의 내벽에는 베리어 금속층(40)이 형성되어 있으며, 베리어 금속층(40)의 안쪽에는 층간 절연막(30) 밖으로 돌출되어 있는 플러그(51)가 형성되어 있다. 층간 절연막(30)의 상부에는 플러그(51) 및 베리어 금속층(40)을 덮는 제2 배선층(60)이 형성되어 있다.In the contact structure of the multilayer wiring completed according to the embodiment of the present invention, the first wiring layer 20 is formed on the substrate 10, and the interlayer insulating film 30 covering the first wiring layer 20 is formed. It is. The interlayer insulating layer 30 has a contact hole 91 exposing the first wiring layer 20, a barrier metal layer 40 is formed on the inner wall of the contact hole 91, and inside the barrier metal layer 40. The plug 51 which protrudes out of the interlayer insulating film 30 is formed. The second wiring layer 60 covering the plug 51 and the barrier metal layer 40 is formed on the interlayer insulating layer 30.

이상에서와 같이, 본 발명에서는 플러그를 층간 절연막의 밖으로 나오도록 형성함으로써 콘택 홀의 내부에 보이드가 발생하는 것을 방지할 수 있어, 콘택부의 접촉 저항을 크게 감소시킬 수 있으며 콘택 특성에 영향을 미치지 않도록 공정 마진을 확보할 수 있다. 따라서, 반도체 칩의 작동 특성의 저하를 막을 수 있다.As described above, in the present invention, by forming the plug out of the interlayer insulating film, voids can be prevented from occurring inside the contact hole, thereby greatly reducing the contact resistance of the contact portion and not affecting the contact characteristics. Margin can be secured. Therefore, the fall of the operating characteristic of a semiconductor chip can be prevented.

Claims (2)

기판의 상부에 제1 배선층을 형성하는 단계,Forming a first wiring layer on the substrate; 상기 제1 배선층을 덮는 층간 절연막을 적층하는 단계,Stacking an interlayer insulating film covering the first wiring layer; 상기 층간 절연막의 상부에 질화막을 형성하는 단계,Forming a nitride film on the interlayer insulating film; 상기 질화막 및 상기 층간 절연막을 패터닝하여 상기 제1 도전층을 드러내는 콘택 홀을 형성하는 단계,Patterning the nitride film and the interlayer insulating film to form a contact hole exposing the first conductive layer; 상기 콘택 홀의 내부에 베리어 금속층을 형성하는 단계,Forming a barrier metal layer in the contact hole; 플러그용 금속막을 적층하는 단계,Stacking a metal film for a plug, 상기 베리어 금속층 및 상기 플러그용 금속막을 에치 백하여 플러그를 형성하는 단계,Etching the barrier metal layer and the plug metal layer to form a plug; 상기 질화막 제거하여 상기 층간 절연막을 드러내는 단계,Removing the nitride film to expose the interlayer insulating film, 상기 플러그를 통하여 상기 제1 배선층과 전기적으로 연결되는 제2 배선층을 형성하는 단계Forming a second wiring layer electrically connected to the first wiring layer through the plug; 를 포함하는 다층 배선의 콘택 형성 방법.Contact formation method of a multilayer wiring comprising a. 제1항에서,In claim 1, 상기 플러그는 상기 질화막 밖으로 돌출되도록 형성하는 다층 배선의 콘택 형성 방법.And the plug is formed to protrude out of the nitride film.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100815186B1 (en) * 2006-09-11 2008-03-19 주식회사 하이닉스반도체 Method of fabricating semiconductor device with protrusion type w plug
KR100831248B1 (en) * 2007-05-16 2008-05-22 주식회사 동부하이텍 Method for forming metal line of semiconductor device
KR100850069B1 (en) 2006-12-27 2008-08-04 동부일렉트로닉스 주식회사 Method for manufacturing metal line of semiconductor device
US11367651B2 (en) 2019-07-18 2022-06-21 Samsung Electronics Co., Ltd. Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100815186B1 (en) * 2006-09-11 2008-03-19 주식회사 하이닉스반도체 Method of fabricating semiconductor device with protrusion type w plug
US7615494B2 (en) 2006-09-11 2009-11-10 Hynix Semiconductor Inc. Method for fabricating semiconductor device including plug
KR100850069B1 (en) 2006-12-27 2008-08-04 동부일렉트로닉스 주식회사 Method for manufacturing metal line of semiconductor device
KR100831248B1 (en) * 2007-05-16 2008-05-22 주식회사 동부하이텍 Method for forming metal line of semiconductor device
US11367651B2 (en) 2019-07-18 2022-06-21 Samsung Electronics Co., Ltd. Semiconductor device

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