KR100478487B1 - Semiconductor device and fabrication method thereof - Google Patents
Semiconductor device and fabrication method thereof Download PDFInfo
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- KR100478487B1 KR100478487B1 KR10-2002-0069184A KR20020069184A KR100478487B1 KR 100478487 B1 KR100478487 B1 KR 100478487B1 KR 20020069184 A KR20020069184 A KR 20020069184A KR 100478487 B1 KR100478487 B1 KR 100478487B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
반도체 소자의 금속배선 형성방법에 관한 것으로, 그 목적은 금속배선 상부에 위치하는 비아의 오정렬을 방지하고 비아의 정렬위치에 대한 공정마진을 확보하는 것이다. 이를 위해 본 발명에서는 금속배선구를 예정된 영역보다 보다 더 넓은 폭으로 형성하고 그 내부에 사이드월을 형성하여 결과적으로 금속배선이 상부로 갈수록 넓은 폭을 가져 상부비아 형성 시 정렬위치에 대한 공정마진을 확보하는 데 그 특징이 있다.The present invention relates to a method for forming metal wirings of a semiconductor device, and an object thereof is to prevent misalignment of vias located on the top of metal wirings and to secure a process margin for alignment positions of vias. To this end, in the present invention, the metal wiring hole is formed to have a wider width than the predetermined area, and sidewalls are formed therein, so that the metal wiring has a wider width toward the top, so that the process margin for the alignment position is formed when forming the upper via. It is characteristic to secure.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 금속 배선을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a metal wiring.
반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring technology has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.
그러면 종래 다층 배선을 형성하는 공정을 간략하게 설명한다.This will briefly describe a process of forming a conventional multilayer wiring.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판의 구조물(1), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속배선 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2)의 소정 영역을 식각하여 하부 금속배선(3)을 노출시키는 비아홀(100)을 형성한 후, 비아홀(100)을 금속물질로 충진하고 하부절연막(2)이 노출될 때까지 화학기계적 연마하여 상부표면을 평탄화함으로써 하부비아(4)를 형성한다.First, as shown in FIG. 1A, a lower insulating film 2 made of an oxide film or the like is formed on a structure 1 of a semiconductor substrate, that is, on a semiconductor substrate on which individual elements are formed or on a lower metal wiring. After etching the predetermined region to form the via hole 100 exposing the lower metal wiring 3, the via hole 100 is filled with a metal material and chemically polished until the lower insulating film 2 is exposed to the upper surface. The lower via 4 is formed by planarization.
이어서, 평탄화된 상면 상에 식각종료층으로 사용하기 위한 질화막(5)을 형성하고, 질화막(5) 상에 층간절연막으로서 산화막(6)을 두껍게 증착한다.Subsequently, a nitride film 5 for use as an etch stop layer is formed on the planarized top surface, and an oxide film 6 is thickly deposited on the nitride film 5 as an interlayer insulating film.
다음, 도 1b에 도시된 바와 같이, 질화막(5)을 식각종료층으로 사용하여 산화막(6) 및 질화막(5)을 선택적으로 식각하여 하부비아(4)를 노출시키는 금속배선구(200)를 형성한 후, 금속배선구(200)의 내벽을 포함하여 산화막(6)의 상부 표면에 Ti 또는 TiN 베리어막(7)을 형성한 후, 베리어막(7) 상에 금속배선구(200)를 충분히 매립하도록 알루미늄(8)을 두껍게 증착한다.Next, as illustrated in FIG. 1B, the metal wires 200 exposing the lower vias 4 by selectively etching the oxide film 6 and the nitride film 5 using the nitride film 5 as an etch stop layer. After the formation, the Ti or TiN barrier film 7 is formed on the upper surface of the oxide film 6 including the inner wall of the metal wire 200, and then the metal wire 200 is formed on the barrier film 7. Thick aluminum 8 is deposited to fill up sufficiently.
다음, 도 1c에 도시된 바와 같이, 산화막(6)이 노출될 때까지 알루미늄(8)을 화학기계적 연마하거나 에치백하여 상면을 평탄화시킴으로써 상부 금속배선(8')을 형성한다.Next, as shown in FIG. 1C, the upper metal wiring 8 'is formed by planarizing the upper surface by chemically polishing or etching back the aluminum 8 until the oxide film 6 is exposed.
다음, 도 1d에 도시된 바와 같이, 평탄화된 상면 상에 상부절연막(9)을 형성하고, 상부절연막(9) 상에 감광막을 도포한 후 이를 노광 및 현상하여 상부비아로 예정된 영역을 노출시키는 감광막 패턴(10)을 형성한다.Next, as shown in FIG. 1D, an upper insulating film 9 is formed on the planarized top surface, a photosensitive film is coated on the upper insulating film 9, and then exposed and developed to expose the predetermined region to the upper via. The pattern 10 is formed.
이후에는 감광막 패턴(10)을 마스크로 하여 상부절연막(9)을 선택적으로 식각하여 상부비아(11)를 형성한다.Thereafter, the upper insulating layer 9 is selectively etched using the photoresist pattern 10 as a mask to form the upper via 11.
그런데, 상부비아 형성을 위한 감광막 패턴(11)이, 금속배선(8')과 연결되는 상부비아 예정 영역을 벗어나서 오정렬(mis-align)되면 결과적으로 도 1d에서 점선원으로 표시한 부분에 나타난 바와 같이 상부비아(11)가 금속배선(8')을 벗어나 오정렬되는 경우가 종종 발생하는데, 이러한 비아의 오정렬은 반도체 소자의 고집적화 추세에 따라 더욱 심해지고 있으므로, 이에 대한 해결책이 시급한 실정이다.However, when the photoresist pattern 11 for forming the upper via is misaligned outside the predetermined region of the upper via connected to the metal wiring 8 ′, as shown in the dotted line circle in FIG. 1D. As the upper via 11 is often misaligned out of the metal wiring 8 ', the misalignment of the via is getting worse according to the high integration trend of the semiconductor device, so a solution for this is urgent.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속배선 상부에 위치하는 비아의 오정렬을 방지하고 비아의 정렬위치에 대한 공정마진을 확보하는 것이다.The present invention is to solve the problems as described above, the object is to prevent misalignment of the vias located on the upper metal wiring and to ensure a process margin for the alignment position of the vias.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 금속배선구를 예정된 영역보다 보다 더 넓은 폭으로 형성하고 그 내부에 사이드월을 형성하여 결과적으로 금속배선이 상부로 갈수록 넓은 폭을 가져 상부비아 형성시 정렬위치에 대한 공정마진을 확보하는 데 그 특징이 있다.In order to achieve the above object, in the present invention, the metal wiring hole is formed to have a wider width than the predetermined area, and sidewalls are formed therein, so that the metal wiring has a wider width toward the top to form upper vias. It is characterized by securing the process margin for the alignment position.
즉, 본 발명에 따른 반도체 소자의 금속배선 형성방법은, 반도체 기판 구조물 상에 형성되고 하부비아를 포함하는 제1절연막을 식각하여 하부비아를 노출시키는 금속배선구를 형성하되, 금속배선구를 설계치보다 더 넓은 폭으로 형성하는 단계; 금속배선구를 포함하여 제1절연막의 상부 전면에 추가막을 증착하고 추가막을 이방성 식각하여, 하부비아를 노출시키고 금속배선구 내벽의 측방에만 추가막을 남김으로써 사이드월을 형성하는 단계; 노출된 하부비아 및 사이드월 상에 제1금속물질을 충진하여 금속배선을 형성하는 단계; 금속배선을 포함한 제1절연막 상부에 제2절연막을 형성하는 단계; 및 제2절연막을 선택적 식각하여 금속배선을 노출시키는 비아홀을 형성한 후 제2금속물질을 충진하여 상부비아를 형성하는 단계를 포함하여 이루어진다.That is, in the method for forming metal wirings of the semiconductor device according to the present invention, the metal wiring holes are formed on the semiconductor substrate structure to form the metal wiring holes to expose the lower vias by etching the first insulating layer including the lower vias. Forming a wider width; Depositing an additional layer on the entire upper surface of the first insulating layer including the metal interconnection and anisotropically etching the additional layer to expose the lower via and to form the sidewall by leaving the additional layer only on the side of the inner wall of the metal interconnection; Filling a first metal material on the exposed lower via and sidewall to form a metal wiring; Forming a second insulating layer on the first insulating layer including the metal wiring; And selectively forming the via hole exposing the metal wiring by selectively etching the second insulating layer, and then filling the second metal material to form the upper via.
여기서, 추가막으로는, 질화막, 산화막, 또는 폴리실리콘막을 2000-4000Å의 두께로 형성하는 것이 바람직하다.Here, as an additional film, it is preferable to form a nitride film, an oxide film, or a polysilicon film with a thickness of 2000-4000 kPa.
제1금속물질로는 알루미늄, 알루미늄합금 또는 구리를 형성할 수 있으며, 제2금속물질로는 텅스텐, 알루미늄, 알루미늄합금, 또는 구리를 형성할 수 있다.The first metal material may be formed of aluminum, aluminum alloy or copper, and the second metal material may be formed of tungsten, aluminum, aluminum alloy, or copper.
이하, 본 발명에 따른 반도체 소자의 금속배선 형성 방법에 대해 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail.
일반적으로 금속배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성이 우수한 금속 배선 재료이므로, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.Generally, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, since copper (Cu) is a metal wiring material having a low specific resistance and excellent reliability compared to tungsten and aluminum, studies are being actively conducted to replace metal wiring of semiconductor devices with copper.
그런데, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(Reactive Ion Etching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 건식 식각 공정을 거치지 않으면서 금속배선(line)을 형성할 수 있는 방법에 관하여 활발히 연구되고 있는바, 이러한 공정을 다마신(damascene)공정이라 한다.However, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by dry etching. Therefore, in the case of copper, active research on a method for forming a metal line without a dry etching process, such a process is called a damascene (damascene) process.
기존의 구리를 이용한 다마신 공정에 의하면 구리를 웨이퍼에 전면증착(blanket deposition)한 후에 불필요한 웨이퍼 표면의 구리층을 화학기계적 연마 또는 에치백 공정으로 제거함으로써 최종적인 구리 금속배선을 형성한다.According to the conventional damascene process using copper, copper is deposited on a wafer and then the copper layer on the wafer surface is removed by chemical mechanical polishing or etch back process to form a final copper metallization.
한편, 반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.Meanwhile, as semiconductor devices have been increasingly integrated and multilayered, multilayer wiring has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed. The circuit operation is performed by electrically connecting the metal wiring layers separated by the via via.
이러한 다층 배선 기술을 실현하기 위해 다마신 공정을 적용하면, 감광막 패턴을 마스크로 이용하여 금속간 절연막을 선택적으로 식각함으로써 하부 비아 금속과 접촉하는 배선구를 형성한 후, 배선구를 금속물질로 매립하여 하부 금속배선을 형성하고, 그 위에 다시 금속간 절연막을 증착하고 이를 선택적으로 식각하여 하부 금속배선과 연결되는 상부 비아홀을 형성한다.When the damascene process is applied to realize the multi-layered wiring technology, a wiring hole in contact with the lower via metal is formed by selectively etching an intermetallic insulating layer using a photosensitive film pattern as a mask, and then the wiring hole is embedded with a metal material. As a result, a lower metal interconnection is formed, and an intermetallic insulating layer is deposited thereon and selectively etched to form an upper via hole connected to the lower metal interconnection.
본 발명에서는 다마신 공정을 이용하여 다층 배선을 형성할 때 금속배선구와 접촉하는 비아의 정렬위치에 대한 여유분을 확보하고자 한다.In the present invention, when the multilayer wiring is formed using the damascene process, it is intended to secure a margin for the alignment position of the vias in contact with the metal wiring holes.
그러면, 본 발명에 따라 반도체 소자의 금속배선을 형성하는 공정을 간략하게 설명한다. 도 2e는 본 발명에 따라 금속배선을 형성한 반도체 소자를 도시한 단면도이며, 이에 도시된 바와 같이, 반도체 기판 구조물(21) 상에서 하부비아(24)를 포함하는 하부절연막(22) 상에는 금속배선구가 형성되어 있어서 금속배선구를 통해 하부비아(24)가 노출되며, 금속배선구 내벽의 측방으로는 사이드월(27')이 형성되어 있다.Then, the process of forming the metal wiring of the semiconductor device according to the present invention will be briefly described. 2E is a cross-sectional view illustrating a semiconductor device in which metal wirings are formed according to the present invention. As shown in FIG. 2E, a metal wiring hole is formed on a lower insulating layer 22 including a lower via 24 on a semiconductor substrate structure 21. The lower via 24 is exposed through the metal wiring hole, and the side wall 27 'is formed on the side of the inner wall of the metal wiring hole.
여기서, 사이드월(27')은 질화막, 산화막, 또는 폴리실리콘막으로 이루어질 수 있으며, 금속배선구의 바닥면 측방으로 가장 두껍게 형성된 부분이 2000-4000Å정도의 두께인 것이 바람직하다.Here, the side wall 27 ′ may be formed of a nitride film, an oxide film, or a polysilicon film, and the portion formed thickest toward the bottom surface side of the metal wiring hole may have a thickness of about 2000-4000 mm 3.
노출된 하부비아(24) 및 사이드월(27') 상에는 금속배선구를 충진하는 금속배선(28')이 형성되어 있으며, 이 때 금속배선(28')은 사이드월(27')로 인해 상부로 갈수록 폭이 넓어지는 형상이다. 금속배선(28')은 알루미늄, 알루미늄합금 또는 구리로 이루어질 수 있다.On the exposed lower via 24 and the sidewall 27 ', a metal wiring 28' is formed to fill the metal wiring holes. In this case, the metal wiring 28 'is formed on the upper side due to the sidewall 27'. It is a shape that becomes wider as it goes. The metal wire 28 'may be made of aluminum, aluminum alloy, or copper.
하부절연막 상에는 금속배선(28')과 연결되도록 형성된 상부비아(30)를 포함하는 상부절연막(26, 29)이 형성되어 있다. 이 때, 상부비아 및 하부비아는 텅스텐, 알루미늄, 알루미늄합금, 또는 구리로 이루어질 수 있다.Upper insulating layers 26 and 29 including upper vias 30 formed to be connected to the metal wiring 28 ′ are formed on the lower insulating layer. In this case, the upper via and the lower via may be made of tungsten, aluminum, an aluminum alloy, or copper.
이러한 본 발명에 따른 반도체 소자를 제조하는 공정을 도 2a 내지 도 2e를 참조하여 설명하면 다음과 같다. 도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 반도체 소자의 금속배선 형성 방법을 도시한 단면도이다.A process of manufacturing the semiconductor device according to the present invention will be described with reference to FIGS. 2A through 2E. 2A through 2E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 구조물(21), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속배선 상부에 산화막 등으로 이루어진 하부절연막(22)을 형성하고, 하부절연막(22)의 소정 영역을 식각하여 하부 금속배선(23)을 노출시키는 비아홀(300)을 형성한 후, 비아홀(300)을 금속물질로 충진하고 하부절연막(22)이 노출될 때까지 화학기계적 연마하여 상부표면을 평탄화함으로써 하부 비아(24)를 형성한다.First, as shown in FIG. 2A, a lower insulating film 22 made of an oxide film or the like is formed on a structure 21 of a semiconductor substrate, that is, on a semiconductor substrate or a lower metal wiring on which an individual element is formed, and then the lower insulating film 22 is formed. After etching the predetermined region to form the via hole 300 exposing the lower metal wiring 23, the via hole 300 is filled with a metal material and chemically polished until the lower insulating layer 22 is exposed to the upper surface. The bottom via 24 is formed by planarization.
이어서, 평탄화된 상면 상에 식각종료층으로 사용하기 위한 질화막(25)을 형성하고, 질화막(25) 상에 층간절연막으로서 제1산화막(26)을 증착한다.Subsequently, a nitride film 25 for use as an etch stop layer is formed on the planarized top surface, and the first oxide film 26 is deposited on the nitride film 25 as an interlayer insulating film.
다음, 도 2b에 도시된 바와 같이, 질화막(25)을 식각종료층으로 사용하여 제1산화막(26) 및 질화막(25)을 선택적으로 식각하여 하부비아(24)를 노출시키는 금속배선구(400)를 형성하는 데, 이 때 의도적으로, 배선구 폭으로 설계한 값보다 더 넓은 폭으로 식각한다. 즉, 제1산화막(26) 상에 감광막을 도포하고 노광 및 현상하여 배선구로 예정된 영역의 제1산화막을 노출시키는 감광막 패턴(미도시)을 형성할 때, 감광막 패턴의 오프닝된 부분의 폭을 설계치보다 더 넓은 폭이 되도록 감광막 패턴을 형성하고, 그 감광막 패턴을 마스크로 하여 제1산화막(26) 및 질화막(25)을 식각하여 설계치보다 더 넓은 폭을 가지는 배선구(400)를 형성한다.Next, as shown in FIG. 2B, the metallization hole 400 exposing the lower via 24 by selectively etching the first oxide layer 26 and the nitride layer 25 using the nitride layer 25 as an etch stop layer. ) Is intentionally etched with a width wider than the value designed for the wiring width. That is, when the photoresist film is coated on the first oxide film 26, the photoresist film is exposed and developed to form a photoresist pattern (not shown) which exposes the first oxide film in a predetermined region as a wiring hole, the width of the opened portion of the photoresist pattern is designed. A photoresist pattern is formed to have a wider width, and the first oxide film 26 and the nitride film 25 are etched using the photoresist pattern as a mask to form a wiring hole 400 having a width wider than the designed value.
다음, 도 2c에 도시된 바와 같이, 배선구(400)를 포함하여 제1산화막(26)의 상부 전면에 추가막(27)을 2000-4000Å의 두께로 증착한다. 추가막(27)으로는 산화막, 질화막 또는 폴리실리콘막을 증착할 수 있다.Next, as illustrated in FIG. 2C, an additional layer 27 is deposited to a thickness of 2000-4000 μm on the entire upper surface of the first oxide layer 26 including the wiring holes 400. As the additional film 27, an oxide film, a nitride film or a polysilicon film can be deposited.
다음, 도 2d에 도시된 바와 같이, 하부비아(24) 및 제1산화막(26)이 노출될 때까지 추가막(27)을 이방성 식각하여 배선구(400) 내벽의 측방에만 추가막(27)을 남김으로써 사이드월(27')을 형성한다. 사이드월(27')의 형성으로 인해 결과적인 배선구는 상부로 갈수록 폭이 넓어지는 형상을 가진다.Next, as shown in FIG. 2D, the additional layer 27 is anisotropically etched until the lower via 24 and the first oxide layer 26 are exposed, so that the additional layer 27 is only on the side of the inner wall of the wiring port 400. The sidewall 27 'is formed by leaving. Due to the formation of the side walls 27 ', the resulting wiring harness has a shape that becomes wider toward the top.
이어서, 노출된 하부비아(24)를 포함하여 사이드월(27') 및 제1산화막(26)의 상부 전면에 알루미늄, 구리, 또는 구리 합금과 같은 금속물질(28)을 증착하여 배선구를 충분히 매립하도록 두껍게 증착한다.Subsequently, the wiring hole is sufficiently formed by depositing a metal material 28 such as aluminum, copper, or a copper alloy on the upper surface of the sidewall 27 'and the first oxide layer 26 including the exposed lower via 24. Deposit thickly to bury.
다음, 도 2e에 도시된 바와 같이, 제1산화막(26)이 노출될 때까지 금속물질(28)을 화학기계적 연마하거나 또는 에치백하여 상면을 평탄화함으로써 상부배선(28')을 형성한다.Next, as shown in FIG. 2E, the upper wiring 28 ′ is formed by planarizing the upper surface by chemically mechanically polishing or etching back the metal material 28 until the first oxide layer 26 is exposed.
이어서, 평탄화된 상면 상에 층간절연막으로서 제2산화막(29)을 증착한 후, 제2산화막(29) 상에 감광막을 도포하고 이를 노광 및 현상하여 상부 비아로 예정된 영역을 노출시키는 감광막 패턴(미도시)을 형성한 후, 감광막 패턴을 마스크로 하여 제2산화막(29)을 선택적으로 식각하여 비아홀을 형성하고 비아홀에 금속물질을 충진시킴으로써 상부비아(30)를 형성한다. 상부비아(30)로 형성되는 금속물질로는 텅스텐, 알루미늄, 알루미늄합금, 또는 구리를 형성할 수 있다. Subsequently, after depositing the second oxide film 29 as an interlayer insulating film on the planarized upper surface, a photoresist film is applied on the second oxide film 29, and the photoresist film is exposed and developed to expose a predetermined region to the upper via. After forming), the second oxide film 29 is selectively etched using the photoresist pattern as a mask to form a via hole, and the upper via 30 is formed by filling a metal material in the via hole. As the metal material formed of the upper via 30, tungsten, aluminum, an aluminum alloy, or copper may be formed.
이 때, 상부비아(30)와 접촉하는 금속배선(28')의 상부 폭이 보다 더 넓게 형성되어 있기 때문에 상부비아 형성을 위한 감광막 패턴의 정렬 시 여유분이 있어서 공정마진이 확보된다.At this time, since the upper width of the metal wiring 28 ′ in contact with the upper via 30 is formed to be wider, a process margin is secured because there is a margin when the photoresist pattern for forming the upper via is aligned.
상술한 바와 같이, 본 발명에서는 금속배선구를 설계치보다 더 넓게 형성하고 사이드월을 이용하여 금속배선이 상부로 갈수록 더 넓어지는 형상을 가지도록 하기 때문에, 금속배선 상부에 비아를 형성할 때 비아 정렬 오차에 대한 여유분이 있어서 공정마진이 확보되는 효과가 있다.As described above, in the present invention, since the metal wiring holes are formed wider than the designed value and the side walls are used to have a shape in which the metal wiring becomes wider toward the top, the via alignment is formed when the via is formed on the metal wiring. Since there is a margin for error, the process margin is secured.
따라서, 금속배선 상부에 형성하는 비아가 금속배선을 벗어나서 오정렬될 가능성이 최소화되는 효과가 있다.Therefore, there is an effect of minimizing the possibility that the vias formed on the metal wirings are misaligned out of the metal wirings.
도 1a 내지 도 1d는 종래 금속배선 형성 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a conventional metal wiring forming method.
도 2a 내지 도 2e는 본 발명에 따른 금속배선 형성 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method for forming metal wirings according to the present invention.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052267A (en) * | 1995-12-16 | 1997-07-29 | 김주용 | Fine contact hole formation method |
| KR19980060729A (en) * | 1996-12-31 | 1998-10-07 | 김광호 | Metal wiring formation method of semiconductor device |
| KR20000008175A (en) * | 1998-07-10 | 2000-02-07 | 윤종용 | Method of forming contact in semiconductor device and structure of contact |
| KR20000043039A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Method for forming contact hole of semiconductor device |
| KR20030015703A (en) * | 2001-08-17 | 2003-02-25 | 삼성전자주식회사 | Structure Of Dielectric Layer In Multilevel Interconnection And Method Of Forming The Same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052267A (en) * | 1995-12-16 | 1997-07-29 | 김주용 | Fine contact hole formation method |
| KR19980060729A (en) * | 1996-12-31 | 1998-10-07 | 김광호 | Metal wiring formation method of semiconductor device |
| KR20000008175A (en) * | 1998-07-10 | 2000-02-07 | 윤종용 | Method of forming contact in semiconductor device and structure of contact |
| KR20000043039A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Method for forming contact hole of semiconductor device |
| KR20030015703A (en) * | 2001-08-17 | 2003-02-25 | 삼성전자주식회사 | Structure Of Dielectric Layer In Multilevel Interconnection And Method Of Forming The Same |
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