KR100440472B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100440472B1 KR100440472B1 KR10-2001-0079099A KR20010079099A KR100440472B1 KR 100440472 B1 KR100440472 B1 KR 100440472B1 KR 20010079099 A KR20010079099 A KR 20010079099A KR 100440472 B1 KR100440472 B1 KR 100440472B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 깊이가 서로 다른 비아를 동시에 형성하는데 있다. 이를 위해 본 발명에서는 반도체 기판 구조물 상의 제1절연막에 제1금속배선구를 형성하고 제1금속막을 충진하여 제1금속배선을 형성하는 단계; 제1금속배선을 포함한 제1절연막 상부에 제2절연막을 형성하는 단계; 제2절연막을 선택적 식각하여 제1금속배선을 노출시키는 제1비아홀을 형성한 후 제2금속막을 충진하여 제1비아금속을 형성하는 단계; 제1비아금속을 포함한 제2절연막 상부에 제3절연막을 형성하는 단계; 제3절연막을 선택적 식각하여 제2금속배선구 및 제1비아금속을 노출시키는 제2비아홀을 형성한 후 제3금속막을 충진하여 제2금속배선 및 제2비아금속을 형성하는 단계; 제2금속배선 및 제2비아금속을 포함한 제3절연막 상부에 제4절연막을 형성하는 단계; 제4절연막을 선택적 식각하여 제2금속배선 및 제2비아금속을 노출시키는 제3비아홀을 형성한 후 제4금속막을 충진하여 제3비아금속을 형성하는 단계를 순차적으로 수행한다.The present invention relates to a method for manufacturing a semiconductor device, and its purpose is to simultaneously form vias having different depths. To this end, the present invention comprises the steps of forming a first metal wiring hole in the first insulating film on the semiconductor substrate structure and filling the first metal film to form a first metal wiring; Forming a second insulating film on the first insulating film including the first metal wiring; Selectively etching the second insulating layer to form a first via hole exposing the first metal wiring, and then filling the second metal layer to form the first via metal; Forming a third insulating layer on the second insulating layer including the first via metal; Selectively etching the third insulating layer to form a second via hole exposing the second metal wiring hole and the first via metal, and then filling the third metal layer to form the second metal wiring and the second via metal; Forming a fourth insulating layer on the third insulating layer including the second metal wiring and the second via metal; After the third insulating layer is selectively etched to form the third via hole exposing the second metal wiring and the second via metal, the third metal is filled to form the third via metal.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 다층 배선을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a multilayer wiring.
반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring technology has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.
그리고, 반도체 소자에서 다층 배선 기술을 적용함으로써, 교차 배선이 가능하게 되어 반도체 소자의 회로 설계에 있어서의 자유도와 집적도를 향상시킬 수 있으며, 또한 배선 길이를 단축할 수 있어 배선이 수반하는 속도의 지연 시간을 짧게 함으로써 반도체 소자의 동작 속도를 향상시킬 수 있다.By applying the multilayer wiring technology in the semiconductor device, cross wiring is possible, which improves the degree of freedom and integration degree in the circuit design of the semiconductor device, and also reduces the length of the wiring, thereby delaying the speed accompanying the wiring. By shortening time, the operation speed of a semiconductor element can be improved.
이러한 다층 배선 기술을 실현하기 위해, 종래에는 감광막 패턴을 마스크로 이용하여 절연막을 선택적으로 건식 식각함으로써, 하부 배선층까지 연결되는 비아홀을 형성한 후 비아홀 내에 비아 금속을 충진시키고 비아 금속과 접촉하는 상부 배선층을 형성한다.In order to realize such a multi-layered wiring technology, conventionally by dry etching the insulating film using a photosensitive film pattern as a mask, after forming a via hole connected to the lower wiring layer, the via wiring is filled in the via hole and in contact with the via metal. To form.
이 때, 하부 배선층이 상부 배선층으로부터 매우 깊은 깊이로 형성되어 있는 경우에는 비아홀 역시 깊게 형성하여야 한다. 그러나, 깊이가 깊어질수록 건식식각에 의해 비아홀을 형성하기가 어려우며, 일정 깊이 이상으로는 비아홀 형성이 불가능한 문제점이 있었다.At this time, when the lower wiring layer is formed at a very deep depth from the upper wiring layer, the via hole must also be formed deep. However, as the depth becomes deeper, it is difficult to form the via hole by dry etching, and there is a problem in that the via hole cannot be formed beyond a certain depth.
또한, 깊이가 서로 다른 비아는 식각조건의 차이로 인해 각각 형성하여야 하므로 제조 공정이 복잡한 단점이 있었다. 만약, 깊이가 서로 다른 비아를 동시에 형성한다면 깊은 비아를 식각하는 동안에 먼저 형성된 얕은 비아의 하부 배선층이 손상되는 문제점이 있었다.In addition, since vias having different depths must be formed due to differences in etching conditions, the manufacturing process was complicated. If vias having different depths are formed at the same time, there is a problem in that the lower wiring layer of the shallow vias formed first is damaged during deep via etching.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 깊이에 상관없이 비아를 형성하는 데 있다.The present invention is to solve the above problems, the object is to form the vias regardless of the depth.
본 발명의 다른 목적은 깊이가 서로 다른 비아를 동시에 형성하는데 있다.Another object of the present invention is to simultaneously form vias of different depths.
도 1a 내지 도 1e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판 구조물 상의 제1절연막에 제1금속배선구를 형성하고 제1금속막을 충진하여 제1금속배선을 형성하는 단계; 제1금속배선을 포함한 제1절연막상부에 제2절연막을 형성하는 단계; 제2절연막을 선택적 식각하여 제1금속배선을 노출시키는 제1비아홀을 형성한 후 제2금속막을 충진하여 제1비아금속을 형성하는 단계; 제1비아금속을 포함한 제2절연막 상부에 제3절연막을 형성하는 단계; 제3절연막을 선택적 식각하여 제2금속배선구 및 제1비아금속을 노출시키는 제2비아홀을 형성한 후 제3금속막을 충진하여 제2금속배선 및 제2비아금속을 형성하는 단계; 제2금속배선 및 제2비아금속을 포함한 제3절연막 상부에 제4절연막을 형성하는 단계; 제4절연막을 선택적 식각하여 제2금속배선 및 제2비아금속을 노출시키는 제3비아홀을 형성한 후 제4금속막을 충진하여 제3비아금속을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the semiconductor device manufacturing method according to the present invention, forming a first metal wiring hole in the first insulating film on the semiconductor substrate structure and filling the first metal film to form a first metal wiring ; Forming a second insulating film on the first insulating film including the first metal wiring; Selectively etching the second insulating layer to form a first via hole exposing the first metal wiring, and then filling the second metal layer to form the first via metal; Forming a third insulating layer on the second insulating layer including the first via metal; Selectively etching the third insulating layer to form a second via hole exposing the second metal wiring hole and the first via metal, and then filling the third metal layer to form the second metal wiring and the second via metal; Forming a fourth insulating layer on the third insulating layer including the second metal wiring and the second via metal; Selectively etching the fourth insulating layer to form a third via hole exposing the second metal wiring and the second via metal, and then filling the fourth metal layer to form the third via metal.
또는, 반도체 기판 구조물 상의 제1절연막에 제1금속배선구를 형성하고 제1금속막을 충진하여 제1금속배선을 형성하는 단계; 제1금속배선을 포함한 상기 제1절연막 상부에 제2절연막과 제3절연막을 형성하는 단계; 제3절연막을 선택적 식각하여 제2금속배선구를 형성함과 동시에 제3절연막과 제2절연막을 선택적 식각하여 제1금속배선을 노출시키는 제4비아홀을 형성한 후 제3금속막을 충진하여 제2금속배선 및 제4비아금속을 형성하는 단계; 제2금속배선 및 제4비아금속을 포함한 제3절연막 상부에 제4절연막을 형성하는 단계; 제4절연막을 선택적 식각하여 제2금속배선 및 제4비아금속을 노출시키는 제3비아홀을 형성한 후 제4금속막을 충진하여 제3비아금속을 형성하는 단계를 순차적으로 수행하여 반도체 소자를 제조할 수도 있다.Or forming a first metal wiring hole in the first insulating film on the semiconductor substrate structure and filling the first metal film to form the first metal wiring; Forming a second insulating layer and a third insulating layer on the first insulating layer including a first metal wiring; The third insulating layer is selectively etched to form a second metal wiring hole, and the third insulating layer and the second insulating layer are selectively etched to form a fourth via hole exposing the first metal wiring, and then the third metal layer is filled with the second metal wiring hole. Forming a metal wiring and a fourth via metal; Forming a fourth insulating layer on the third insulating layer including the second metal wiring and the fourth via metal; Selectively etching the fourth insulating layer to form a third via hole exposing the second metal wiring and the fourth via metal, and then filling the fourth metal layer to form the third via metal in order to manufacture a semiconductor device. It may be.
상기한 방법들에서, 제1, 3금속막은 Al, Al합금, 또는 Cu의 금속막이며,제2, 4금속막은 W, Al, Al합금, 또는 Cu의 금속막인 것이 바람직하다.In the above methods, it is preferable that the first and third metal films are metal films of Al, Al alloys or Cu, and the second and fourth metal films are metal films of W, Al, Al alloys or Cu.
그리고, 제1 내지 제4금속막의 충진전에 각각 베리어메탈을 증착하는 단계를 더 포함하는 것이 바람직하다.The method may further include depositing barrier metals before filling the first to fourth metal films.
또한, 제1 내지 제4절연막의 형성 후 각각 화학 기계적 연마 또는 에치백에 의해 평탄화하는 단계를 더 포함하는 것이 바람직하다.The method may further include planarization by chemical mechanical polishing or etch back, respectively, after the formation of the first to fourth insulating films.
제1 내지 제4금속막의 충진은 각각 선택적 금속 성장법을 이용하거나 증착 후 평탄화 공정에 의해 수행하는 것이 바람직하다.Filling of the first to fourth metal films is preferably performed by using a selective metal growth method or by a planarization process after deposition.
이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail. 1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판의 구조물(1), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2)의 소정 영역을 식각하여 금속 배선구를 형성한 후 금속물질을 충진하고 하부절연막(2)이 노출될 때까지 화학기계적 연마하여 상부표면을 평탄화함으로써, 제1금속배선(3A)을 형성한다. 제1금속배선은 Al, Al 합금 또는 Cu로 형성한다. 금속 배선구에 금속 물질을 충진하기전 베리어 메탈을 증착할 수도 있다.First, as shown in FIG. 1A, a lower insulating film 2 made of an oxide film or the like is formed on a structure 1 of a semiconductor substrate, that is, on a semiconductor substrate on which individual elements are formed or on a lower metal wiring layer. The first metal wiring 3A is formed by etching a predetermined region to form a metal wiring hole, and then filling the metal material and chemically polishing the upper insulating film 2 until the lower insulating film 2 is exposed to planarize the upper surface. The first metal wiring is formed of Al, Al alloy or Cu. The barrier metal may be deposited before the metal wiring is filled with metal material.
다음, 제1금속배선(3A)을 포함한 상부 전면에 제1절연막(4)을 증착하고 평탄화한 후, 감광막을 도포하고 노광 현상하여 제1비아로 예정된 영역의 상부에 해당하는 감광막을 제거함으로써, 제1감광막 패턴(5)을 형성한다.Next, by depositing and planarizing the first insulating film 4 on the entire upper surface including the first metal wiring 3A, applying a photoresist film and exposing and developing the photoresist film to remove the photoresist film corresponding to the upper portion of the region designated as the first via. The first photosensitive film pattern 5 is formed.
이 때, 제1절연막(4)은 플라즈마 증착법을 이용하여 산화막으로 형성하는 것이 바람직하고, 증착 후 평탄화할 때에는 화학기계적 연마 또는 에치백(etch back) 방법을 이용하여 평탄화하며, 평탄화한 후에는 10000Å 이내의 두께가 되도록 하는 것이 바람직하다. 또한, 제1절연막(4)의 평탄화 후에는 열처리를 수행하는 것이 바람직하다.At this time, the first insulating film 4 is preferably formed of an oxide film by using a plasma deposition method. When the planarization is performed after deposition, the first insulating film 4 is planarized using a chemical mechanical polishing or an etch back method. It is desirable to be within thickness. In addition, heat treatment is preferably performed after the first insulating film 4 is planarized.
다음, 도 1b에 도시된 바와 같이, 제1감광막 패턴(5)을 마스크로 하여 제1절연막(4)을 식각하여 하부의 제1금속배선(3A)과 연결되는 제1비아홀(100A)을 형성한 후, 제1감광막 패턴(5)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 1B, the first insulating layer 4 is etched using the first photoresist pattern 5 as a mask to form a first via hole 100A connected to the lower first metal wiring 3A. After that, the first photoresist pattern 5 is removed and a cleaning process is performed.
다음, 제1비아홀(100A) 내에 제1비아금속(6)을 충진시킨 후, 제1비아금속(6) 및 제1절연막(4)을 포함한 상부 전면에 제2절연막(7)을 증착하고 평탄화한다.Next, after the first via metal 6 is filled in the first via hole 100A, the second insulating film 7 is deposited and planarized on the entire upper surface including the first via metal 6 and the first insulating film 4. do.
이 때, 제1비아금속(6)을 충진하기 전에 반도체 기판을 플라즈마 및 케미컬 중의 어느 하나 이상에 노출시켜 비아의 바닥을 세정하는 것이 바람직하고, 제1비아금속(6)은 W, Al, Al 합금, 또는 Cu 등을 선택적 금속성장법으로 형성하거나 증착 후 화학 기계적 연마 또는 에치백에 의한 평탄화에 의해 형성하며, 제1비아금속의 형성 후에는 열처리를 수행하는 것이 바람직하다.At this time, before filling the first via metal 6, the semiconductor substrate is exposed to any one or more of plasma and chemical to clean the bottom of the via, and the first via metal 6 is W, Al, Al. It is preferable to form an alloy, Cu, or the like by a selective metal growth method or by chemical mechanical polishing or planarization by etching back after deposition, and heat treatment is performed after the formation of the first via metal.
제2절연막(7)은 플라즈마 증착법을 이용하여 산화막으로 형성하는 것이 바람직하고, 증착 후에는 화학기계적 연마 또는 에치백 방법을 이용하여 평탄화하며, 평탄화한 후에는 10000Å 이내의 두께가 되도록 하는 것이 바람직하다. 또한, 제2절연막(7)의 평탄화 후에는 열처리를 수행하는 것이 바람직하다. 이때, 제1비아홀(100A)에 제1비아금속(6)을 충진하기전 베리어 메탈을 증착할 수도 있다.The second insulating film 7 is preferably formed of an oxide film by using a plasma deposition method, and after deposition, is planarized by a chemical mechanical polishing or etch back method, and after the planarization, the second insulating film 7 preferably has a thickness of 10000 kPa or less. . In addition, it is preferable to perform heat treatment after the planarization of the second insulating film 7. In this case, the barrier metal may be deposited before the first via metal 6 is filled in the first via hole 100A.
이어서, 제2절연막(7) 상부에 감광막을 도포하고 노광 현상하여 제2비아 및 제2금속배선구로 예정된 영역의 상부에 해당하는 감광막을 제거함으로써, 제2감광막 패턴(8)을 형성한다.Subsequently, the second photoresist pattern 8 is formed by applying a photoresist film over the second insulating film 7 and exposing the photoresist to remove the photoresist film corresponding to the upper portion of the region defined as the second via and the second metal wiring hole.
다음, 제2감광막 패턴(8)을 마스크로 하여 제2절연막(7)을 식각하여 도 1c에 도시된 바와 같이 제2금속배선구(150), 및 제1비아금속(6)과 연결되는 제2비아홀(100B)을 형성한 후, 제2감광막 패턴(8)을 제거하고 세정공정을 수행한다.Next, the second insulating layer 7 is etched using the second photoresist layer pattern 8 as a mask to connect the second metal wire 150 and the first via metal 6 as shown in FIG. 1C. After forming the second via hole 100B, the second photoresist pattern 8 is removed and a cleaning process is performed.
다음, 제2금속배선구(150) 및 제2비아홀(100B) 내에 각각 제2금속배선(3B) 및 제2비아금속(9)을 형성하여 충진시킨 후, 상부 전면에 제3절연막(10)을 증착하고 평탄화한다.Next, the second metal wiring 3B and the second via metal 9 are formed and filled in the second metal wiring hole 150 and the second via hole 100B, respectively, and then the third insulating layer 10 is formed on the entire upper surface of the second metal wiring hole 150 and the second via hole 100B. Is deposited and planarized.
이 때, 제2금속배선(3B) 및 제2비아금속(9)을 형성하기 전에 반도체 기판을 플라즈마 및 케미컬 중의 어느 하나 이상에 노출시켜 제2비아홀(10B)의 바닥을 세정하는 것이 바람직하고, 제2금속배선(3B)과 제2비아금속(9)은 Al, Al 합금, 또는 Cu 등의 금속막을 선택적 금속성장법으로 형성하거나 증착후 평탄화에 의해 형성하며, 제2금속배선(3B)과 제2비아금속(9)의 형성 후에는 열처리를 수행한다. 또한, 제2금속배선(3B)과 제2비아금속(9)의 형성전 제2금속배선구(150)와 제2비아홀(100B)에 베리어메탈을 증착할 수도 있다.At this time, before forming the second metal wiring 3B and the second via metal 9, it is preferable to expose the semiconductor substrate to at least one of plasma and chemical to clean the bottom of the second via hole 10B. The second metal wiring 3B and the second via metal 9 are formed of a metal film such as Al, Al alloy, or Cu by selective metal growth, or by planarization after deposition, and the second metal wiring 3B and the second metal wiring 3B. After the formation of the second via metal 9, heat treatment is performed. In addition, barrier metal may be deposited in the second metal wiring hole 150 and the second via hole 100B before the second metal wiring 3B and the second via metal 9 are formed.
그리고, 제3절연막(10)은 플라즈마 증착법을 이용하여 산화막으로 형성하는 것이 바람직하고, 증착 후에는 화학기계적 연마 또는 에치백 방법을 이용하여 평탄화하며, 평탄화 후에는 10000Å 이내의 두께가 되도록 하는 것이 바람직하다. 또한, 제3절연막(10)의 평탄화 후에는 열처리를 수행하는 것이 바람직하다.The third insulating film 10 is preferably formed of an oxide film by using a plasma deposition method. After deposition, the third insulating film 10 is preferably flattened by a chemical mechanical polishing or etch back method. Do. In addition, heat treatment may be performed after the third insulating film 10 is planarized.
이어서, 감광막을 도포하고 노광 현상하여 제3비아로 예정된 영역의 상부에 해당하는 감광막을 제거함으로써, 제3감광막 패턴(11)을 형성한다.Subsequently, the third photosensitive film pattern 11 is formed by coating and exposing the photosensitive film to remove the photosensitive film corresponding to the upper portion of the region defined as the third via.
다음, 제3감광막 패턴(11)을 마스크로 하여 제3절연막(10)을 식각하여 도 1d에 도시된 바와 같이 제2금속배선(150) 및 제2비아금속(9)과 각각 연결되는 제3비아홀(200, 100C)를 형성한 후, 제3감광막 패턴(11)을 제거하고 세정공정을 수행한다.Next, a third insulating layer 10 is etched using the third photoresist layer pattern 11 as a mask to be connected to the second metal wire 150 and the second via metal 9, respectively, as shown in FIG. 1D. After the via holes 200 and 100C are formed, the third photoresist pattern 11 is removed and a cleaning process is performed.
다음, 제3비아홀(200, 100C) 내에 제3비아금속(12)을 형성하여 충진시킨 후, 상부 전면에 상부금속배선(13)을 증착한다.Next, after the third via metal 12 is formed and filled in the third via holes 200 and 100C, the upper metal wiring 13 is deposited on the entire upper surface.
이 때, 제3비아홀(200, 100C)에 제3비아금속(12)을 충진하기 전에 반도체 기판을 플라즈마 및 케미컬 중의 어느 하나 이상에 노출시켜 비아의 바닥을 세정하는 것이 바람직하고, 제3비아금속(12)은 W, Al, Al 합금, 또는 Cu 등의 금속막을 선택적 금속성장법으로 형성하거나 증착후 평탄화에 의해 형성하며, 제3비아금속(12)의 형성 후에는 열처리를 수행하며, 상부금속배선(13)은 Al, Al 합금 또는 Cu로 형성한다. 또한, 제3비아금속(12)의 형성전에 제3비아홀(200, 100C)에 베리어메탈을 증착할 수도 있다.At this time, before filling the third via metal 12 in the third via holes 200 and 100C, it is preferable to expose the semiconductor substrate to at least one of plasma and chemical to clean the bottom of the via. (12) forms a metal film such as W, Al, Al alloy, or Cu by the selective metal growth method or by the planarization after deposition, and after the formation of the third via metal 12, heat treatment is performed, and the upper metal The wiring 13 is made of Al, Al alloy or Cu. In addition, barrier metal may be deposited in the third via holes 200 and 100C before the third via metal 12 is formed.
상부금속배선(13) 상에는 제4감광막을 도포하고 노광 현상하여 일정부분의 감광막만 제거한 다음, 이를 마스크로 하여 상부금속배선(13)의 일정영역을 식각함으로써, 도 1e에 도시된 바와 같이, 제1금속배선(3A) 및 제2금속배선(3B)와 각각 연결되는 상부금속배선이 서로 분리되어 반도체 소자의 내부 회로를 형성하도록함으로써, 본 발명에 따른 다층 비아 형성 공정을 완료한다.By applying a fourth photoresist film on the upper metal wiring 13 and exposing and developing the photoresist film, only a portion of the photoresist film is removed, and then a predetermined region of the upper metal wiring 13 is etched using the mask as shown in FIG. 1E. The upper metal wirings respectively connected to the first metal wiring 3A and the second metal wiring 3B are separated from each other to form an internal circuit of the semiconductor device, thereby completing the multilayer via forming process according to the present invention.
그러나, 본 발명은 상기한 바와 같은 실시예에 국한되지 않으며, 다양하게 변형될 수 있다.However, the present invention is not limited to the embodiment as described above, and may be variously modified.
일 예로, 제1비아홀(100A)을 제2비아홀(100B) 형성시 동시에 형성할 수도 있다. 즉, 제1절연막(4)을 선택적으로 식각하여 제1비아홀(100A)을 형성하는 대신에, 제2절연막(7) 식각시 제1절연막(4)까지 식각하여 제1비아홀(100A)을 형성할 수도 있다.For example, the first via hole 100A may be simultaneously formed when the second via hole 100B is formed. In other words, instead of selectively etching the first insulating layer 4 to form the first via hole 100A, the first insulating layer 4 is etched to form the first via hole 100A when the second insulating layer 7 is etched. You may.
그리고, 본 발명은 깊이가 더 깊거나 얕은 비아 형성 공정에도 적용할 수 있으며, 일 예로, 제3비아를 포함하여 제3절연막의 상부 전면에 다수층의 절연막 및 제2비아와 연결되는 다수층의 비아를 더 형성한 후에 상부 금속배선막을 형성함으로써, 더욱 깊은 비아를 형성할 수도 있다.In addition, the present invention may be applied to a deeper or shallower via formation process. For example, a plurality of layers connected to a plurality of insulating layers and a second via are formed on the entire upper surface of the third insulating layer including the third via. Deeper vias may be formed by forming the upper metallization film after further forming vias.
상술한 바와 같이, 본 발명에서는 절연막을 한층씩 증착하고 선택적으로 식각하여 비아를 형성하므로 아무리 깊은 비아라도 형성이 가능한 효과가 있다.As described above, in the present invention, since the insulating film is deposited one by one and selectively etched to form vias, no matter how deep the vias can be formed.
또한, 절연막을 한층씩 증착하고 선택적으로 식각하여 비아를 형성할 때 금속배선구를 동시에 형성하고 이 때 형성된 금속배선구와 연결되는 비아 역시 마찬가지의 방법으로, 즉 절연막을 한층씩 증착하고 선택적으로 식각하여 다수개의 비아를 동시에 형성하므로, 결과적으로 깊이가 서로 다른 비아를 동시에 형성하는 효과가 있으며, 이로 인해 공정이 간단해지는 효과가 있다.In addition, when the insulating film is deposited one by one and selectively etched to form vias, the metal wiring holes are simultaneously formed and the vias connected to the formed metal wiring holes are similarly formed, that is, the insulating film is deposited one by one and selectively etched. Since a plurality of vias are formed at the same time, as a result, there is an effect of simultaneously forming vias having different depths, thereby simplifying the process.
따라서, 종래 깊이가 서로 다른 비아를 동시에 형성할 때 문제가 되었던 얕은 비아의 금속배선이 손상되는 일이 방지되는 효과가 있다.Therefore, there is an effect that the metal wiring of the shallow via, which is a problem when forming vias having different depths at the same time, is prevented from being damaged.
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| JPH04211121A (en) * | 1990-02-14 | 1992-08-03 | Toshiba Corp | Semiconductor device and fabrication thereof |
| JPH07122644A (en) * | 1993-10-26 | 1995-05-12 | Nec Corp | Semiconductor device and fabrication thereof |
| KR20000061188A (en) * | 1999-03-24 | 2000-10-16 | 윤종용 | Wiring line structure body for semiconductor device &manufacturing method thereof |
| JP2000357737A (en) * | 1999-06-15 | 2000-12-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
| KR20010062217A (en) * | 1999-12-07 | 2001-07-07 | 추후제출 | Integrated circuit and process for producing the same |
| JP2001250824A (en) * | 2000-03-03 | 2001-09-14 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacturing method |
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