JP4110829B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a dual damascene process in which, for example, a wiring groove and a connection hole are filled with a conductive material to form a wiring and a contact at the same time.
[0002]
[Prior art]
With the progress of miniaturization of LSI, the influence on the LSI performance due to the wiring resistance and the wiring capacitance is becoming a value that cannot be ignored. In a wiring structure in which aluminum (Al) is used as a wiring material and silicon oxide (SiO ₂ ) is used as an interlayer insulating film, the ratio of wiring delay to the whole increases rapidly after the 0.18 μm generation.
[0003]
In order to reduce the inter-wiring capacitance and wiring resistance while suppressing the reduction in the spacing between adjacent wirings and the increase in the facing area between the wirings, the insulating material is made of a material having a lower dielectric constant than conventional silicon oxide. For example, LSIs using copper (Cu) instead of aluminum are being developed. Since copper has a lower specific resistance and a higher melting point than aluminum, it is expected to reduce wiring delay and greatly improve reliability.
[0004]
For fine wiring pattern processing, a metal layer made of aluminum has been formed on the entire surface, and an etching-resistant mask is put on this, and unnecessary metal regions are removed by etching to form a desired wiring structure. It was.
[0005]
However, in the case of copper wiring, since it is practically difficult to form a fine structure by dry etching, a method of forming a wiring groove in the insulating film in advance by etching the insulating film and embedding copper in the wiring groove, so-called damascene (Damascene) method is used. In particular, the dual damascene method, in which copper is collectively embedded after forming connection holes for connecting upper and lower wirings and wiring grooves for upper layer wirings in advance, is the center of development.
[0006]
However, in the dual damascene method, as the wiring becomes finer, it becomes difficult to embed copper in the connection hole and the wiring groove without any gap. As a result, voids are easily formed in the connection hole, resulting in poor conductivity. There is a problem that it is easy.
[0007]
In order to solve the above problems, as a dual damascene process, for example, there are techniques described in Japanese Patent Laid-Open Nos. 10-229122 and 2000-299376.
[0008]
In the technique disclosed in Japanese Patent Laid-Open No. 10-229122, the interlayer insulating film is half-etched with the pattern of the connecting hole to form the connecting hole partway through the interlayer insulating film, and then the interlayer insulating film is formed into the wiring groove pattern. Etching is performed to form a wiring groove and a connection hole reaching the lower layer wiring. At the time of etching for forming the wiring groove at this time, the end portion of the connection hole on the wiring groove side which is a corner portion is also etched so that the opening diameter of the connection hole is directed toward the wiring groove. In this way, the embedding property is improved in the embedding of the wiring material into the wiring groove and the connection hole performed thereafter.
[0009]
In the technique described in Japanese Patent Application Laid-Open No. 2000-299376, two layers of a lower insulating film and an upper insulating film are formed. First, an opening is formed in the upper insulating film with a pattern of connection holes, and a tapered shape is formed on the lower insulating film. Then, a connection hole is formed by etching, and then a wiring groove is formed in the upper insulating film.
[0010]
[Problems to be solved by the invention]
However, in the technique described in Japanese Patent Application Laid-Open No. 10-229122, when the wiring groove is formed by etching, variation in the etching depth occurs in the substrate surface, and the wiring film thickness to be formed in the wiring groove later. As a result, there is a problem that the wiring resistance and the capacitance between the wirings become large.
[0011]
In the technique described in Japanese Patent Application Laid-Open No. 2000-299376, when forming the connection hole in the lower insulating film, the etching is performed under the etching condition such that the diameter continuously decreases from the upper end to the lower end. For this reason, if the area of the lower end of the connection hole is not secured, problems such as an increase in resistance will occur. If the diameter of the upper end of the connection hole is made sufficiently large, it is possible to secure the area of the lower end of the connection hole, but there are cases where it is difficult to ensure the area of the lower end due to restrictions on the design rules. .
[0012]
The present invention has been made in view of the above circumstances, and its purpose is to suppress the variation in the depth of the wiring groove and the connection hole and to the connection hole in a state where the connection area with the lower layer wiring is secured. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the embedding property of the conductive material.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a lower wiring, a step of forming an etching stopper layer on the first insulating film, Forming a second insulating film on the stopper layer; removing the second insulating film, the stopper layer and the first insulating film by etching to form a connection hole; and until the stopper layer is exposed. When removing the second insulating film in the step of removing the second insulating film by etching to form a wiring groove in the second insulating film and the step of forming the wiring groove in the second insulating film. Etching that is the same as the etching performed is further continued, and the stopper layer and the first insulating film in the connecting portion between the wiring groove and the connection hole are shaved, and the diameter of the end portion of the connection hole on the wiring groove side Expand It has a degree, and a step of embedding said wiring groove and the connection hole with a conductive material.
[0014]
After the step of expanding the diameter of the end portion of the connection hole on the wiring groove side, before the step of embedding the wiring groove and the connection hole with a conductive material, a step of removing the stopper layer exposed in the wiring groove Also have.
[0015]
Before the step of forming the first insulating film, the method further includes a step of forming a lower layer stopper layer serving as an etching stopper on the lower layer wiring, and in the step of forming the connection hole, the lower layer stopper layer is exposed. After the step of forming the connection hole to be expanded and expanding the diameter of the end portion of the connection hole on the wiring groove side, before the step of embedding the wiring groove and the connection hole with a conductive material, the exposure of the connection hole The method further includes a step of removing the lower stopper layer and the stopper layer exposed in the wiring groove.
[0016]
The step of filling the wiring groove and the connection hole with a conductive material includes the step of depositing a conductive material on the second insulating film so as to fill the wiring groove and the connection hole, and the step of filling the wiring groove and the connection hole. Removing the conductive material deposited on the second insulating film by polishing while leaving the conductive material left.
[0017]
In the step of filling the wiring groove and the connection hole with a conductive material, a conductive material containing copper is embedded.
[0018]
Prior to the step of depositing a conductive material on the second insulating film, a barrier film is formed on the second insulating film to cover the inner surfaces of the wiring grooves and the connection holes and prevent copper diffusion. And further comprising a step of depositing the conductive material containing copper on the barrier film so as to fill the wiring trench and the connection hole, and removing the conductive material by polishing. The barrier film and the conductive material deposited on the second insulating film are removed by polishing while leaving the barrier film and the conductive material buried in the wiring trench and the connection hole.
[0019]
In the manufacturing method of the semiconductor device of the present invention, first, the connection hole in a state where the area of the lower end is secured by forming the connection hole by removing the second insulating film, the stopper layer, and the first insulating film by etching. Is formed.
Next, the second insulating film is removed by etching until the stopper layer is exposed, and a wiring groove is formed in the second insulating film. At this time, since the stopper layer serves as an etching stopper, the wiring groove is formed in a state where variation in the depth of the wiring groove to be formed is suppressed.
Next, by continuing the same etching as the etching performed when removing the second insulating film in the step of forming the wiring groove in the second insulating film, the stopper layer at the connecting portion between the wiring groove and the connecting hole, and The first insulating film is shaved to increase the diameter of the end of the connection hole on the wiring groove side. Thereby, the diameter of the edge part of the connection hole by the side of a wiring groove will expand in the state which ensured the connection area with the lower layer wiring of a connection hole.
Thereafter, the wiring groove and the connection hole are filled with a conductive material. At this time, since the diameter of the end portion of the connection hole on the wiring groove side is expanded, it is easy to embed the conductive material in the connection hole.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
[0021]
FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a dual damascene structure manufactured by the method for manufacturing a semiconductor device according to this embodiment.
A lower insulating film 11 made of, for example, silicon oxide is formed on a semiconductor substrate 10 on which a MOS transistor or other semiconductor element is formed. An opening reaching the semiconductor substrate 10 is formed in the lower insulating film 11. A barrier metal 12 made of Ta, Ti, TaN, TiN or the like that covers the inner wall surface of the opening to prevent diffusion of copper is formed, and a conductive layer 13 such as copper is embedded therein, The barrier metal 12 and the conductive layer 13 embedded in the insulating film 11 form a first layer wiring W1 which is a lower layer wiring. Although not shown, the first layer wiring W1 is connected to a semiconductor element or the like formed on the semiconductor substrate 10 via a first layer contact.
[0022]
On the lower insulating film 11 and the first layer wiring W1, a diffusion preventing film 14 for preventing diffusion of copper made of, for example, silicon nitride is formed, and on the diffusion preventing film 14, a first made of, for example, silicon oxide or the like is formed. An insulating film 15 is formed.
[0023]
An etching stopper film 16 made of, for example, silicon nitride or the like is formed on the first insulating film 15, and a second insulating film 17 made of, for example, silicon oxide or the like is formed on the etching stopper film 16. ing.
[0024]
A wiring groove 17a is formed in the second insulating film 17 and the etching stopper film 16, and the upper surface of the first layer wiring W1 is exposed through the first insulating film 15 and the diffusion prevention film 14. A connection hole 15a is formed in communication with the wiring groove 17a.
[0025]
In the present embodiment, the diameter of the connection hole 15a formed in the first insulating film 15 has a shape that widens at the end on the wiring groove 17a side so that the conductive material can be easily embedded in the connection hole 15a. It has become.
[0026]
A barrier metal 18 made of, for example, Ta, Ti, TaN, TiN or the like that prevents diffusion of copper is formed so as to cover the inner wall surfaces of the connection hole 15a and the wiring groove 17a that communicate with each other. A conductive layer 19 is embedded and formed.
A second layer wiring W2 is constituted by the barrier metal 18 and the conductive layer 19 buried in the wiring groove 17a, and a second layer contact C2 is constituted by the barrier metal 18 and the conductive layer 19 buried in the connection hole 15a. Yes.
In the above structure, the second layer wiring W2 is connected to the first layer wiring W1 which is the lower layer wiring through the second layer contact C2.
[0027]
Next, a method for manufacturing the semiconductor device having the above configuration will be described with reference to FIGS.
[0028]
First, steps up to FIG. 2A will be described.
On the semiconductor substrate 10 on which a MOS transistor or other semiconductor element is formed and contacts (not shown) are embedded in the insulating film, silicon oxide is deposited by, for example, a CVD (Chemical Vapor Deposition) method, and the lower insulating film 11 Form.
Subsequently, an opening for embedding wiring is formed in the lower insulating film 11, a material such as Ta, Ti, TaN, TiN is formed in the opening to form a barrier metal 12, and further made of copper. The conductive layer 13 is deposited, and the excess barrier metal 12 and the conductive layer 13 on the lower insulating film 11 are removed and planarized by a CMP (Chemical Mechanical Polishing) method, thereby forming a lower layer as shown in FIG. A first layer wiring W1 made of the conductive layer 13 and the barrier metal 12 embedded in the insulating film 11 is formed.
[0029]
Next, as shown in FIG. 2B, a diffusion preventing film 14 for preventing diffusion of copper is formed on the lower insulating film 11 and the first layer wiring W1 by depositing silicon nitride, for example, by a CVD method. Further, silicon oxide is deposited on the diffusion prevention film 14 by, for example, a CVD method to form the first insulating film 15. At this time, the first insulating film 15 and the diffusion prevention film 14 are formed so that the total film thickness becomes the height of a contact to be formed later.
[0030]
Next, as shown in FIG. 3C, silicon nitride is deposited on the first insulating film 15 by, for example, a CVD method to form an etching stopper film 16, and further, silicon oxide is formed thereon by, for example, the CVD method. A second insulating film 17 is formed by depositing the film. At this time, the total film thickness of the second insulating film 17 and the etching stopper film 16 is formed to be a wiring film thickness to be formed later.
[0031]
Next, as shown in FIG. 3D, a resist is applied on the second insulating film 17, and a resist mask R1 is formed on the second insulating film 17 in a pattern of connection holes by photolithography. To do.
[0032]
Next, as shown in FIG. 4E, by performing etching such as RIE using the resist mask R1 as an etching mask, the second insulating film 17, the etching stopper film 16, and the first insulating film 15 are sequentially removed. Then, a connection hole 15 b is formed in the first insulating film 15. At this time, the etching conditions of the second insulating film 17 made of silicon oxide, the etching stopper film 16 made of silicon nitride, and the etching of the first insulating film 15 made of silicon oxide are changed.
[0033]
Next, as shown in FIG. 4F, the resist mask R1 opening in the connection hole pattern is removed.
[0034]
Next, as shown in FIG. 5G, a resist is again applied on the second insulating film 17, and a resist mask R2 that opens in the pattern of the wiring trench is formed on the second insulating film 17 by photolithography. Patterning is formed.
[0035]
Next, as shown in FIG. 5H, the second insulating film 17 made of silicon oxide selectively with respect to the silicon nitride film of the diffusion prevention film 14 and the etching stopper film 16 using the resist mask R2 as an etching mask. By etching the second insulating film 17 made of silicon oxide under the condition that can be removed by etching, a wiring groove 17 a is formed in the second insulating film 17.
[0036]
Next, as shown in FIG. 6I, the above etching is further continued, that is, the etching is performed to the thickness of the second insulating film 17 or more, so that the end of the connection hole 15b on the wiring groove 17a side. Then, the etching stopper film 16 in the portion which has become the corner portion A in the step shown in FIG. 5H is shaved by the physical sputtering action of the etching, and further made of silicon oxide in the exposed corner portion A. By etching the first insulating film 15, a connection hole 15 a in which the diameter of the end portion on the wiring groove 17 a side is widened is formed.
In this process, the diameter of the connection hole 15b and the width of the wiring groove 17a as shown on the right side of FIG. 5 (h) are substantially the same, and the diameter at the connecting portion from the wiring groove 17a to the connection hole 15b. In the flat portion B where there is no corner (stepped portion) due to the difference of the above, since the sputtering action does not occur as in the corner A, the end of the connection hole 15a on the wiring groove 17a side is the wiring groove. It does not spread beyond the width of 17a.
[0037]
Next, as shown in FIG. 6J, the resist mask R2 opening in the wiring groove pattern is removed.
[0038]
Next, as shown in FIG. 7 (k), the etching stopper film 16 made of silicon nitride exposed in the wiring groove 17a and the diffusion prevention film 14 made of silicon nitride exposed in the connection hole 15a are removed by etching. The connecting hole 15a is connected to the bottom of the wiring groove 17a to expose the first layer wiring W1.
[0039]
Next, as shown in FIG. 7L, the inner wall surfaces of the connection holes 15a and the wiring grooves 17a are covered, and a material such as Ta, Ti, TaN, or TiN that prevents copper diffusion is sputtered over the entire surface. The barrier metal 18 is formed by depositing by the method.
[0040]
Next, as shown in FIG. 8 (m), a conductive layer made of, for example, copper is formed on the barrier metal 18 until the inside of the connection hole 15a and the wiring groove 17a is buried by sputtering, CVD, or plating. 19 is deposited. Note that the conductive layer 19 is deposited by electrolytic plating after forming a seed film (not shown) with the same material as the conductive layer 19 by sputtering.
[0041]
As a subsequent process, the excess conductive layer 19 and the barrier metal 18 on the second insulating film 17 are removed and planarized by the CMP method, and the conductive layer 19 and the barrier metal 18 are only in the connection hole 15a and the wiring groove 17a. As a result, the second layer wiring W2 is formed by the barrier metal 18 and the conductive layer 19 embedded in the wiring groove 17a, and the second layer contact C2 is formed by the barrier metal 18 and the conductive layer 19 embedded in the connection hole 15a. It is formed.
[0042]
When forming the third and subsequent wiring layers, the multilayer wiring is formed by repeating the steps of FIGS. 2B to 8M. As described above, the semiconductor device having the dual damascene structure shown in FIG. 1 is manufactured.
[0043]
According to the manufacturing method of the semiconductor device according to the above-described embodiment, in the step shown in FIG. 4E, etching such as RIE is performed using the resist mask R1 opening in the connection hole pattern as an etching mask. After forming the connection hole 15b with the bottom surface area secured in the insulating film 15, the wiring groove 17a shown in FIG. 5 (h) is etched to a thickness greater than that of the second insulating film 17. Then, the etching stopper film 16 which is the end portion of the connection hole 15b on the wiring groove 17a side and is the corner A is shaved by a physical sputtering action at the time of etching, and the exposed first insulating film 15 is etched. As a result, it is possible to form the connection hole 15a in which only the diameter of the end portion on the wiring groove 17a side as shown in FIG. 6 (i) is expanded, so that the bottom area of the connection hole 15a is ensured. While, it is possible to expand only the upper shape.
Therefore, the embedding property of the conductive layer 19 deposited thereafter can be improved, and the formation of voids in the connection holes can be prevented.
[0044]
FIG. 9 shows an example of a top view after the wiring groove 17a and the connection hole 15a are processed in the step shown in FIG. 6 (i). The processed connection hole 15a has a shape in which the diameter of the upper end 15a-2 is expanded in the wiring groove 17a with respect to the lower end 15a-1.
Here, as described above, in the wiring groove 17a and the connection hole 15a as shown on the right side of FIG. 9, in the portion where the diameter of the connection hole 15a and the width of the wiring groove 17a are substantially the same, the wiring groove 17a Since the connecting portion to the connection hole 15a is a flat portion and the shape does not change due to the sputtering action during etching, the end of the connection hole 15a on the wiring groove 17a side is larger than the width of the wiring groove 17a. It won't spread. Therefore, there is no problem that the diameter of the upper end 15a-2 of the connection hole 15a is unnecessarily widened and short-circuited with the adjacent wiring. Even in this case, since the diameter of the upper end 15a-2 of the connection hole 15a increases in the extending direction of the wiring groove 17a, the embedding property of the conductive layer 19 in the connection hole 15a is improved.
[0045]
In the present embodiment, since the etching stopper film 16 is provided between the second insulating film 17 and the first insulating film 15, the second insulating film 17 can be prevented from being etched more than necessary. In addition, since variation in the depth of the wiring groove 17a in the substrate surface can be suppressed, it is possible to improve the uniformity of the film thickness of wiring formed later by embedding the barrier metal 18 and the conductive layer 19.
[0046]
As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, the variation in the depth of the wiring groove 17a and the connection hole 15a is suppressed, and the connection area with the lower layer wiring W1 is secured. The embedding property of the conductive layer 19 in the connection hole 15a can be improved. Therefore, even when the wiring width is further reduced, the generation of voids in the connection holes can be suppressed.
[0047]
The method for manufacturing a semiconductor device of the present invention is not limited to the description of the above embodiment.
For example, in the present embodiment, an example in which silicon oxide is used for the first insulating film 15 and the second insulating film 17 has been described. However, the present invention is not limited to this, and a xerogel having a dielectric constant of 3.0 or less is used. A low dielectric constant material can also be used.
[0048]
In the present embodiment, an example of the material of the barrier metals 12 and 18 has been described. However, the present invention is not limited to this, and various materials having a function as a barrier metal can be used. , 19 can be made of a material other than copper.
[0049]
In this embodiment, the diffusion prevention film 14 made of an insulating film for preventing copper diffusion is inserted between the wiring layers, and the diffusion prevention film 14 is also used as an etching stopper layer when the connection hole 15a is formed. However, only the exposed surface of copper may be selectively electrolessly plated with a material such as CoWP to form a barrier metal that prevents copper diffusion.
In addition, various modifications can be made without departing from the scope of the present invention.
[0050]
【The invention's effect】
According to the present invention, it is possible to improve the embedding property of the conductive material in the connection hole while suppressing the variation in the depth of the wiring groove and the connection hole and securing the connection area with the lower layer wiring.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a dual damascene structure manufactured by a method for manufacturing a semiconductor device according to an embodiment.
FIG. 2 is a cross-sectional view after forming a first insulating film in the manufacture of the semiconductor device according to the embodiment;
FIG. 3 is a cross-sectional view after forming a resist mask opening in a pattern of connection holes on the second insulating film in the manufacture of the semiconductor device according to the embodiment;
FIG. 4 is a cross-sectional view after forming a connection hole in the first insulating film in manufacturing the semiconductor device according to the embodiment;
FIG. 5 is a cross-sectional view after forming a wiring trench in the second insulating film in manufacturing the semiconductor device according to the embodiment;
6 is a cross-sectional view after enlarging the diameter of the upper end of the connection hole in the manufacture of the semiconductor device according to the embodiment. FIG.
7 is a cross-sectional view of the semiconductor device according to the present embodiment after deposition of barrier metal in the wiring trench and the connection hole in the manufacturing process.
8 is a cross-sectional view after the conductive layer is deposited in the wiring groove and the connection hole in the manufacture of the semiconductor device according to the embodiment. FIG.
FIG. 9 is a top view after formation of wiring grooves and connection holes in the manufacture of the semiconductor device according to the embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Lower layer insulating film, 12 ... Barrier metal, 13 ... Conductive layer, 14 ... Diffusion prevention film, 15 ... 1st insulating film, 15a, 15b ... Connection hole, 15a-1 ... Lower end of connection hole, 15a-2 ... upper end of connection hole, 16 ... etching stopper film, 17 ... second insulating film, 17a ... wiring groove, 18 ... barrier metal, 19 ... conductive layer, W1 ... first layer wiring, W2 ... second layer wiring , C2 ... second layer contact, R1, R2 ... resist mask, A ... corner, B ... flat part.

Claims (6)

Forming a first insulating film on the lower wiring;
Forming an etching stopper layer on the first insulating film;
Forming a second insulating film on the stopper layer;
Removing the second insulating film, the stopper layer and the first insulating film by etching to form a connection hole;
Removing the second insulating film by etching until the stopper layer is exposed, and forming a wiring groove in the second insulating film;
The stopper layer at the connecting portion between the wiring groove and the connection hole is further continued by performing the same etching as that performed when removing the second insulating film in the step of forming the wiring groove in the second insulating film. And scraping the first insulating film to expand the diameter of the end of the connection hole on the wiring groove side,
And a step of filling the wiring groove and the connection hole with a conductive material. After the step of expanding the diameter of the end portion of the connection hole on the wiring groove side, before the step of embedding the wiring groove and the connection hole with a conductive material, a step of removing the stopper layer exposed in the wiring groove The method for manufacturing a semiconductor device according to claim 1, further comprising: Before the step of forming the first insulating film, further comprising a step of forming a lower layer stopper layer serving as an etching stopper on the lower layer wiring,
In the step of forming the connection hole, a connection hole that exposes the lower stopper layer is formed,
After the step of expanding the diameter of the end portion of the connection hole on the wiring groove side, before the step of embedding the wiring groove and the connection hole with a conductive material, the lower layer stopper layer and the wiring groove exposed in the connection hole The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the stopper layer exposed to the surface. The step of embedding the wiring groove and the connection hole with a conductive material,
Depositing a conductive material on the second insulating film so as to fill the wiring trench and the connection hole;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the conductive material deposited on the second insulating film by polishing while leaving the conductive material embedded in the wiring trench and the connection hole. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of filling the wiring groove and the connection hole with a conductive material, a conductive material containing copper is embedded. Prior to the step of depositing a conductive material on the second insulating film, a barrier film is formed on the second insulating film to cover the inner surfaces of the wiring grooves and the connection holes and prevent copper diffusion. And further comprising a step,
In the step of depositing the conductive material, the conductive material containing copper is deposited on the barrier film so as to fill the wiring trench and the connection hole,
In the step of removing the conductive material by polishing, the barrier film and the conductive material deposited on the second insulating film while leaving the barrier film and the conductive material embedded in the wiring trench and the connection hole are removed. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is removed by polishing.

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