JP2003332421A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein embedding property of a conducting material into a connection hole can be improved, in the state that a connection area with lower layer wiring is ensured while irregularity of depth of a wiring trench and the connection hole is restrained. <P>SOLUTION: A first insulating film 15 is formed on the lower layer wiring W1, a stopper layer 16 of etching is formed on the first insulating film 15, a second insulating film 17 is formed on the stopper layer 16, the second insulating film 17, the stopper layer 16 and the first insulating film 15 are eliminated by etching, and a connection hole 15a is formed. The second insulating film 17 is eliminated by etching until the stopper layer 16 is exposed, and the wiring trench 17a is formed on the second insulating film 17. Etching is continued further, the stopper layer 16 in a linkage part of the wiring trench 17a and the connection hole 15a and the first insulating film 15 are ground, a diameter of an end portion of the connection hole 15a on a wiring trench 17a side is enlarged, and the wiring trench 17a and the connection hole 15a are filled with the conducting material. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a dual damascene process in which a wiring groove and a connection hole are filled with a conductive material to simultaneously form a wiring and a contact.

[0002]

2. Description of the Related Art With the progress of miniaturization of LSI, the influence of wiring resistance and wiring capacitance on the LSI performance is becoming a non-negligible value. In the wiring structure in which aluminum (Al) is used as the wiring material and silicon oxide (SiO ₂ ) is used as the interlayer insulating film, the proportion of the wiring delay in the whole is 0.18 μm.
It will increase rapidly after the mth generation.

A material having a lower dielectric constant than that of conventional silicon oxide is used as the insulating material in order to reduce the capacitance between wirings and the wiring resistance while suppressing the reduction of the space between adjacent wirings and the increase of the facing area between the wirings. An LSI using copper (Cu) as a wiring material instead of aluminum is under development. Since copper has a lower specific resistance and a higher melting point than aluminum, copper is expected to reduce wiring delay and greatly improve reliability.

To process a fine wiring pattern, a metal layer made of aluminum has been formed over the entire surface, a mask having etching resistance is covered therewith, and unnecessary metal regions are removed by etching to obtain a desired wiring structure. Had formed.

However, in the case of copper wiring, it is practically difficult to form a fine structure by dry etching. Therefore, a method of forming a wiring groove in the insulating film in advance by etching the insulating film and burying copper in the wiring groove is used. The so-called damascene method is used. In particular, the development of a dual damascene method, in which a connection hole for connecting upper and lower wirings and a wiring groove for an upper layer wiring are formed in advance and then copper is embedded in a lump, is the center of development.

However, in the dual damascene method,
As the wiring becomes finer, it becomes difficult to bury copper in the connection hole and the wiring groove without any gap, and as a result, there is a problem that voids are easily formed in the connection hole and poor conductivity easily occurs.

In order to solve the above problems, a dual damascene process is disclosed in, for example, Japanese Patent Laid-Open No. 10-229.
122 and JP-A 2000-299376.

In the technique disclosed in Japanese Patent Laid-Open No. 10-229122, the connection hole is formed halfway in the interlayer insulation film by half-etching the interlayer insulation film with the pattern of the connection hole, and then the interlayer insulation film is wired. By etching with a groove pattern, a wiring groove is formed and a connection hole is formed so as to reach the lower layer wiring. At the time of etching for forming the wiring groove at this time, the end portion of the connection hole on the wiring groove side, which is a corner portion, is also etched so that the opening diameter of the connection hole is directed toward the wiring groove. By embedding the wiring material into the wiring groove and the connection hole after that, the embedding property is improved.

In the technique described in Japanese Patent Laid-Open No. 2000-299376, two layers of a lower insulating film and an upper insulating film are formed,
First, an opening is formed in the upper insulating film with a pattern of connection holes,
Further, a connection hole having a tapered shape is formed in the lower insulating film by etching, and then a wiring groove is formed in the upper insulating film.

[0010]

However, according to the technique disclosed in Japanese Patent Laid-Open No. 10-229122, when the wiring groove is formed by etching, the etching depth varies within the substrate surface, which is later described. Variation in the wiring film thickness formed in the wiring groove will occur,
There is a problem that variations in wiring resistance and wiring capacitance increase.

Further, according to the technique disclosed in Japanese Patent Laid-Open No. 2000-299376, when forming the connection hole in the lower insulating film, the etching condition is such that the diameter is continuously narrowed from the upper end to the lower end. Since the etching is performed in step 1, if the area of the lower end of the connection hole is not secured, problems such as an increase in resistance will occur.
If the diameter of the upper end of the connection hole is made large enough, it is possible to secure the area of the lower end of the connection hole, but it may be difficult to secure the area of the lower end because of the restrictions of the design rule. .

The present invention has been made in view of the above circumstances, and it is an object of the present invention to suppress variations in the depths of wiring trenches and connection holes while ensuring a connection area with a lower layer wiring. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving the embeddability of a conductive material in a connection hole.

[0013]

[Means for Solving the Problems]
Therefore, the semiconductor device manufacturing method of the present invention is
1 step of forming an insulating film, and etching on the first insulating film
The step of forming a stopper layer for the
Forming a second insulating film on the second insulating film,
The stopper layer and the first insulating film are removed by etching.
To remove the contact hole and expose the stopper layer
Until the second insulating film is removed by etching
Forming a wiring groove in the second insulating film,
The wiring groove and the connection hole.
The stopper layer and the first insulating film in the connecting portion
To increase the diameter of the end of the connection hole on the wiring groove side.
Step and filling the wiring groove and the connection hole with a conductive material
And a step of embedding.

After the step of expanding the diameter of the end portion of the connection hole on the wiring groove side and before the step of filling the wiring groove and the connection hole with a conductive material, the stopper layer exposed in the wiring groove is removed. The method further includes the step of:

Prior to the step of forming the first insulating film, the method further comprises the step of forming a lower stopper layer serving as an etching stopper on the lower wiring, and in the step of forming the connection hole, the lower stopper is formed. After forming the connection hole exposing the layer and expanding the diameter of the end portion of the connection hole on the wiring groove side, before the step of filling the wiring groove and the connection hole with a conductive material, The method further includes the step of removing the exposed lower stopper layer and the exposed stopper layer in the wiring groove.

The step of filling the wiring groove and the connection hole with a conductive material includes the step of depositing a conductive material on the second insulating film so as to fill the wiring groove and the connection hole, and the wiring groove and the connection. And removing the conductive material deposited on the second insulating film by polishing while leaving the conductive material buried in the holes.

In the step of filling the wiring groove and the connection hole with a conductive material, a conductive material containing copper is embedded.

Before the step of depositing a conductive material on the second insulating film, a barrier film for covering the inner wall surfaces of the wiring groove and the connection hole to prevent copper from diffusing on the second insulating film. The step of depositing the conductive material, the conductive material containing copper is deposited on the barrier film so as to fill the wiring groove and the connection hole, and the conductive material is polished. In the removing step, the barrier film and the conductive material deposited on the second insulating film are removed by polishing while leaving the barrier film and the conductive material buried in the wiring groove and the connection hole.

In the method of manufacturing a semiconductor device according to the present invention, first, the second insulating film, the stopper layer and the first insulating film are removed by etching to form a connection hole, so that the area of the lower end is secured. The connection hole of is formed. Next, the second insulating film is removed by etching until the stopper layer is exposed, and a wiring groove is formed in the second insulating film. At this time, since the stopper layer serves as an etching stopper, the wiring groove is formed in a state where variations in the depth of the wiring groove to be formed are suppressed. Next, by further continuing the etching, the stopper layer and the first insulating film in the connection portion between the wiring groove and the connection hole are removed, and the diameter of the end portion of the connection hole on the wiring groove side is expanded. As a result, the diameter of the end portion of the connection hole on the wiring groove side is expanded in a state where the connection area with the lower layer wiring of the connection hole is secured. After that, the wiring groove and the connection hole are filled with a conductive material. At this time, since the diameter of the end portion of the connection hole on the wiring groove side is expanded, it is easy to embed the conductive material in the connection hole.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an example of a semiconductor device having a dual damascene structure manufactured by the method for manufacturing a semiconductor device according to this embodiment. A lower layer insulating film 11 made of, for example, silicon oxide is formed on a semiconductor substrate 10 on which MOS transistors and other semiconductor elements are formed, and an opening reaching the semiconductor substrate 10 is formed in the lower layer insulating film 11. , Ta, Ti, TaN, TiN that covers the inner wall surface of the opening to prevent copper diffusion
A barrier metal 12 made of, for example, is formed, and a conductive layer 13 made of, for example, copper is embedded inside the barrier metal 12 to form
The barrier metal 12 and the conductive layer 13 embedded in the first layer wiring W1 which is a lower layer wiring is formed. Although not shown, the first layer wiring W1 is connected to a semiconductor element or the like formed on the semiconductor substrate 10 via a first layer contact.

A diffusion prevention film 14 for preventing the diffusion of copper such as silicon nitride is formed on the lower insulating film 11 and the first layer wiring W1, and on the diffusion prevention film 14,
A first insulating film 15 made of, for example, silicon oxide is formed.

An etching stopper film 16 made of, for example, silicon nitride or the like and serving as an etching stopper is formed on the first insulating film 15, and a second insulating film 17 made of, for example, silicon oxide or the like is formed on the etching stopper film 16. Are formed.

A wiring groove 17a is formed in the second insulating film 17 and the etching stopper film 16, and further penetrates the first insulating film 15 and the diffusion prevention film 14 to form the upper surface of the first layer wiring W1. A connection hole 15a exposing the wiring is formed so as to communicate with the wiring groove 17a.

In the present embodiment, the diameter of the connection hole 15a formed in the first insulating film 15 has a shape that widens at the end portion on the wiring groove 17a side, and a conductive material is embedded in the connection hole 15a. It is easy to be damaged.

A connecting hole 15a and a wiring groove 17a which communicate with each other.
Coating the inner wall surface of, for example, T to prevent the diffusion of copper
Barrier metal 18 made of a, Ti, TaN, TiN, etc.
Is formed, and a conductive layer 19 made of, for example, copper is embedded therein. The barrier metal 18 and the conductive layer 19 embedded in the wiring groove 17a form a second layer wiring W2, and the barrier metal 18 and the conductive layer 19 embedded in the connection hole 15a form a second layer contact C2. There is. In the above structure, the second layer wiring W2 is connected to the first layer wiring W1 which is the lower layer wiring via the second layer contact C2.

Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS.

First, the steps up to FIG. 2A will be described. On a semiconductor substrate 10 in which MOS transistors and other semiconductor elements are formed and contacts (not shown) are embedded in an insulating film, for example, CVD (Ch
The lower insulating film 11 is formed by depositing silicon oxide by the emical vapor deposition method or the like. Subsequently, an opening for burying the wiring is formed in the lower insulating film 11, a material such as Ta, Ti, TaN, or TiN is formed in the opening to form the barrier metal 12, and further, it is made of copper. The conductive layer 13 is deposited, and the excess barrier metal 12 and the conductive layer 13 on the lower insulating film 11 are subjected to CMP (Chemical Mecha
As shown in FIG. 2A, the first layer wiring W1 made of the conductive layer 13 and the barrier metal 12 embedded in the lower insulating film 11 is formed by removing and planarizing by the nical polishing method.

Next, as shown in FIG. 2B, a diffusion prevention film 14 for preventing the diffusion of copper by depositing silicon nitride on the lower insulating film 11 and the first layer wiring W1 by, for example, the CVD method. Then, silicon oxide is deposited on the diffusion prevention film 14 by, for example, the CVD method to form the first insulating film 15. At this time, the total thickness of the first insulating film 15 and the diffusion prevention film 14 is formed so as to be the height of the contact to be formed later.

Next, as shown in FIG. 3C, an etching stopper film 16 is formed on the first insulating film 15 by depositing silicon nitride by, for example, a CVD method, and further, an etching stopper film 16 is formed thereon. Then, a silicon oxide film is deposited to form a second insulating film 17. At this time, the second insulating film 1
7 and the etching stopper film 16 are formed so as to have a total film thickness of a wiring to be formed later.

Next, as shown in FIG. 3D, a resist is coated on the second insulating film 17 and a resist mask R1 is formed on the second insulating film 17 by a photolithography technique to form a pattern of connection holes. Is patterned.

Next, as shown in FIG. 4E, etching such as RIE is performed using the resist mask R1 as an etching mask to remove the second insulating film 17, the etching stopper film 16 and the first insulating film 15 in order. By doing so, the connection hole 15b is formed in the first insulating film 15. In addition,
At this time, the second insulating film 17 made of silicon oxide is etched and the etching stopper film 1 made of silicon nitride is formed.
6, the first insulating film 15 made of silicon oxide
The etching conditions are changed.

Next, as shown in FIG. 4F, the resist mask R1 having an opening in the pattern of the connection holes is removed.

Next, as shown in FIG. 5G, a resist is again coated on the second insulating film 17 and a resist is formed on the second insulating film 17 in the pattern of the wiring groove by the photolithography technique. The mask R2 is formed by patterning.

Next, as shown in FIG. 5H, the diffusion preventive film 14 is formed by using the resist mask R2 as an etching mask.
The second insulating film 17 made of silicon oxide can be selectively removed from the silicon nitride film of the etching stopper film 16 and the second insulating film 17 made of silicon oxide by etching.
By etching the insulating film 17, the second insulating film 1
A wiring groove 17a is formed in the wiring 7.

Next, as shown in FIG. 6 (i), the above etching is further continued, that is, etching is performed to a thickness of the second insulating film 17 or more, so that the contact hole 15b on the wiring groove 17a side is formed. The etching stopper film 16 at the end portion, which was the corner portion A in the step shown in FIG. 5H, was scraped by the physical sputtering action of the etching, and the exposed corner portion A was oxidized. By etching the first insulating film 15 made of silicon, the connection hole 15a having a wider diameter at the end portion on the wiring groove 17a side is formed. In the process, the diameter of the connection hole 15b and the width of the wiring groove 17a are substantially the same as shown on the right side of FIG.
In the flat portion B where there is no corner portion (step portion) due to the difference in diameter in the connecting portion from the connection hole 15b to the connection hole 15b, the sputtering action as in the above corner portion A does not occur. The end portion on the groove 17a side does not expand beyond the width of the wiring groove 17a.

Next, as shown in FIG. 6J, the resist mask R2 having an opening in the wiring groove pattern is removed.

Next, as shown in FIG. 7K, the wiring groove 1
The etching stopper film 16 made of silicon nitride exposed at 7a and the diffusion prevention film 14 made of silicon nitride exposed at the connection hole 15a are removed by etching to connect to the bottom of the wiring groove 17a and expose the first layer wiring W1. Connection hole 15a.

Next, as shown in FIG. 7 (l), the connection hole 1
5a and the inner wall surface of the wiring groove 17a are covered, for example, Ta, Ti, TaN, TiN for preventing diffusion of copper.
The barrier metal 18 is formed by depositing such materials as a sputtering method.

Next, as shown in FIG. 8 (m), for example, copper is formed on the barrier metal 18 by sputtering, CVD, or plating until the insides of the connection hole 15a and the wiring groove 17a are filled. A conductive layer 19 is deposited. When the conductive layer 19 is deposited by electrolytic plating, the conductive layer 19 is formed by the sputtering method.
This is performed after forming a seed film (not shown) with the same material as the above.

In the subsequent steps, the excess conductive layer 19 and the barrier metal 18 on the second insulating film 17 are removed by the CMP method and planarized, and the connection hole 15a and the wiring groove 1 are formed.
By leaving the conductive layer 19 and the barrier metal 18 only in the inside 7a, the barrier metal 1 embedded in the wiring groove 17a is formed.
8 and the conductive layer 19 form the second layer wiring W2,
The barrier metal 18 and the conductive layer 19 embedded in the connection hole 15a form a second layer contact C2.

When forming the third and subsequent wiring layers, the multilayer wiring is formed by repeating the steps of FIGS. 2 (b) to 8 (m). As described above, the semiconductor device having the dual damascene structure shown in FIG. 1 is manufactured.

According to the method of manufacturing a semiconductor device of the present embodiment described above, in the step shown in FIG. 4E, etching such as RIE is performed using the resist mask R1 opened in the pattern of the connection hole as an etching mask. After forming the connection hole 15b in the state where the bottom surface area is secured in the first insulating film 15, when forming the wiring groove 17a shown in FIG. By performing the above step, at the end of the connection hole 15b on the wiring groove 17a side,
The etching stopper film 16 that has become the corner portion A is scraped by the physical sputtering action during etching, and the exposed first insulating film 15 is etched,
Since it is possible to form the connection hole 15a in which only the diameter of the end portion on the wiring groove 17a side is widened as shown in FIG. 6I, it is possible to widen only the upper shape of the connection hole 15a while securing the bottom area of the connection hole 15a. be able to. Therefore, the filling property of the conductive layer 19 deposited thereafter can be improved, and the formation of voids in the connection hole can be prevented.

FIG. 9 shows an example of a top view after the wiring groove 17a and the connection hole 15a are processed in the step shown in FIG. 6 (i). The processed connection hole 15a has a lower end 15a.
-1, the diameter of the upper end 15a-2 is equal to that of the wiring groove 17
The shape is expanded in a. Here, as described above, the wiring groove 17a as illustrated on the right side of FIG.
In the connection hole 15a and the diameter of the connection hole 15a and the width of the wiring groove 17a are substantially the same, the wiring groove 1
Since the connecting portion from 7a to the connecting hole 15a is a flat portion and the shape of the connecting hole 15a does not change due to the sputtering action at the time of etching, the wiring groove 1 of the connecting hole 15a is formed.
The end on the 7a side does not expand beyond the width of the wiring groove 17a. Therefore, the upper end 15a-2 of the connection hole 15a is
There is no problem that the diameter of the wiring becomes wider than necessary and short-circuits with the adjacent wiring. Even in this case, the upper end 1 of the connection hole 15a is extended in the extending direction of the wiring groove 17a.
Since the diameter of 5a-2 is expanded, the embeddability of the conductive layer 19 in the connection hole 15a is improved.

Further, in the present embodiment, since the etching stopper film 16 is provided between the second insulating film 17 and the first insulating film 15, the second insulating film 17 is prevented from being etched more than necessary. Since it is possible to suppress the variation in the depth of the wiring groove 17a in the surface of the substrate, the barrier metal 18 and the conductive layer 19 can be formed later.
The uniformity of the film thickness of the wiring formed by embedding can be improved.

As described above, according to the method of manufacturing the semiconductor device of the present embodiment, the variation in the depth of the wiring groove 17a and the connection hole 15a is suppressed and the connection area with the lower layer wiring W1 is secured. Conductive layer 1 to connection hole 15a
The embedding property of No. 9 can be improved. Therefore, even when the wiring width is further miniaturized, the generation of voids in the connection hole can be suppressed.

The method of manufacturing the semiconductor device of the present invention is not limited to the above description of the embodiment. For example, in the present embodiment, an example in which silicon oxide is used for the first insulating film 15 and the second insulating film 17 has been described, but the present invention is not limited to this, and xerogel having a dielectric constant of 3.0 or less may be used. A low dielectric constant material can also be used.

In the present embodiment, the barrier metal 1
Although an example of the materials 2 and 18 has been described, the material is not limited to this, and various materials having a function as a barrier metal can be used, and the conductive layers 13 and 19 can be used.
It is also possible to use a material other than copper.

Further, in this embodiment, the diffusion prevention film 14 made of an insulating film for preventing the diffusion of copper is inserted between the wiring layers, and the diffusion prevention film 14 is also used as a stopper layer for etching when the connection hole 15a is formed. Although the dual-purpose example has been described, only the exposed surface of copper may be selectively electroless-plated with a material such as CoWP to form a barrier metal that prevents diffusion of copper. Besides, various modifications can be made without departing from the scope of the present invention.

[0050]

According to the present invention, the burying property of the conductive material in the connection hole is improved while suppressing the variation in the depths of the wiring groove and the connection hole and ensuring the connection area with the lower layer wiring. Can be made.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a dual damascene structure manufactured by a method of manufacturing a semiconductor device according to this embodiment.

FIG. 2 is a plan view of a semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing after formation of the 1st insulating film.

FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after formation of a resist mask that opens in a pattern of connection holes on the second insulating film.

FIG. 4 is a plan view of the semiconductor device manufacturing method according to the present embodiment.
FIG. 6 is a cross-sectional view after forming a connection hole in the first insulating film.

FIG. 5 is a view showing manufacturing of the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after forming a wiring groove in a second insulating film.

FIG. 6 is a view showing manufacturing of the semiconductor device according to the present embodiment.
It is sectional drawing after expanding the diameter of the upper end of a connection hole.

FIG. 7 is a view showing manufacturing of the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after a barrier metal is deposited on a wiring groove and a connection hole.

FIG. 8 is a view showing a method of manufacturing the semiconductor device according to the present embodiment.
FIG. 6 is a cross-sectional view after a conductive layer is deposited on the wiring groove and the connection hole.

FIG. 9 is a view illustrating manufacturing of the semiconductor device according to the present embodiment.
It is a top view after forming a wiring groove and a connection hole.

[Explanation of symbols]

10 ... Semiconductor substrate, 11 ... Lower insulating film, 12 ... Barrier metal, 13 ... Conductive layer, 14 ... Diffusion preventive film, 15 ... First insulating film, 15a, 15b ... Connection hole, 15a-1 ... Lower end of connection hole, 15a-2 ... Upper end of connection hole, 16 ... Etching stopper film, 17 ... Second insulating film, 17a ... Wiring groove, 18 ...
Barrier metal, 19 ... Conductive layer, W1 ... First layer wiring, W2
... second layer wiring, C2 ... second layer contacts, R1, R2 ...
Resist mask, A ... corner, B ... flat part.

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Claims (6)

[Claims] 1. A step of forming a first insulating film on a lower wiring, a step of forming an etching stopper layer on the first insulating film, and a step of forming a second insulating film on the stopper layer. A step of etching the second insulating film, the stopper layer and the first insulating film to form a connection hole; and etching the second insulating film until the stopper layer is exposed, The step of forming a wiring groove in the second insulating film and the etching are further continued, and the stopper layer and the first insulating film in the connecting portion between the wiring groove and the connection hole are removed to remove the wiring groove side portion. A method of manufacturing a semiconductor device, comprising: expanding the diameter of the end portion of the connection hole; and burying the wiring groove and the connection hole with a conductive material. 2. The stopper layer exposed in the wiring groove after the step of expanding the diameter of the end portion of the connection hole on the wiring groove side and before the step of filling the wiring groove and the connection hole with a conductive material. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the. 3. Before the step of forming the first insulating film, the method further comprises the step of forming a lower stopper layer serving as an etching stopper on the lower wiring, and in the step of forming the connection hole, After forming the connection hole exposing the lower stopper layer and expanding the diameter of the end portion of the connection hole on the wiring groove side, and before the step of filling the wiring groove and the connection hole with a conductive material, the connection The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing the lower stopper layer exposed in the hole and the stopper layer exposed in the wiring groove. 4. The step of filling the wiring groove and the connection hole with a conductive material comprises the step of filling the second wiring groove and the connection hole with each other.
A step of depositing a conductive material on the insulating film, and a step of removing the conductive material deposited on the second insulating film by polishing while leaving the conductive material buried in the wiring groove and the connection hole. The method for manufacturing a semiconductor device according to claim 1, further comprising. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of filling the wiring groove and the connection hole with a conductive material, a conductive material containing copper is embedded. 6. Before the step of depositing a conductive material on the second insulating film, the inner wall surfaces of the wiring groove and the connection hole are covered to prevent copper from diffusing on the second insulating film. The method further comprises the step of forming a barrier film, wherein in the step of depositing the conductive material, the conductive material containing copper is deposited on the barrier film so as to fill the wiring groove and the connection hole, In the step of removing by polishing, the barrier film and the conductive material deposited on the second insulating film are removed by polishing while leaving the barrier film and the conductive material buried in the wiring groove and the connection hole. The method for manufacturing a semiconductor device according to claim 5.