JP2004356315A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve electromigration (EM) resistance and to prevent diffusion of a wiring material due to alignment deviation without increasing capacity between wirings. <P>SOLUTION: A lower layer wiring 16 is formed in the first groove 14a of a first interlayer insulating film 14. An upper face of the lower layer wiring 16 is arranged between the upper face and the lower face of a first barrier insulating film 13. A second barrier metal film 17 is formed in a region except for a region where a connection hole 22b on the upper face of the lower layer wiring 16 is formed. An upper layer wiring 24 and a wiring connection part 24a are formed in a second groove 22a and a connection hole 22b in a second interlayer insulating film 22. The first barrier insulating film 13 is arranged between the wiring connection part 24a and a first insulating film 12 even if alignment deviation occurs. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a plurality of wiring layers and a method of manufacturing the same, and in particular, a lower wiring and an upper wiring, and a wiring connection portion connecting the lower wiring and the upper wiring are embedded in an interlayer insulating film. The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
Due to demands for miniaturization and high-speed operation of semiconductor integrated circuits, there is a demand for lowering the resistivity and improving the reliability of wiring used in semiconductor integrated circuits and the like. In particular, aluminum has conventionally been used as a material forming the wiring, but in recent years, copper has been used as a wiring material having lower resistance and higher reliability than aluminum.
[0003]
Here, when copper is used as the wiring material, since copper atoms have a property of easily diffusing into silicon oxide forming the interlayer insulating film, for example, tantalum nitride (TaN) is formed on the bottom and side surfaces of the wiring groove and the connection hole. For example, it is necessary to prevent a wiring material from diffusing into an interlayer insulating film by forming a barrier metal film made of a material having a barrier property against copper atoms.
[0004]
(First conventional example)
FIG. 10 is a sectional view showing a first conventional semiconductor device formed by the damascene method. As shown in FIG. 10, the semiconductor device of the first conventional example has a semiconductor substrate 101 on which a semiconductor integrated circuit is provided, on which a first trench 102a is provided as a first interlayer insulating film. One silicon oxide film 102 is formed, and a lower wiring 104 made of copper is formed inside the first trench 102a via a first barrier metal film 103 made of tantalum nitride covering the side and bottom surfaces. Have been.
[0005]
Further, on the first silicon oxide film 102 including the lower wiring 104, a first silicon nitride film 105, a second silicon oxide film 106, a second silicon nitride film 107, and a third silicon oxide film 107 are formed. A second interlayer insulating film 109 is formed as a laminated film in which the films 108 are sequentially laminated. The second interlayer insulating film 109 is provided with a second groove 109 a for the upper wiring, and a connection hole 109 b extending from the bottom surface of the second groove 109 a to the upper surface of the lower wiring 104. Copper, which is a wiring material, is buried inside the second groove 109a and the connection hole 109b via a second barrier metal film 110 made of tantalum nitride covering the respective side surfaces and bottom surfaces, thereby forming an upper layer wiring. 111 and a wiring connection portion 111a for connecting the upper wiring 111 and the lower wiring 104 are formed.
[0006]
Here, tantalum nitride forming the first barrier metal film 103 and the second barrier metal film 110 is a conductive material having a barrier property against copper atoms (a property of preventing diffusion of copper atoms). The first and second silicon oxide films 102, 106 and the third silicon oxide film 108 form the copper constituting the lower wiring 104 and the upper wiring 111 by the barrier metal film 103 and the second barrier metal film 110. Is prevented from diffusing into
[0007]
Further, since silicon nitride is an insulating material having a barrier property against copper atoms, the first silicon nitride film 105 is provided between the lower wiring 104 and the second silicon oxide film 106, Copper atoms forming the wiring 104 can be prevented from diffusing into the second silicon oxide film 106.
[0008]
In the semiconductor device of the first conventional example, the second trench 109a and the connection hole 109b are patterned on the second interlayer insulating film 109 by using a photolithography method and a dry etching method. An opening region for forming the connection hole portion 109b is positioned so as to be included in a formation region of the lower wiring 104.
[0009]
Meanwhile, when a high-density current flows between the lower wiring 104 and the upper wiring 111, a phenomenon called electro-migration (EM) in which copper atoms as a wiring material move by an electron flow occurs.
[0010]
In the semiconductor device of the first conventional example, since the second barrier metal film 110 is disposed between the lower wiring 104 and the wiring connection portion 111a, the movement of the copper atoms by the EM prevents the second barrier metal film. Since a void grows between the lower wiring 104 and the wiring connection portion 111a because of being hindered by the wiring 110, it causes a failure such as disconnection.
[0011]
As described above, the semiconductor device of the first conventional example has a problem that voids are easily generated by electromigration (that is, EM resistance is low).
[0012]
In order to solve such a problem, a semiconductor device in which a lower wiring and an upper wiring are formed continuously by removing the bottom surface of the connection hole 109b in the second barrier metal film 110 (see, for example, Patent Document 1) A semiconductor device in which the bottom surface of the connection hole 109b in the second barrier metal film 110 is thinned to such an extent that copper atoms can move (for example, see Patent Document 2).
[0013]
(Second conventional example)
Hereinafter, a semiconductor device described in Patent Document 1 will be described as a second conventional example with reference to the drawings.
[0014]
FIG. 11A shows a cross-sectional configuration of a semiconductor device of a second conventional example. As shown in FIG. 11A, in the semiconductor device of the second conventional example, a portion of the second barrier metal film 110 between the lower wiring 104 and the wiring connection portion 111a and a portion of the second silicon nitride film 107 are formed. The upper part has been removed. In such a configuration, after the second barrier metal film 110 is formed over the entire surface including the second trench 109 a and the connection hole 109 b on the second interlayer insulating film 109, the second barrier metal This is realized by performing anisotropic etching on the film 110 and removing portions of the second barrier metal film 110 formed on the bottom surfaces of the second trench 109a and the connection hole 109b.
[0015]
According to the configuration of the second conventional example, since a barrier metal film is not formed between the lower wiring 104 and the wiring connection portion 111a, even if a high-density current is generated between the lower wiring 104 and the upper wiring 111. In addition, the generation of voids is suppressed because the transfer of copper atoms by EM is not hindered. Therefore, the semiconductor device of the second conventional example has improved EM resistance.
[0016]
However, in the semiconductor device of the second conventional example, there is a problem that copper atoms are diffused when a misalignment occurs in the photolithography process. Hereinafter, a case where the misalignment occurs in the semiconductor device of the second conventional example will be specifically described.
[0017]
FIG. 11B is a cross-sectional configuration diagram in a case where an alignment shift occurs between photomasks in a photolithography process for patterning the connection hole 109b. As shown in FIG. 11B, when a portion of the connection hole portion 109b protrudes from the lower wiring 104 due to misalignment, a portion of the wiring connection portion 111a is disposed in contact with the first silicon oxide film 102. Is done.
[0018]
Accordingly, since a material having a barrier property against copper atoms is not arranged between the wiring connection portion 111a and the first silicon oxide film 102, the copper atoms of the wiring material diffuse into the first silicon oxide film 102. This may cause poor connection or disconnection.
[0019]
As described above, in the semiconductor device of the second conventional example, the EM resistance is ensured by allowing the copper atoms of the wiring material to move between the wiring connection portion 111a and the lower wiring 104. Since there is no second barrier metal film 110 on the bottom surface, copper atoms diffuse into the first silicon oxide film 102 when the misalignment occurs, thereby deteriorating the reliability of the semiconductor device.
[0020]
To cope with such a problem, after forming an insulating film having a barrier property against a wiring material on the first silicon oxide film 102, the second trench 109a and the connection hole 109b for the upper wiring 111 are formed. 2. Description of the Related Art A semiconductor device configured to be patterned is known (for example, see Patent Document 3).
[0021]
(Third conventional example)
Hereinafter, a semiconductor device described in Patent Document 3 will be described as a third conventional example with reference to the drawings.
[0022]
FIG. 12A shows a cross-sectional configuration of a semiconductor memory device of a third conventional example. As shown in FIG. 12A, in the semiconductor device of the third conventional example, the first silicon oxide film 102 is formed on the first silicon oxide film 102 as a barrier insulating film made of an insulating material having a barrier property against copper atoms. Of the first silicon oxide film 102 and the first silicon nitride film 112 are used as the first interlayer insulating film 113, and the silicon nitride film 112 is provided on the first interlayer insulating film 113. The lower layer wiring 104 is provided in the first groove 113a. Further, as second interlayer insulating film 109A, SiC film 114 made of silicon carbide (SiC), second silicon oxide film 106, second silicon nitride film 107, third silicon oxide film 108, and second silicon A laminated film in which the nitride films 115 are sequentially laminated is formed.
[0023]
Here, when the first silicon nitride film 112 constituting the uppermost layer of the first interlayer insulating film 113 is misaligned when forming the connection hole 109b, the first silicon nitride film 112 is made of the wiring material of the wiring connection portion 111a. This prevents certain copper atoms from diffusing into the first silicon oxide film 102.
[0024]
Further, the SiC film 114 constituting the lowermost layer of the second interlayer insulating film 109A prevents copper atoms, which are the wiring material of the lower wiring 104, from diffusing into the second silicon oxide film 106, and also has a connection hole. If an alignment shift occurs when the portion 109b is formed, selective etching with the first silicon nitride film 112 can be performed. Hereinafter, a specific description will be given of a case where misalignment occurs in the semiconductor device manufacturing method of the third conventional example.
[0025]
FIG. 12B is a cross-sectional configuration diagram showing a case where an alignment shift occurs in a photolithography process for patterning the connection hole 109b in the method of manufacturing the semiconductor device of the third conventional example. As shown in FIG. 12B, even when a part of the connection hole portion 109b protrudes from the lower layer wiring 104 and is arranged on the first interlayer insulating film 113 due to misalignment, the wiring connection portion 111a is Since the first silicon nitride film 112 is arranged between the first silicon oxide film 102 and the first silicon nitride film 112, copper forming the wiring connection portion 111 a is not diffused into the first silicon oxide film 102.
[0026]
[Patent Document 1]
JP 2001-284449 A
[Patent Document 2]
JP-A-2002-176099
[Patent Document 3]
JP-A-2002-064140
[0027]
[Problems to be solved by the invention]
However, according to the third conventional example, as the insulating film for preventing the diffusion of the wiring material, the lowermost layer of the second interlayer insulating film 109A for preventing the diffusion from the lower wiring 104 to the second silicon oxide film 106. The first silicon nitride film 112 provided on the uppermost layer of the first interlayer insulating film 113 in order to prevent diffusion from the wiring connection portion 111a to the first silicon oxide film 102. is necessary. Here, since silicon nitride and silicon carbide have a higher dielectric constant than silicon oxide, the first silicon nitride film 112 and the SiC film 114 each have a sufficient thickness to prevent diffusion of copper atoms. Then, the capacitance between the second conventional example and the wiring increases.
[0028]
As described above, the semiconductor device of the third conventional example can improve the EM resistance by allowing the wiring material to move between the lower layer wiring and the wiring connection portion. If the diffusion of the wiring material from above can be prevented, the thickness of the insulating film for preventing the diffusion becomes large, so that there is a problem that the capacitance between the wirings increases.
[0029]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to improve the EM resistance and prevent the diffusion of wiring material due to misalignment without increasing the capacitance between wirings.
[0030]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a diffusion preventing insulating layer on the uppermost layer of an interlayer insulating film, a diffusion preventing film on an upper surface of a lower wiring, and an upper surface of the lower wiring having a diffusion preventing insulating layer. It is configured to be provided between the upper surface and the lower surface.
[0031]
Specifically, a semiconductor device according to the present invention is formed over a semiconductor region and includes a lower wiring formed of a first wiring material and a lower wiring formed on the semiconductor region and insulating between the semiconductor region and the lower wiring. A first interlayer insulating film, an upper layer wiring formed of a second wiring material, formed above the lower wiring, and a wiring formed of the second wiring material and connecting an upper surface of the lower wiring and a lower surface of the upper wiring; Except for a connection portion, a second interlayer insulating film formed on the first interlayer insulating film and insulating between the lower wiring and the upper wiring, and a portion on the upper surface of the lower wiring where the wiring connecting portion is formed A first diffusion preventing film formed in the region and preventing diffusion of the first wiring material, wherein the first interlayer insulating film is formed on the first insulating layer and the first insulating layer. And first diffusion preventing insulation for preventing diffusion of the first wiring material and the second wiring material. Consists of a upper surface of the lower layer wiring is provided so as to be positioned between the upper and lower surfaces of the first diffusion preventing insulating layer.
[0032]
According to the semiconductor device of the present invention, since the first diffusion prevention film is formed in a region other than the region where the wiring connection portion is formed on the lower wiring, the lower wiring and the second interlayer insulating film are formed. Since the wiring material forming the lower layer wiring is not diffused into the second interlayer insulating film during the period, an insulating film for preventing diffusion is provided in the lowermost layer of the second interlayer insulating film as in the third conventional example. There is no need to increase the capacitance between wirings. Further, since the first diffusion prevention film does not exist between the lower wiring and the wiring connection portion, the wiring material can move, so that the EM resistance is improved. Further, since the upper surface of the lower wiring is disposed between the upper surface and the lower surface of the first diffusion prevention insulating layer, a part of the wiring connection portion is formed on the first interlayer insulating film due to misalignment. Even in this case, it is possible to prevent the wiring material forming the wiring connection portion from diffusing into the first insulating layer.
[0033]
In the semiconductor device of the present invention, the first diffusion barrier film is preferably made of a conductive material.
[0034]
In this case, the capacitance between the lower wiring and the upper wiring can be further reduced.
[0035]
In the semiconductor device of the present invention, it is preferable that the first wiring material and the second wiring material are copper or an alloy containing copper.
[0036]
In this case, the lower wiring, the upper wiring, and the wiring connection portion can be formed with low resistance and high reliability.
[0037]
In the semiconductor device of the present invention, the material constituting the first diffusion barrier film is preferably any one of tantalum, tantalum nitride, tungsten nitride, and tantalum nitride silicide.
[0038]
In this case, the diffusion of copper atoms as a wiring material can be reliably prevented by the first diffusion prevention film.
[0039]
In the semiconductor device of the present invention, the material forming the first diffusion prevention insulating layer is preferably silicon nitride or silicon carbide.
[0040]
In this case, the diffusion of copper atoms, which is a wiring material, can be reliably prevented by the first diffusion prevention insulating layer.
[0041]
The semiconductor device of the present invention further includes a second diffusion prevention film covering the upper wiring and preventing the diffusion of the second wiring material, wherein the second interlayer insulating film includes a second insulating layer; A second diffusion preventing insulating layer formed on the second insulating layer and preventing diffusion of the second wiring material, wherein an upper surface of the upper wiring is positioned on the upper surface of the second diffusion preventing insulating layer; It is preferable to be provided so as to be located between the lower surface position.
[0042]
In this way, even when another wiring is formed on the upper wiring, it is possible to improve the EM resistance and prevent the diffusion of the wiring material due to the misalignment without increasing the capacitance between the wirings. it can.
[0043]
A method of manufacturing a semiconductor device according to the present invention includes the steps of sequentially laminating a first insulating layer and a first diffusion prevention insulating layer on a semiconductor region to form a first interlayer insulating film; Forming a groove in the film, forming a lower wiring inside the groove such that the upper surface is located between the upper surface and the lower surface of the first diffusion preventing insulating layer, and forming a lower wiring on the lower wiring. Forming a second interlayer insulating film on the entire surface including the first diffusion preventing film on the first diffusion preventing film; and forming a second interlayer insulating film on the entire surface including the first diffusion preventing film. Forming an opening through the second interlayer insulating film in the insulating film to expose the first diffusion barrier film; and removing the first diffusion barrier film exposed in the opening to remove the first diffusion barrier film. Exposing a lower wiring on a bottom surface, and forming a wiring connection portion and an upper wiring inside the opening. There.
[0044]
According to the method for manufacturing a semiconductor device of the present invention, the method includes the step of forming the lower wiring such that the upper surface is located between the upper surface and the lower surface of the first diffusion prevention insulating layer. Even if a part of the opening is disposed above the first interlayer insulating film due to misalignment when the opening is formed in the insulating film, the lower wiring is exposed in the step of exposing the lower wiring in the opening. Since the etching is stopped when the upper surface of the opening is exposed, the first insulating layer is not exposed on the bottom surface of the opening. Therefore, the second wiring material is removed from the wiring connecting portion by the first diffusion preventing insulating layer. Can be prevented from diffusing into the interlayer insulating film. The method further includes a step of forming a first diffusion barrier film on the lower wiring, and a step of removing the first diffusion barrier film exposed at the opening to expose the lower wiring at the bottom surface of the opening. Therefore, it is possible to prevent the first wiring material from diffusing from the lower wiring into the second interlayer insulating film without forming an insulating layer for preventing diffusion in the lowermost layer of the second interlayer insulating film, and also to prevent the wiring from being formed. Since the material can move between the lower wiring and the wiring connection portion, EM resistance is improved. Therefore, it is possible to improve the EM resistance and prevent the diffusion of the wiring material due to the misalignment without increasing the capacitance between the wirings.
[0045]
In the method of manufacturing a semiconductor device according to the present invention, in the step of exposing the lower wiring, an etching agent capable of etching the material forming the first diffusion prevention film and the material forming the first diffusion prevention insulating layer is used. Preferably, the first diffusion barrier film exposed at the opening is removed.
[0046]
In the method of manufacturing a semiconductor device according to the present invention, in the step of exposing the lower wiring, the etching rate for the material forming the first diffusion prevention film is higher than the etching rate for the material forming the first diffusion prevention insulating layer. It is preferable to etch away the first anti-diffusion film exposed in the opening using an etching agent having a large value.
[0047]
In this case, since the first diffusion prevention insulating layer is hardly etched in the step of exposing the lower wiring, even if the thickness of the first diffusion prevention insulating layer is reduced, the diffusion of the wiring material at the bottom of the opening is prevented. Since a sufficient thickness can be ensured for prevention, the capacitance between wirings can be reduced.
[0048]
In the method of manufacturing a semiconductor device according to the present invention, the step of forming the lower wiring includes forming a lower wiring forming film over the entire surface including the groove on the first interlayer insulating film; Forming a lower wiring from the lower wiring forming film by polishing and removing the upper surface to such an extent that the upper surface is located between the upper surface and the lower surface of the first diffusion prevention insulating layer.
[0049]
With this configuration, by appropriately setting the polishing conditions of the lower wiring forming film, the position of the upper surface of the lower wiring can be adjusted to be located between the upper surface and the lower surface of the first diffusion prevention insulating layer. It can be formed reliably at low cost.
[0050]
In the method for manufacturing a semiconductor device according to the present invention, the step of forming the first diffusion prevention film includes the step of forming the first diffusion prevention film made of a conductive material on the entire surface including the lower wiring on the first diffusion prevention insulating layer. Forming the first diffusion barrier film, removing the upper portion of the first diffusion barrier film so that the upper surface of the first diffusion barrier insulating layer is exposed, and removing the first diffusion barrier film from the first diffusion barrier film. And forming a first diffusion prevention film.
[0051]
By doing so, the first diffusion prevention film can be formed in a self-aligned manner with respect to the groove of the first interlayer insulating film, so that the first diffusion prevention film can be reliably formed at low cost. Can be.
[0052]
The method of manufacturing a semiconductor device according to the present invention further includes, after the step of forming the upper layer wiring, a step of forming a second anti-diffusion film on the upper layer wiring, wherein the step of forming the second interlayer insulating film includes: Forming a second insulating layer and a second diffusion preventing insulating layer sequentially on the first interlayer insulating film. The step of forming the upper wiring includes opening the second interlayer insulating film on the second interlayer insulating film. Forming the upper wiring formation film over the entire surface including the inside of the portion, and polishing and removing the upper wiring formation film to such an extent that the upper surface is located between the upper surface and the lower surface of the second diffusion prevention insulating layer. Forming an upper wiring from the upper wiring forming film.
[0053]
In this way, even when another wiring is formed on the upper wiring, it is possible to improve the EM resistance and prevent the diffusion of the wiring material due to the misalignment without increasing the capacitance between the wirings. it can.
[0054]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
[0055]
FIG. 1A shows a cross-sectional configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1A, the semiconductor device according to the first embodiment includes, for example, a first insulating film 12 made of silicon oxide having a thickness of about 250 nm on a semiconductor substrate 11 made of silicon. And a first barrier insulating film (first diffusion prevention insulating layer) 13 made of silicon nitride having a thickness of about 70 nm. Here, the first insulating film 12 and the first barrier insulating film 13 constitute a first interlayer insulating film 14, and a wiring groove for forming a lower wiring is formed on the first interlayer insulating film 14. A first groove (groove) 14a having a depth of about 250 nm from the upper surface of the first barrier insulating film 13 and a width of about 240 nm is provided.
[0056]
A first barrier metal film 15 made of tantalum nitride having a thickness of about 20 nm is provided on the wall surface and the bottom surface of the first groove portion 14a, and copper, which is a wiring material, is provided inside the first groove portion 14a. Is embedded to form the lower wiring 16.
[0057]
Although not shown, a semiconductor integrated circuit including a transistor and the like and a protective film covering the surface of the semiconductor integrated circuit are provided on the upper surface of the semiconductor substrate 11, and the upper surface of the protective film is provided on the upper surface of the protective film. A tungsten plug serving as an electrode of a transistor or the like is provided. The lower wiring 16 is connected to the semiconductor integrated circuit on the semiconductor substrate 11 via the tungsten plug. Further, the first interlayer insulating film 14 insulates between the lower wiring 16 and the semiconductor integrated circuit.
[0058]
The upper surface of the lower wiring 16 is disposed at a position where the depth from the upper surface of the first barrier insulating film 13 in the first groove portion 14a is about 10 nm to 20 nm. In a region other than a region where a later-described wiring connection portion is formed on the lower wiring 16 in the first groove portion 14 a, a second portion is formed so as to fill a portion below the upper surface of the first barrier insulating film 13. A barrier metal film (first diffusion prevention film) 17 is provided. Here, the thickness of the second barrier metal film 17 is approximately 10 nm to 20 nm, which is substantially equal to the depth from the upper surface of the first barrier insulating film 13 to the upper surface of the lower wiring 16, so that the barrier property against copper atoms is Is secured.
[0059]
On the first interlayer insulating film 14 including the second barrier metal film 17, a second insulating film 18 made of silicon oxide having a thickness of about 200 nm, and a silicon nitride film having a thickness of about 70 nm Barrier insulating film 19 made of silicon, a third insulating film 20 made of silicon oxide having a thickness of about 200 nm, and a third barrier insulating film made of silicon nitride having a thickness of about 70 nm (second diffusion preventing insulation) Layers) 21 are sequentially stacked.
[0060]
Here, the second insulating film 18, the second barrier insulating film 19, the third insulating film 20, and the third barrier insulating film 21 constitute a second interlayer insulating film 22. A second insulating film having a depth of about 250 nm and a width of about 240 nm from the upper surface of the third barrier insulating film 21 is provided on the film 22, that is, on the third insulating film 20 and the third barrier insulating film 21. A groove 22a is provided, and the lower part of the second interlayer insulating film 22, that is, the second insulating film 18 and the second barrier insulating film 19 are formed on the lower surface of the lower wiring 16 from the bottom of the second groove 22a. Is provided.
[0061]
A third barrier metal film 23 made of tantalum nitride having a thickness of about 20 nm is formed on the wall surfaces of the second trench 22a and the connection hole 22b in the second interlayer insulating film 22. The upper layer wiring 24 and the wiring connection part 24a are respectively formed by embedding copper as a wiring material inside the groove part 22a and the connection hole part 22b.
[0062]
Here, the upper surface of the upper wiring 24 is disposed at a position where the depth from the upper surface of the third barrier insulating film 21 in the second groove 22a is about 10 nm to 20 nm, and the upper wiring in the second groove 22a is formed. A fourth barrier metal film (second diffusion prevention film) 25 made of tantalum nitride having a film thickness of about 10 to 20 nm is provided on 24.
[0063]
In the semiconductor device according to the first embodiment configured as described above, the first barrier insulating film 13, the second barrier insulating film 19, and the third barrier insulating film 21 have a barrier property against copper atoms (copper The first barrier metal film 15, the second barrier metal film 17, and the third barrier metal film are made of a silicon nitride film which is an insulating material having a property of preventing diffusion of atoms. 23 and the fourth barrier metal film 25 are made of tantalum nitride, which is a conductive material having a barrier property against copper atoms, so that the wiring material of the lower wiring 16 and the upper wiring 24 is the first interlayer insulating film 14. In addition, diffusion to the second interlayer insulating film 22 can be prevented.
[0064]
Specifically, since the side and bottom surfaces of the lower wiring 16 are covered with the first barrier metal film 15, copper atoms, which are the wiring material forming the lower wiring 16, diffuse into the first insulating film 12. In addition, since the upper surface of the lower wiring 16 is covered with the second barrier metal film 17 except for the region where the wiring connection portion 24a is formed, copper atoms are removed from the second insulating film. 18 is prevented.
[0065]
Further, since the side surfaces of the upper wiring 24 and the wiring connection portion 24a are covered with the third barrier metal film 23, the copper atoms constituting the upper wiring 24 and the wiring connection portion 24a are not covered by the third insulating film 20 and the third Diffusion to the second insulating film 18 is prevented.
[0066]
Furthermore, since the second barrier insulating film 19 is provided on the bottom of the upper wiring 24 except for the region where the wiring connection portion 24a is formed on the bottom surface, silicon nitride prevents diffusion of copper atoms. Since it is an insulating material having a barrier property, copper atoms, which are wiring materials forming the upper layer wiring 24, are prevented from diffusing into the second insulating film 18.
[0067]
In addition, the fourth barrier metal film 25 formed on the upper wiring 24 and the third barrier insulating film 21 constituting the uppermost layer of the second interlayer insulating film 22 form another wiring on the upper wiring 24. In the case of forming another wiring via the interlayer insulating film, the diffusion of the wiring material constituting the upper wiring 24 and the other wiring formed thereon can be prevented.
[0068]
Here, in the semiconductor device according to the first embodiment, since the diffusion of the wiring material from the lower wiring 16 to the second insulating film 18 can be prevented by using the second barrier metal film 17, the second interlayer insulating film is formed. Since it is not necessary to form a barrier insulating film in the lowermost layer of the film 22, the capacitance between the lower wiring 16 and the upper wiring 24 is smaller than that of the third conventional semiconductor device.
[0069]
In addition, since there is no barrier metal film between the lower wiring 16 and the wiring connection part 24a, the structure is such that copper atoms as the wiring material can move between the lower wiring 16 and the wiring connection part 24a. Void growth due to electromigration (EM) can be suppressed, and EM resistance is improved.
[0070]
A feature of the first embodiment is that a first insulating film 12 and a first barrier insulating film 13 are sequentially laminated as a first interlayer insulating film 113 for insulating between the semiconductor substrate 11 and the lower wiring 16. The upper surface of the lower wiring 16 is disposed between the upper surface and the lower surface of the first barrier insulating film 13, and the wiring connection portion 24 a on the upper surface of the lower wiring 16 is formed. Is characterized in that the first barrier insulating film 13 is arranged on the region excluding the above.
[0071]
With such a configuration, even when the alignment shift occurs when the connection hole 22b is formed, the wiring material forming the wiring connection portion 24a is changed to the first insulating film 12 by the first barrier insulating film 13. Can be prevented.
[0072]
Hereinafter, a description will be given, with reference to the drawings, of a case where misalignment occurs when the connection hole 22b is formed in the semiconductor device of the first embodiment.
[0073]
FIG. 1B illustrates a first example in which, in the semiconductor device illustrated in FIG. 1A, when the connection hole 22 b is formed, a part of the connection hole 22 b protrudes to the side of the lower wiring 16 due to misalignment. 2 shows a cross-sectional configuration in the case where it is disposed above an interlayer insulating film 14.
[0074]
As shown in FIG. 1B, when a part of the connection hole 22 b is disposed on the first barrier insulating film 13, the bottom surface of the connection hole 22 b coincides with the upper surface of the lower wiring 16. Be placed. At this time, in a region of the first barrier insulating film 13 facing the connection hole 22b, a portion above the upper surface of the lower wiring 16 is removed.
[0075]
Here, in the first embodiment, the thickness of the first barrier insulating film 13 is about 70 nm, and the depth from the upper surface of the first barrier insulating film 13 to the upper surface of the lower wiring 16 is 10 to 20 nm. Therefore, the thickness of the region of the first barrier insulating film 13 facing the connection hole 22b is about 50 to 60 nm, so that the first barrier insulating film 13 has a sufficient barrier property against copper atoms. Is done. Therefore, the diffusion of copper atoms from the wiring connection portion 24 a to the first insulating film 12 is prevented by the first barrier insulating film 13.
[0076]
As described above, according to the semiconductor device of the first embodiment, the upper surface of the lower wiring 16 is covered with the second barrier metal film 17 except for the region where the wiring connection portion 24a is formed. Therefore, EM resistance can be improved, and since there is no need to form a barrier insulating film in the lowermost layer of the second interlayer insulating film 22, the capacitance between wirings does not increase. Further, since the upper surface of the lower wiring 16 is disposed between the upper surface and the lower surface of the first barrier insulating film 13, the wiring from the wiring connecting portion 24 a to the first insulating film 12 even if the alignment shift occurs. Material diffusion can be prevented.
[0077]
In the semiconductor device according to the first embodiment, since the upper surface of the upper wiring 24 is disposed between the upper surface and the lower surface of the third barrier insulating film 21, another wiring layer is formed on the upper wiring 24. Is formed, as in the case where the upper wiring 24 is formed on the lower wiring 16, it is possible to cope with the misalignment and to reduce the capacitance between the wiring between the upper wiring 24 and the other wiring thereon. Can be reduced.
[0078]
(Manufacturing method of the first embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.
[0079]
2 (a) to 2 (d), FIGS. 3 (a) to 3 (d), FIGS. 4 (a) to 4 (d), and FIGS. 5 (a) to 5 (c) 4 illustrates a cross-sectional configuration in a process order of a method for manufacturing a semiconductor device according to one embodiment.
[0080]
First, as shown in FIG. 2A, a first insulating film having a thickness of about 250 nm is formed on a semiconductor substrate 11 provided with a semiconductor integrated circuit (not shown) by, for example, a chemical vapor deposition (CVD) method. A first interlayer insulating film 14 is formed by sequentially depositing a film 12 and a first barrier insulating film 13 having a thickness of about 70 nm.
[0081]
Next, as shown in FIG. 2B, the first interlayer insulating film 14 is patterned by using a photolithography method and a dry etching method, so that the depth of a wiring groove for forming a lower wiring is reduced. A first groove 14a having a thickness of about 250 nm and a width of about 240 nm is formed.
[0082]
Next, as shown in FIG. 2C, the bottom surface of the first groove portion 14a is formed on the first interlayer insulating film 14 over the entire surface including the bottom surface and the wall surface of the first groove portion 14a by the sputtering method. The first tantalum nitride film 15A is formed such that the thickness of the first tantalum nitride film becomes about 20 nm.
[0083]
Next, as shown in FIG. 2D, the first copper film 16A is formed on the first tantalum nitride film 15A by electrolytic plating over the entire surface so as to fill the inside of the first groove 14a. Is deposited. Here, in the step of forming the first copper film 16A, it is preferable to form a thin film made of copper by using a sputtering method prior to the electrolytic plating method so that copper as a plating metal is easily deposited. .
[0084]
Next, as shown in FIG. 2E, the upper portions of the first copper film 16A and the first tantalum nitride film 15A above the first interlayer insulating film 14 are formed by a chemical mechanical polishing (CMP) method. The layers are sequentially removed, and the upper surface of the first interlayer insulating film 14 is planarized. In this flattening step, the polishing conditions in the CMP method are adjusted to conditions for over-polishing until the depth from the upper surface of the first barrier insulating film 13 to the upper surface of the first copper film 16A becomes about 10 nm to 20 nm. I do. As a result, the first barrier metal film 15 is formed from the first tantalum nitride film 15A, and the upper surface is formed between the upper surface and the lower surface of the first barrier insulating film 13 from the first copper film 16A. The arranged lower layer wiring 16 is formed.
[0085]
Here, since the upper surface of the lower wiring 16 is arranged below the upper surface of the first barrier insulating film 13, the upper surface of the first barrier insulating film 13 and the lower wiring 16 are formed in the first groove 14 a. A step is formed between the upper surface and the upper surface.
[0086]
Next, as shown in FIG. 3A, the film thickness on the first interlayer insulating film 14 is formed on the first interlayer insulating film 14 over the entire surface including the lower wiring 16 by a sputtering method. The second tantalum nitride film 17A is formed to have a thickness of about 20 nm. Thereby, the second tantalum nitride film 17A is also formed in a region between the upper surface of the first barrier insulating film 13 and the upper surface of the lower wiring 16.
[0087]
Next, as shown in FIG. 3B, a portion of the second tantalum nitride film 17A above the first interlayer insulating film 14 is removed by a CMP method to remove the second tantalum nitride film 17A from the second tantalum nitride film 17A. The barrier metal film 17 is formed, and the upper surface of the first interlayer insulating film 14 is flattened.
[0088]
Here, since the upper surface of the lower wiring 16 is disposed between the upper surface and the lower surface of the first barrier insulating film 13, the second tantalum nitride film 17 </ b> A is exposed on the upper surface of the first interlayer insulating film 14. Then, the second barrier insulating film 17 is formed in a self-aligned manner with respect to the first groove 14a.
[0089]
That is, the second barrier metal film 17 is formed such that the upper surface thereof substantially coincides with the upper surface of the first barrier insulating film 13, and the thickness thereof is from the upper surface of the first barrier insulating film 13 to the upper surface of the lower wiring 16. To a thickness of about 10 nm to 20 nm, which is a depth up to 10 nm. Thus, the second barrier metal film 17 can be formed to have a sufficient thickness to prevent diffusion of copper atoms.
[0090]
Next, as shown in FIG. 3C, a second layer having a thickness of about 200 nm is formed on the first interlayer insulating film 14 over the entire surface including the second barrier metal film 17 by the CVD method. An insulating film 18, a second barrier insulating film 19 having a thickness of about 70 nm, a third insulating film 20 having a thickness of about 200 nm, and a third barrier insulating film 21 having a thickness of about 70 nm are sequentially formed. accumulate. Thus, the second interlayer formed of the second insulating film 18, the second barrier insulating film 19, the third insulating film 20, and the third barrier insulating film 21 is formed on the first interlayer insulating film 14. An insulating film 22 is formed.
[0091]
Next, as shown in FIG. 3D, the second interlayer insulating film 22 is patterned by photolithography and dry etching to form a second trench 22a having a width of about 240 nm and a depth of about 250 nm. The connection hole 22b having a diameter of about 140 nm and a depth of about 250 nm is formed. Here, the second barrier insulating film 19 becomes an etching stopper film when patterning the second groove 22a. Therefore, the depth of the second groove 22a is the depth from the upper surface of the third barrier insulating film 21 to the upper surface of the second barrier insulating film 19, and the depth of the connection hole 22b is the second barrier insulating film. The depth is from the upper surface of the first barrier metal film 19 to the upper surface of the second barrier metal film 17.
[0092]
In a photolithography method for forming the connection hole 22b, a photomask for patterning the connection hole 22b is aligned (aligned) with the second interlayer insulating film 22 so that the mask pattern is The position is adjusted so that the entire region of the opening for forming the portion 22b is arranged on the upper surface of the lower wiring 16.
[0093]
Next, as shown in FIG. 4A, the connection is formed on the second interlayer insulating film 22 over the entire surface including the wall surface and the bottom surface of the second groove portion 22a and the connection hole portion 22b by the sputtering method. The third tantalum nitride film 23A is formed so that the thickness at the bottom surface of the hole 22b is about 20 nm.
[0094]
Next, as shown in FIG. 4B, anisotropic etching is performed on the third tantalum nitride film 23A and the second barrier metal film 17 by dry etching to form a lower wiring on the bottom surface of the connection hole 22b. Expose 16. Here, as an etching gas for etching the third tantalum nitride film 23A and the second barrier metal film 17, in the tantalum nitride dry etching step, argon (T) can remove tantalum nitride and silicon nitride at almost the same rate. Ar) is performed by sputter etching using a gas.
[0095]
As a result, a portion of the third tantalum nitride film 23A formed on the upper surface of the second interlayer insulating film 22 and a portion formed on the bottom surface of the second groove 22a and the connection hole 22b are removed. A third barrier metal film 23 is formed from the third tantalum nitride film 23A so as to cover the wall surfaces of the second groove 22a and the connection hole 22b.
[0096]
Next, as shown in FIG. 4C, the second trench 22a and the connection hole 22b are buried on the second interlayer insulating film 22 by a sputtering method and an electroplating method so as to fill the inside. Is deposited.
[0097]
Next, as shown in FIG. 5A, a portion of the second copper film 24A above the second interlayer insulating film 22 in the second copper film 24A is removed, and planarization is performed. Also in this flattening step, the depth from the upper surface of the third barrier insulating film 21 to the upper surface of the second copper film 24A is set to 10 to 10 by setting the second copper film 24A to be over-polished. The second copper film 24A is polished and removed until the thickness becomes about 20 nm. Thus, the upper wiring 24 whose upper surface is disposed between the upper surface and the lower surface of the third barrier insulating film 21 is formed from the second copper film 24A, and the connection hole in the second copper film 24A is formed. The region formed in the part 22b becomes a wiring connection part 24a that connects the upper wiring 24 and the lower wiring 16.
[0098]
Next, as shown in FIG. 5B, the film thickness on the second interlayer insulating film 22 is formed on the second interlayer insulating film 22 over the entire surface including the upper wiring 24 by sputtering. A fourth tantalum nitride film 25A is formed to have a thickness of about 20 nm. As a result, the fourth tantalum nitride film 25A is also formed in a region between the upper surface of the third barrier insulating film 21 and the upper surface of the upper wiring 24.
[0099]
Next, as shown in FIG. 5C, the upper part of the second interlayer insulating film 22 in the fourth tantalum nitride film 25A is removed by the CMP method, so that the upper surface of the upper wiring 24 is formed. A fourth barrier metal film 25 is formed from the fourth tantalum nitride film 25A. As a result, the thickness of the fourth barrier metal film 25 becomes about 10 nm to 20 nm, which is the depth from the upper surface of the third barrier insulating film 21 to the upper surface of the upper wiring 24.
[0100]
Through the above steps, the semiconductor device according to the first embodiment shown in FIG. 1A is completed.
[0101]
In each step of forming the first tantalum nitride film 15A, the second tantalum nitride film 17A, the third tantalum nitride film 23A, and the fourth tantalum nitride film 25A, a CVD method is used instead of a sputtering method. Is also good.
[0102]
Hereinafter, in the first method for manufacturing a semiconductor device, a part of the connection hole 22b protrudes to the side of the lower wiring 16 due to misalignment of the photomask when the connection hole 22b is formed, and the first interlayer insulating film is formed. The case where it is arranged above 14 will be described with reference to the drawings.
[0103]
FIGS. 6A to 6C and FIGS. 7A to 7C show the alignment of the photomask when the connection hole 22b is formed after the step shown in FIG. 3C. FIGS. 3D and 4A to 4D illustrate a case where a part of the connection hole portion 22b protrudes to the side of the lower layer wiring 16 and is disposed above the first barrier insulating film 13 due to displacement. 4 (c), 5 (a) and 5 (c).
[0104]
As shown in FIG. 6A, the misalignment of the photomask occurs in the process of FIG. 3D, so that the second barrier metal formed on the lower wiring 16 is formed on the bottom surface of the connection hole 22b. The film 17 is exposed, and the first barrier insulating film 13 on the side of the lower wiring 16 is exposed.
[0105]
Next, as shown in FIG. 6B, a third tantalum nitride film 23A is formed in the same manner as in the step shown in FIG. 4A. As a result, the third tantalum nitride film 23A is formed on the upper surface of the second barrier metal film 17 and the upper surface of the first barrier insulating film 13 on the bottom surface of the connection hole 22b.
[0106]
Next, as shown in FIG. 6C, anisotropic etching is performed on the third tantalum nitride film 23A and the second barrier metal film 17 in the same manner as in the step shown in FIG. The lower wiring 16 is exposed at the bottom of the hole 22b. Here, as an etching agent for removing the third tantalum nitride film 23A and the second barrier metal film 17, an etching agent capable of removing tantalum nitride and silicon nitride at almost the same speed is used. When the etching is performed until the upper surface of the lower wiring 16 is exposed, the first barrier insulating film 13 located on the bottom surface of the connection hole is also etched.
[0107]
In this dry etching step, etching is performed until the lower wiring 16 is exposed. Therefore, when a portion of the first barrier insulating film 13 above the lower wiring 16 is removed, the etching stops. Therefore, the first barrier insulating film 13 remains on the side of the lower wiring 16, and the first insulating film 12 is not exposed.
[0108]
Specifically, the depth dimension at which the first barrier insulating film 13 is etched in the dry etching step is the same as the depth dimension at which the first barrier insulating film 13 is over-polished in the CMP step of FIG. The region of the insulating film 13 facing the connection hole 22b is etched by about 10 to 20 nm to a thickness of about 50 to 60 nm, and a sufficient film thickness for realizing a barrier property against copper atoms is secured.
[0109]
Next, as shown in FIG. 7A, a second copper film 24A is deposited to fill the inside of the second groove 22a and the connection hole 22b in the same manner as in the step shown in FIG. 4C. I do.
[0110]
Next, as shown in FIG. 7B, the upper part of the second interlayer insulating film 22 in the second copper film 24A is removed in the same manner as in the step shown in FIG. The upper wiring 24 and the wiring connection portion 24a are formed from the copper film 24A, and the upper surfaces of the second interlayer insulating film 22 and the upper wiring 24 are flattened.
[0111]
Here, since the first barrier insulating film 13 having a thickness of about 30 to 40 nm remains on the bottom surface of the connection hole portion 22b on the side of the lower wiring 16, the copper forming the wiring connection portion 24a is formed. The atoms do not diffuse into the first insulating film 12.
[0112]
Next, as shown in FIG. 7 (c), a fourth tantalum nitride film is deposited and then its upper portion is polished and removed in the same manner as in the steps shown in FIGS. 5 (b) and 5 (c). A fourth barrier metal film 25 is formed on the upper surface of the upper wiring 24.
[0113]
As described above, according to the method of manufacturing the semiconductor device of the first embodiment, a part of the connection hole portion 22 b protrudes to the side of the lower wiring 16 due to misalignment and is disposed on the first interlayer insulating film 14. Even in this case, only the portion of the first barrier insulating film 13 exposed on the bottom surface of the connection hole 22b above the upper surface of the lower wiring 16 is removed. Therefore, the first barrier insulating film 13 can prevent the wiring material from diffusing from the wiring connection portion 24a to the first insulating film 12.
[0114]
(Second embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings.
[0115]
8A to 8C, 9A, and 9B show a method for manufacturing a semiconductor device according to the second embodiment. 8 (a) to 8 (c), 9 (a) and 9 (b), the same members as those used in the description of the method for manufacturing the semiconductor device according to the first embodiment will be described. The description is omitted by attaching the same reference numerals. Note that, in the second embodiment, the case where the connection holes 22b are normally arranged is the same as in the first embodiment, and thus illustration and description are omitted.
[0116]
As shown in FIG. 8A, first, first steps are performed on the semiconductor substrate 11 in the same manner as in FIGS. 2A to 2E and FIGS. 3A to 3C. After the formation of the interlayer insulating film 14 and the lower wiring 16, a second interlayer insulating film 22 is formed, and then the second interlayer insulating film 22 is formed on the second interlayer insulating film 22 in the same manner as in the step shown in FIG. The groove 22a and the connection hole 22b are formed. Here, due to misalignment in the step of forming the connection hole 22b, a part of the connection hole 22b protrudes to the side of the lower wiring 16 and is disposed above the first barrier insulating film 13.
[0117]
After that, in the same manner as the steps shown in FIGS. 4A and 4B, the second interlayer insulating film 22 includes the second groove 22a and the bottom surface and the wall surface of the connection hole 22b. After forming the third tantalum nitride film over the entire surface, the third tantalum nitride film and the second barrier metal film 17 located on the bottom surface of the connection hole 22b are removed by anisotropic dry etching to form the connection hole 22b. The lower wiring 16 is exposed on the bottom surface of the substrate.
[0118]
Here, in the second embodiment, in the anisotropic etching for exposing the lower layer wiring 16, an etching agent having a higher etching rate for tantalum nitride than silicon nitride is used. As shown in (1), the portion of the first barrier insulating film 13 exposed on the bottom surface of the connection hole 22b is hardly etched. Here, as an etching gas having a higher etching rate with respect to tantalum nitride than silicon nitride, for example, a plasma gas mainly containing chlorine gas or a mixed gas containing chlorine is used.
[0119]
Next, as shown in FIG. 8B, a second copper film 24A is deposited to fill the inside of the second groove 22a and the connection hole 22b in the same manner as in the step shown in FIG. 4C. I do.
[0120]
Next, as shown in FIG. 8C, the upper part of the second interlayer insulating film 22 in the second copper film 24A is removed in the same manner as in the step shown in FIG. The upper wiring 24 and the wiring connection portion 24a are formed from the copper film 24A, and the upper surfaces of the second interlayer insulating film 22 and the upper wiring 24 are flattened.
[0121]
Next, as shown in FIG. 9A, the fourth interlayer insulating film 22 is formed on the entire surface including the upper layer wiring 24 in the same manner as in the step shown in FIG. A tantalum nitride film 25A is deposited.
[0122]
Next, as shown in FIG. 9B, the fourth tantalum nitride film 25A is polished and removed until the upper surface of the second interlayer insulating film 22 is exposed, similarly to the step shown in FIG. 5C. Thereby, a fourth barrier metal film 25 covering the upper surface of the upper wiring 24 is formed from the fourth tantalum nitride film 25A.
[0123]
As described above, according to the method of manufacturing the semiconductor device of the second embodiment, the first barrier insulating film 13 is hardly etched in the step of exposing the lower wiring 16, so that the first barrier insulating film 13 is exposed at the bottom surface of the connection hole 22b. Even if the thickness of the first barrier insulating film 13 is set to about 50 nm, a sufficient barrier property against copper atoms can be secured after the lower wiring 16 is exposed. Therefore, in the second embodiment, the thickness of the first barrier insulating film 13 can be made smaller than that in the first embodiment, so that the capacitance between wirings can be further reduced.
[0124]
In the first and second embodiments, the material forming the lower wiring 16, the upper wiring 24, and the wiring connection portion 24a is not limited to copper, and may be an alloy containing copper. Further, different materials may be used for the lower layer wiring 16, the upper layer wiring 24, and the wiring connection portion 24a.
[0125]
In the first embodiment and the second embodiment, the material forming the first barrier insulating film 13, the second barrier insulating film 19, and the third barrier insulating film 21 is not limited to silicon nitride. Any insulation having a barrier property against copper atoms may be used. For example, even if silicon carbide (SiC) is used for one or more of the first barrier insulating film 13, the second barrier insulating film 19, and the third barrier insulating film 21, silicon nitride is used. Similarly, the diffusion of the wiring material forming the lower wiring 16, the upper wiring 24 and the wiring connection portion 24a can be prevented.
[0126]
In the first embodiment and the second embodiment, each barrier metal film (that is, the first barrier metal film 15, the second barrier metal film 17, the third barrier metal film 23, and the fourth barrier metal film 23) is used. The material forming the metal film 25) is not limited to tantalum nitride, and another material having a barrier property against copper atoms may be used. In particular, by using a conductive material such as tantalum (Ta), tungsten nitride (WN), or tantalum nitride silicide (TaSiN) as a material forming each barrier metal film, the effect of reducing the capacitance between wirings can be obtained. can get.
[0127]
In the first embodiment and the second embodiment, when another wiring is not formed on the upper wiring, the fourth barrier metal film 25 formed on the upper wiring 24 and the second The third barrier insulating film 21 constituting the uppermost layer of the interlayer insulating film 22 may be omitted.
[0128]
【The invention's effect】
According to the semiconductor device and the method of manufacturing the same of the present invention, since the wiring material can move between the lower wiring and the wiring connection portion, the electromigration resistance is improved, and the first wiring formed on the lower wiring is formed. Since the diffusion of the wiring material from the lower wiring to the second insulating film can be prevented by the diffusion preventing film, the capacitance between the wirings does not increase. Further, even when the alignment connection is misaligned and the wiring connection portion is arranged so as to protrude to the side of the lower wiring, the wiring material is transferred from the wiring connection portion to the first insulating layer by the first diffusion prevention insulating layer. Can be prevented from being diffused. Therefore, it is possible to improve the EM resistance and prevent the diffusion of the wiring material due to the misalignment without increasing the capacitance between the wirings.
[Brief description of the drawings]
FIG. 1A is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention; FIG. FIG. 9 is a cross-sectional configuration view showing a case where a part of a connection hole is formed so as to protrude to the side of a lower wiring.
FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
FIGS. 3A to 3D are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIGS. 4A to 4D are sectional views in the order of steps showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIGS. 5A to 5D are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
FIGS. 6A to 6D show a method of manufacturing a semiconductor device according to the first embodiment of the present invention, in which a misalignment occurs and a part of a connection hole protrudes to the side of a lower wiring; FIG. 4 is a cross-sectional view of a configuration in a process order showing a case where the power supply is performed.
FIGS. 7A to 7D show a method of manufacturing a semiconductor device according to the first embodiment of the present invention, in which a misalignment occurs and a part of a connection hole protrudes to the side of a lower wiring; FIG. 4 is a cross-sectional view of a configuration in a process order showing a case where the power supply is performed.
FIGS. 8A to 8D show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, in which a portion of a connection hole protrudes to the side of a lower wiring due to misalignment. It is a structure sectional view of a process order in a case.
FIGS. 9A to 9D show a method for manufacturing a semiconductor device according to a second embodiment of the present invention, in which a part of a connection hole protrudes to the side of a lower wiring due to misalignment. It is a structure sectional view of a process order in a case.
FIG. 10 is a configuration sectional view showing a semiconductor device according to a first conventional example.
FIG. 11A is a cross-sectional configuration diagram illustrating a semiconductor device according to a second conventional example, and FIG. 11B is a diagram illustrating a semiconductor device according to a second embodiment; FIG. 4 is a cross-sectional view showing a configuration in which a part of the semiconductor device is formed so as to protrude to the side of a lower wiring.
FIG. 12A is a cross-sectional configuration diagram illustrating a semiconductor device according to a third conventional example, and FIG. 12B is a diagram illustrating a semiconductor device according to FIG. FIG. 4 is a cross-sectional view showing a configuration in which a part of the semiconductor device is formed so as to protrude to the side of a lower wiring.
[Explanation of symbols]
11 Semiconductor substrate (semiconductor area)
12 First insulating film (first insulating layer)
13 First barrier insulating film (first diffusion prevention insulating layer)
14 First interlayer insulating film
14a First groove (groove)
15 First barrier metal film
15A First tantalum nitride film
16 Lower layer wiring
16A First copper film (lower wiring formation film)
17 Second barrier metal film (first diffusion prevention film)
17A Second tantalum nitride film (first diffusion barrier film forming film)
18 Second insulating film
19 Second barrier insulating film
20 Third insulating film
21. Third barrier insulating film (second diffusion preventing insulating layer)
22 Second interlayer insulating film
22a Second groove
22b Connection hole
23 Third barrier metal film
23A Third Tantalum Nitride Film
24 Upper layer wiring
24a Wiring connection
24A Second copper film (upper wiring formation film)
25 Fourth barrier metal film (second diffusion prevention film)
25A Fourth Tantalum Nitride Film

Claims (12)

A lower layer wiring formed above the semiconductor region and made of a first wiring material;
A first interlayer insulating film formed on the semiconductor region and insulating between the semiconductor region and the lower wiring;
An upper layer wiring formed above the lower layer wiring and made of a second wiring material;
A wiring connection portion made of the second wiring material and connecting between an upper surface of the lower wiring and a lower surface of the upper wiring;
A second interlayer insulating film formed on the first interlayer insulating film and insulating between the lower wiring and the upper wiring;
A first diffusion prevention film formed in a region of the upper surface of the lower wiring other than a portion where the wiring connection portion is formed, and preventing diffusion of the first wiring material;
The first interlayer insulating film is formed on the first insulating layer and the first insulating layer, and is a first diffusion barrier for preventing the diffusion of the first wiring material and the second wiring material. Consisting of an insulating layer,
A semiconductor device, wherein an upper surface of the lower wiring is provided between an upper surface and a lower surface of the first diffusion prevention insulating layer. 2. The semiconductor device according to claim 1, wherein the first diffusion prevention film is made of a conductive material. 3. The semiconductor device according to claim 1, wherein the first wiring material and the second wiring material are copper or an alloy containing copper. 4. 4. The semiconductor device according to claim 3, wherein a material forming the first diffusion prevention film is any one of tantalum, tantalum nitride, tungsten nitride, and tantalum nitride silicide. 4. The semiconductor device according to claim 3, wherein a material forming the first diffusion prevention insulating layer is silicon nitride or silicon carbide. A second diffusion prevention film that covers the upper wiring and prevents diffusion of the second wiring material;
The second interlayer insulating film has a second insulating layer, and a second diffusion preventing insulating layer formed on the second insulating layer and for preventing diffusion of the second wiring material.
The upper surface of the upper layer wiring is provided so as to be located between the position of the upper surface and the position of the lower surface of the second diffusion prevention insulating layer. 2. The semiconductor device according to claim 1. Forming a first interlayer insulating film by sequentially stacking a first insulating layer and a first diffusion prevention insulating layer on the semiconductor region;
Forming a groove in the first interlayer insulating film;
Forming a lower wiring inside the trench such that the upper surface is located between the upper surface and the lower surface of the first diffusion prevention insulating layer;
Forming a first diffusion barrier film on the lower wiring,
Forming a second interlayer insulating film over the entire surface including the first diffusion preventing film on the first diffusion preventing insulating layer;
Forming an opening through the second interlayer insulating film in the second interlayer insulating film to expose the first diffusion barrier film;
Removing the first diffusion barrier film exposed in the opening to expose a lower wiring on the bottom surface of the opening;
Forming a wiring connection portion and an upper wiring inside the opening. In the step of exposing the lower wiring, the material forming the first diffusion prevention film and the material forming the first diffusion prevention insulating layer are exposed to the opening using an etchant capable of etching. The method according to claim 7, wherein the first diffusion barrier film is removed. In the step of exposing the lower wiring, using an etchant having an etching rate higher than that of the material forming the first diffusion prevention insulating layer than that of the material forming the first diffusion prevention insulating layer. 8. The method according to claim 7, wherein the first diffusion barrier film exposed in the opening is removed by etching. The step of forming the lower wiring includes forming a lower wiring forming film over the entire surface including the groove on the first interlayer insulating film; and forming the lower wiring forming film on the first interlayer insulating film. Forming the lower wiring from the lower wiring forming film by polishing and removing the lower wiring to such an extent that the lower wiring is positioned between the upper surface and the lower surface of the diffusion prevention insulating layer. A method for manufacturing a semiconductor device according to any one of the preceding claims. The step of forming the first diffusion prevention film comprises:
Forming a first diffusion prevention film forming film made of a conductive material over the entire surface including the lower wiring, on the first diffusion prevention insulating layer;
The first diffusion barrier film is removed from the first diffusion barrier film by removing an upper portion of the first diffusion barrier film so that the upper surface of the first diffusion barrier insulating layer is exposed. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming. Forming a second diffusion barrier film on the upper wiring, after the step of forming the upper wiring,
The step of forming the second interlayer insulating film includes a step of sequentially forming a second insulating layer and a second diffusion prevention insulating layer on the first interlayer insulating film,
The step of forming the upper layer wiring,
Forming an upper wiring forming film over the entire surface including the inside of the opening on the second interlayer insulating film;
Forming the upper wiring from the upper wiring forming film by polishing and removing the upper wiring forming film to such an extent that the upper surface is located between the upper surface and the lower surface of the second diffusion prevention insulating layer; The method of manufacturing a semiconductor device according to claim 7, further comprising:

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