JPH11186391A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a dual damascene process for preventing the thickness variation of wiring trenches, without forming voids in a layer insulation film below vias. SOLUTION: Below layer insulation films 12 , 13 , an etching stopper film 31 is provided for etching the insulation films 12 , 13 , then the etching condition is changed, and the stopper film 31 is removed so as to form vias 5 through a layer insulation film 11 , without forming voids in this film 11 , even if a photoresist pattern 4 is deviated. Also below the layer insulation film 13 an etching stopper film 32 provided, and the insulation film 13 is overetched to form wiring trenches 7 of a depth which is aligned with the thickness of the layer insulation film 13 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring structure, and more particularly to a semiconductor device having a dual damascene type wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Present Ultra Large Scale Integrated Circuit (ULSIC)
In general, a multi-layer wiring formed by connecting three or more layers of metal wiring to each other is used. Conventionally, this kind of multilayer wiring has been formed as follows.

First, after a photoresist is applied on a metal film to be a first metal wiring, the photoresist is exposed and developed by photolithography to form a photoresist pattern having the pattern of the metal wiring.

Next, the metal film is anisotropically etched using the photoresist pattern as a mask, and the pattern of the photoresist pattern is transferred to the metal film to form a metal wiring. Thereafter, the photoresist pattern is peeled off and the first
Metal wiring is completed.

Next, after forming a first interlayer insulating film over the entire surface so as to cover the first metal wiring, a via hole reaching the first metal wiring is formed in the interlayer insulating film by photolithography and etching. I do.

Next, after a metal is buried in the via hole to form a connection plug electrode, a second metal wiring is formed in the same manner as the first metal wiring. This second metal wiring is connected to the first metal wiring via the connection plug electrode.

By repeating the series of steps described above as many times as necessary, a multilayer wiring is completed. However, in the conventional method of forming a multilayer wiring of this kind, the following two problems become remarkable as the degree of integration increases. (1) With higher integration, the pattern of the metal wiring becomes finer. Therefore, as the degree of integration increases, it becomes increasingly difficult to form a metal wiring by etching a metal film. (2) As the degree of integration increases, the width between metal wires decreases.
Therefore, it becomes increasingly difficult to completely fill voids between metal wirings with an interlayer insulating film with the increase in integration. This kind of void causes a decrease in reliability. .

In order to solve such a problem, a so-called dual damascene process has been proposed as a method for manufacturing a metal wiring and a connection plug electrode. The dual damascene process is outlined below.

First, as shown in FIG. 7A, a first metal wiring 82 is formed on a _first interlayer insulating film 811. The metal wiring 82 itself is also formed by a dual damascene process described below.

[0010] Next, as shown in FIG.
Forming an interlayer insulating film 81 _2. The thickness of the interlayer insulating film 81 ₂ is equal to the sum of the depth and the second metal interconnection of the via hole 84 (the wiring grooves) forming later, for example from 0.5 to 5
The value is in the range of μm.

Next, as shown in FIG. 7C, after a photoresist pattern 83 for forming a via hole is formed,
And the photoresist pattern 83 as a mask, and etching the interlayer insulating film 81 ₂ by RIE, metal wires 8
A via hole 84 is formed to reach No. 2. Thereafter, the photoresist pattern 83 is stripped.

[0012] Next, as shown in FIG. 7 (d), after forming a photoresist pattern 85 for forming a wiring trench, and the photoresist pattern 85 as a mask, etching the interlayer insulating film 81 ₂ by RIE And via hole 84
Then, a wiring groove 86 connected to the metal wiring 82 is formed. The depth of the wiring groove 86 is equal to the design value of the thickness of the second metal wiring formed of the metal film 87 formed in the next step, and is, for example, a value in the range of 0.1 to 3 μm. After this,
The photoresist pattern 85 is stripped.

Next, as shown in FIG. 7E, a metal film 87 to be a connection plug electrode and a second metal wiring is formed on the entire surface so as to fill the via hole 84 and the wiring groove 86.

The metal film 87 is formed by using, for example, a CVD method or a PVD method. As the material of the metal film 87, for example, tungsten, aluminum, copper, an alloy of aluminum and copper, or the like can be used.

Here, before the metal film 87 is formed, a thin film or a laminated thin film made of a metal or alloy such as titanium nitride, tungsten silicon nitride, niobium or tantalum is formed on the surface of the via hole 84 and the wiring groove 86. Is also commonly practiced. These are also intended to be formed by a CVD method or a PVD method, the laminated film or the purpose of the laminated thin films prevent the diffusion of the like interlayer insulating film 81 ₂ of the constituent metals of the promotion and metal film 87 deposited metal film 87 Is to do.

Finally, as shown in FIG. 7F, by removing the unnecessary metal film 87 outside the via hole 84 and the wiring groove 86, the second metal wiring and the connection plug made of the metal film 87 are removed. Electrodes are simultaneously formed in the wiring groove 86 and the via hole 84, respectively.

By repeating the series of steps described above as many times as necessary, a multilayer wiring is completed. The dual damascene process solves the two problems mentioned above.

That is, in the dual damascene process, since the second metal wiring is formed by embedding the metal film 87 in the wiring groove, it is difficult to form a fine pattern by etching the metal film. Can be avoided.

Since the metal film 87 is buried in the wiring groove 86 to form the second metal wiring, an interlayer insulating film 81 is formed between the second metal wiring and the second metal wiring at the same time as forming the second metal wiring. _Since it is buried with ₂ , it is possible to prevent the generation of voids that cause a reduction in reliability.

However, the dual damascene process has another problem which will be described below. Current ultra-large-scale integrated circuits save space and increase integration density.
For this purpose, for example, it is preferable to design the width of the via hole 84 equal to the width of the metal wiring 82 thereunder. However, the position of the via hole 84 and the metal wiring
It is difficult to completely match the positions of.

Meanwhile, the etching rate of the interlayer insulating film 81 ₂ because there are variations in the surface, in order to reliably form the via hole 84, it is necessary to over-etching the interlayer insulating film 81 _2.

Therefore, where the etching rate of the interlayer insulating film 81 ₂ is high, the interlayer insulating film 81 ₁ thereunder is also etched, and the etched portion may not be filled with the metal film 87.

[0023] As a result, as shown in FIG. 8, the interlayer insulating film 81 ₁ in the vicinity of the via hole 84 below the metal wiring 82, there is a possibility that the voids 88 cause a reduction in reliability occur.

A second problem is that, as shown in FIG. 8, wiring grooves 86 having different depths may be formed. And that the reason for the etching rate of the interlayer insulating film 81 ₂ is not uniform in the plane, if possible that the etching rate varies in a plane even in the case of forming a different wiring groove width and density as was uniform Because there is.

As described above, the design value of the thickness of the second metal wiring is selected for the depth of the wiring groove 86. Therefore, the etching rate of the interlayer insulating film 81 ₂ is that's not uniform in the plane, the wiring grooves 86 of different depths are formed from the design value. As a result, the resistance value of the metal wiring 82 varies.

In the case of the conventional method, since the metal film is etched to form the metal wiring, the variation in the resistance value of the metal wiring is determined by the variation in the thickness of the metal film. For dual damascene process contrast, variation in the resistance value of the second metal wiring 82 is determined by the variation of the etching rate of the interlayer insulating film 81 _2.

Generally, the control of the thickness of the metal film is easier than the control of the etching rate of the insulating film. Therefore, the variation in the resistance value of the metal wiring is larger in the dual damascene process than in the conventional method. Is expected. Therefore, in the dual damascene process, the variation in the overall performance of the very large-scale integrated circuit may exceed an allowable range.

[0028]

As described above, the conventional dual damascene process has a problem that voids are generated in the interlayer insulating film near the metal wiring below the via hole, which causes a reduction in reliability. . Further, there is a problem that wiring grooves having different depths are formed, and the resistance of the metal wiring varies.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device having a multilayer wiring capable of preventing generation of voids and variation in resistance of a wiring layer, and a method of manufacturing the same. Is to do.

[0030]

Means for Solving the Problems [Structure] In order to achieve the above object, a semiconductor device according to the present invention (claim 1)
A first wiring layer formed on a semiconductor substrate, first, second, and third insulating films sequentially formed on the semiconductor substrate and having connection holes reaching the first wiring layer; A fourth insulating film formed on the insulating film of No. 3 and having a wiring groove reaching the first wiring layer through the connection hole;
A connection plug electrode formed inside the connection hole and the wiring groove; and a conductive film as a second wiring layer, wherein the first insulating film and the second insulating film are made of different materials. And the third insulating film and the fourth insulating film are insulating films made of different materials from each other.

Here, the first wiring layer is, for example, a metal wiring buried in an interlayer insulating film on a semiconductor substrate or an impurity diffusion layer such as a source (drain) diffusion layer formed on the surface of the semiconductor substrate. is there.

When a silicon oxide film is used as the second and fourth insulating films, for example, a silicon nitride film can be used as the first and third insulating films. It is preferable that the wiring groove penetrates through the third insulating film and is formed to a certain depth in the second insulating film.

Preferably, a fifth insulating film having a lower dielectric constant than the first insulating film is formed between the first insulating film and the first wiring layer. ). Also,
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first wiring layer on a semiconductor substrate; and forming a first wiring layer on the semiconductor substrate so as to cover the first wiring layer. Forming an insulating film, a second insulating film having a different material from the first insulating film, a third insulating film, and a fourth insulating film having a different material from the third insulating film; , Third, second, and first insulating films are sequentially etched to form connection holes in the insulating films that reach the first wiring layer, wherein the fourth, third, and second insulating films are formed. Are sequentially etched to form a groove penetrating the fourth and third insulating films but not penetrating the second insulating film, and then the first insulating film is substantially etched. Under the etching conditions that are not performed, the second insulating film at the bottom of the groove is removed by over-etching, Changing the etching conditions to remove the first insulating film at the bottom of the groove by etching to form the connection hole; and forming the third hole before or after forming the connection hole. Under the etching conditions in which the insulating film is not substantially etched,
Forming an interconnect groove reaching the first wiring layer through the connection hole in the fourth insulating film by over-etching the insulating film, and forming a conductive film inside the connection hole and the interconnect groove. And forming a connection plug electrode and a second wiring layer.

Here, the etching conditions are, for example, R
In the case of the etching by the IE method, it is realized by changing the etching gas. Specifically, when a silicon oxide film is used as the second and fourth insulating films and a silicon nitride film is used as the first and third insulating films, the silicon oxide film and the silicon nitride film are etched. For this, a mixed gas of CF ₄ gas and O ₂ gas is used as an etching gas. Further, in order to selectively etch the silicon oxide film, a mixed gas of C ₄ F ₈ gas and CO gas is used. Another method of manufacturing a semiconductor device according to the present invention (claim 5) Forming a first wiring layer in
On the semiconductor substrate, covering the first wiring layer,
Sequentially forming a first insulating film, a second insulating film different in material from the first insulating film, a third insulating film, and a fourth insulating film different in material from the third insulating film; A step of sequentially etching the fourth, third, second, and first insulating films to form connection holes reaching the first wiring layer in these insulating films; The second insulating film is sequentially etched to form a groove penetrating the fourth and third insulating films but not penetrating the second insulating film, and then the first insulating film is substantially Under etching conditions that are not etched, the second insulating film at the bottom of the groove is over-etched and removed, and then the etching condition is changed to etch the first insulating film at the bottom of the groove. Forming the connection hole by removing, and forming the connection hole Or after forming, under the etching condition in which the third insulating film is not substantially etched, fourth and over-etching the fourth insulating film
Forming a through hole in the insulating film, and then etching the third insulating film below the through hole by changing etching conditions, and further etching halfway through the second insulating film therebelow. Forming a wiring groove reaching the first wiring layer through the connection hole in the fourth, third, and second insulating films; and forming a conductive film inside the connection hole and the wiring groove. Burying to form a connection plug electrode and a second wiring layer.

Here, after forming a fifth insulating film having a lower dielectric constant than the first insulating film on the semiconductor substrate, the first insulating film is formed, and the first insulating film at the bottom of the groove is formed. After the etching, the connection hole is preferably formed by etching and removing the fifth insulating film at the bottom of the groove (claim 6).

[Operation] According to the semiconductor device having the structure as described in the present invention (claims 1 to 3), the semiconductor device can be manufactured by the method for manufacturing a semiconductor device according to the present invention (claims 4 to 6) without causing the above-described problems. can do.

That is, in the step of forming the connection hole, when the second insulating film is over-etched,
The insulating film functions as an etching stopper. Therefore, even if the mask used in the over-etching is misaligned, the base of the first insulating film is not etched, and voids are formed in the base even when the second insulating film is over-etched. It can be prevented from being formed.

If the first insulating film is formed thin, it is possible to effectively prevent the formation of voids due to the etching of the base when the first insulating film is removed by etching.

In the step of forming the wiring groove, when the fourth insulating film is etched, the third insulating film functions as an etching stopper. Therefore, the fourth insulating film is over-etched so that
The wiring groove having the same thickness as that of the insulating film can be formed.

In the case of the present invention (claim 5 and the like), the third and second insulating films are also etched, which may cause variations in the depth of the wiring groove. There is no practical problem if the insulating film is formed thin and the etching amount of the second insulating film is reduced.

Further, the present invention (claims 2 and 5) has the following operation and effects. That is, in the case of the present invention, even when an insulating film having a higher dielectric constant than the fourth insulating film is used as the third insulating film, such an insulating film having a high dielectric constant is formed on the bottom surface of the second wiring layer. Since it no longer exists, an increase in parasitic capacitance between wiring layers can be suppressed.

Further, the present invention (claims 3 and 6) has the following operation and effects. That is, in the case of the present invention, even if an insulating film having a higher dielectric constant than the second insulating film is used as the first insulating film, the first insulating film and the first wiring layer have a first insulating film. Since the fifth insulating film having a lower dielectric constant than that of the first insulating film is formed, an increase in parasitic capacitance between wiring layers can be suppressed.

[0043]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIGS. 1 and 2 are process sectional views showing a dual damascene process according to a first embodiment of the present invention.

[0044] First, as shown in FIG. 1 (a), SiO ₂
A first metal wiring 2 buried in the first interlayer insulating film 1 ₁ made of. Interlayer insulating film 1 ₁ are those formed on a silicon substrate (not shown). The metal wiring 2 itself is also formed by the dual damascene process of the present embodiment described below.

Next, as shown in FIG.
Forming an etching stopper film 3 _1. The etching stopper film 3 _1, the etching conditions, an insulating film can be etched at a sufficiently slow etch rate or about the same etch rate than the interlayer insulating film 1 _1. In the present embodiment, as the etching stopper film 3 _1, a silicon nitride film. The thickness is, for example, 10
５０50 nm.

[0046] Then, as shown in FIG. (B), a etching stopper film 3 ₁ second interlayer insulating film 1 ₂ made of SiO ₂ on. Interlayer insulating film 1 ₂ thickness, the sum of the film thickness and the etching stopper film 3 ₁ of the film thickness is chosen to be equal to the depth of the design value of the via hole.

[0047] Next, as shown in FIG. 1 (c), to form a second etching stopper film 3 ₂ on the interlayer insulating film 1 _2.
The etching stopper film 3 _2, like the etching stopper film 3 _1, the etching conditions, an insulating film can be etched at a sufficiently slow etch rate or about the same etch rate than the interlayer insulating film 1 _1.

In this embodiment, the etching stopper film 3
₂ , a silicon nitride film is used, and its thickness is, for example, in the range of 10 to 50 nm. The etching stopper film 3 ₂ and the etching stopper film 3 ₁ need not be an insulating film made of the same material, nor need to be the same thickness.

[0049] Then, as shown in FIG. (C), a third interlayer insulating film 1 ₃ on the etching stopper film 3 _2.
The thickness of the interlayer insulating film 1 ₃ is the same as the thickness of the second metal wiring formed later. Further, an interlayer insulating film 1 ₃ is the same kind of insulating film and the interlayer insulating film 1 _2, wherein the Si
O ₂ film.

[0050] Next Fig. 1 (d), the photoresist pattern 4 of the interlayer insulating film 1 ₃ for via hole formation
Form on top. Next, as shown in FIG. 2 (d), the etching conditions etching rate of the etching stopper film 3 ₂ and the interlayer insulating film 1 ₃ is substantially the same, using the photoresist pattern 4 as a mask, an etching stopper film 3 ₂ an interlayer insulating film 1 ₃ is etched by RIE. The above etching conditions can be realized, for example, by using a mixed gas of CF ₄ gas and O ₂ gas as an etching gas.

[0051] Then, as shown in FIG. 2 (d), When the etching reaches the interlayer insulating film 1 _2, the etching stopper film 3
₁ whichever is the etching conditions, the etching rate sufficiently slower than the interlayer insulating film 1 _2, using the photoresist pattern 4 as a mask, to etch the interlayer insulation film 12 by RIE. The above etching conditions can be realized, for example, by using a mixed gas of C ₄ F ₈ gas and CO gas as an etching gas.

[0052] Here, the etching of the interlayer insulating film 1 _2,
The etching rate of the interlayer insulating film 1 ₂ since there are variations in the surface, and over-etching. This allows
The through-holes can be reliably formed in the interlayer insulating film 1 _2.

[0053] At this time, etching conditions, because more of the etching stopper film 3 ₁ are chosen such that the etch rate than the interlayer insulating film 1 ₂ is sufficiently slow, the etching stops at the etching stopper film 3 _1.

[0054] Therefore, even if occurred misalignment photoresist pattern 4, an interlayer insulating film 1 ₁ below the through hole of the interlayer insulating film 1 ₂ is etched, the metal film is the etched portion is formed later 8 By not being buried by the step, the formation of voids can be prevented.

[0055] Next, as shown in FIG. 2 (e), by changing the etching condition, using the photoresist pattern 4 as a mask, the etching stopper film 3 ₁ at the bottom of the interlayer insulating film 1 _second through-hole of RIE And remove it by etching. As a result, a via hole 5 reaching the metal wiring 2 is formed. Thereafter, the photoresist pattern 4 is stripped.

[0056] Here, since the etching stopper film 3 ₁ is thin, can be removed in a short time of etching. Therefore,
Is the interlayer insulating film 1 ₁ etching, no voids are formed. Further, the etching conditions, but more of the etching stopper film 3 ₁ is preferably more chosen such that the etch rate is sufficiently faster than the interlayer insulating film 1 _3, not necessarily the same.

[0057] Next, as shown in FIG. 2 (f), a photoresist pattern 6 for wiring grooves formed on the interlayer insulating film 1 _3. Next, as shown in FIG. (F), the etching conditions, the etching rate sufficiently slower than the etching stopper film 3 ₂ whichever interlayer insulating film 1 _3, using the photoresist pattern 6 as a mask, the interlayer insulating film 1 ₃ is etched by RIE to form a wiring groove 7 reaching the wiring layer 2 via the via hole 5.

[0058] Here, the etching of the interlayer insulating film _1-3,
The etching rate of the interlayer insulating film 1 ₃ since there are variations in the surface, and over-etching. This allows
Variation in depth without the wiring groove 7 can be reliably formed in the interlayer insulating film 1 _3.

[0059] At this time, etching conditions, because more of the etching stopper film 3 ₂ are chosen such that the etch rate than the interlayer insulating film 1 ₃ is sufficiently slow, the etching stops at the etching stopper film 3 _2.

Next, as shown in FIG. 2G, a metal film 8 is formed on the entire surface so as to completely fill the inside of the via hole 5 and the wiring groove 7. This metal film 8 is, for example, CV
The deposition is performed using the D method or the PVD method. In addition, as a material of the metal film 8, for example, tungsten, aluminum, copper, an alloy of aluminum and copper, or the like can be used.

Here, the deposition of the metal film 8 is promoted,
To prevent diffusion to the configuration interlayer insulating film 1 ₂ metal, 1 _3, before forming the metal film 8, the surface of titanium nitride of the via hole 5 and the wiring groove 7, tungsten silicon nitride, niobium, tantalum Alternatively, a thin film or a laminated thin film made of a metal or alloy such as these may be formed.

Next, as shown in FIG. 2H, unnecessary metal films 8 outside the via holes 5 and the wiring grooves 7 are removed by, for example, CM.
By removing with P, the second metal wiring composed of the metal film 8 and the connection plug electrode are simultaneously formed in the wiring groove 8 and the via hole 5, respectively.

By repeating the series of steps described above as many times as necessary, a multilayer wiring is completed. In the present embodiment, the case where the wiring groove 7 is formed after the formation of the via hole 5 has been described, but the via hole 5 may be formed after forming the wiring groove 7. In this case, the steps up to the step shown in FIG. 1C are the same, and then the process proceeds to the step shown in FIG. After the photoresist pattern 3 is removed after FIG. 3C, the process proceeds to the step of FIG.

By the way, as is apparent from FIG. 2H, in the final structure of the above-described embodiment, the etching stopper films 3 ₁ and 3 ₂ are formed by the first metal wiring 2 and the second metal wiring (respectively). It exists directly above and below the metal film 8).

In this embodiment, the etching stopper film 3
_1, 3 ₂ and a silicon nitride film is used as the. Silicon nitride has a higher dielectric constant than a material such as glass generally used as a material of an interlayer insulating film. For example, silicon nitride has a dielectric constant of approximately 7.0, whereas glass has a dielectric constant of 2.5 to 4.2.

If the silicon nitride film, which is an insulating film having a high dielectric constant, is located very close to the corner of the metal wiring, electric charges accumulate. Therefore, the capacitance formed between the metal wirings (parasitic capacitance between wirings). Will increase.

FIG. 4 shows this phenomenon. FIG. 4 shows the increase rate of the parasitic capacitance between the wirings (capacitance increase rate) as a function of the distance between the silicon nitride film and the metal wiring (the distance between the SiN film and the wiring).

When the thickness of the silicon nitride film is 20 nm,
When the silicon nitride film exists directly above or immediately below the metal wiring (distance = 0), the parasitic capacitance increases by 5% or more as compared with the case where no silicon nitride film is provided.

For high performance very large scale integrated circuits, a 5% increase is likely to be unacceptable. However, FIG. 4 also shows a solution to this problem. That is, if the silicon nitride film is separated from the metal wiring by 50 nm, the capacity increase rate can be suppressed to about 2%. Therefore, by arranging the silicon nitride film separately from every corner of the metal wiring, the rate of increase in capacitance can be reduced. The second embodiment described below adopts this idea. (Second Embodiment) FIGS. 5 and 6 are process sectional views showing a dual damascene process according to a second embodiment of the present invention. 1 and 2 correspond to FIG. 1 and FIG.
The same reference numerals as in FIG. 2 are used, and the detailed description is omitted.

[0070] First, as shown in FIG. 5 (a), the first metal wiring 2 buried in the first interlayer insulating film 1 _1. Next, as shown in FIG. 6 (a), the entire surface thin spacer insulating film 9, the first etching stopper film 3 _1, second interlayer insulating film 1 _2, the second etching stopper film 3, _second and third They are sequentially formed interlayer insulating film 1 _3. Spacer insulating film 9 is lower insulating film having a dielectric constant than the etching stopper film 3 _1,
An example is an SiO ₂ film.

[0071] In this manner, in the present embodiment, an amount corresponding to the thickness of the low dielectric constant spacers insulating film 9, the first metal wiring 2 is so away from the etching stopper film 3 _1, parasitic capacitance is reduced. The thickness of the spacer insulating film 9 corresponds to the required reduction in the parasitic capacitance, for example, 50 nm.
It is. The etching stopper film 3 _1, 3 ₂ and the interlayer insulating film 1 _2, 1 ₃ of the material, the thickness is the same as in the first embodiment.

[0072] However, the interlayer insulating film 1 ₂ The thickness of the film thickness and the etching stopper film 3 of the thickness and the spacer insulating film 9
The sum of the film thickness and the thickness of ₁ is selected so as to be equal to the design value of the depth of the via hole to be formed later.

[0073] Next Fig. 5 (b), the photoresist pattern 4 of the interlayer insulating film 1 ₃ for via hole formation
After forming the above, using the photoresist pattern 4 as a mask to etch the interlayer insulating film 1 _3, the etching stopper film 3 ₂ and the interlayer insulating film 1 ₂ by RIE. Thereafter, the photoresist pattern 4 is stripped.

The step of FIG. 5B is the same as the step of FIG. 1D of the first embodiment, and the same effects as those of the first embodiment can be obtained. Next, as shown in FIG. 5 (c), the interlayer photoresist pattern 6 for forming a wiring trench insulating film 1 ₃
After forming the above, using the photoresist pattern 6 as a mask, the interlayer insulating film 1 ₃ is etched by an RIE method to form a wiring groove 7.

The step of FIG. 5C is the same as the step of FIG. 2F of the first embodiment, and the same effects as those of the first embodiment can be obtained. Next, as shown in FIG. 6 (d), after removing the photoresist pattern 6 is removed by etching the etching stopper 3 ₁ and the spacer insulating film 9 by RIE.

[0076] The etching stopper film 3 ₂ at the bottom of the wiring groove 7 are removed by etching, and further part of the interlayer insulating film 1 ₂ thereunder is etched. As a result, the bottom of the wiring groove 7 becomes lower than the etching stopper film 3 _2.

[0077] Also, since the etching stopper film 3 ₁ and the spacer insulating film 9 is thin, it can be removed in a short time of etching. Thus is the interlayer insulating film 1 ₁ etching, it is possible to prevent the voids are formed. Further, the etching conditions, but more of the etching stopper film 3 ₁ is preferably more chosen such that the etch rate is sufficiently faster than the interlayer insulating film 1 _3, not necessarily the same.

Thereafter, a second metal wiring and a connection plug electrode made of the metal film 8 are formed in accordance with the steps of FIGS. 2G and 2H of the first embodiment. A cross-sectional view at this stage is shown in FIG.

[0079] As shown in FIG. 6 (e), the corners of the second metal wiring made of a metal film 8, the etching stopper film 3 ₂ made of a silicon nitride film having a high dielectric constant insulating film
Does not exist, it is possible to suppress an increase in parasitic capacitance between wirings.

Thus, according to the present embodiment, not only the same effects as in the first embodiment can be obtained, but also the effect that the increase in the parasitic capacitance between wirings can be suppressed.
In addition, even if the spacer insulating film 9 is omitted, the parasitic resistance can be reduced as compared with the related art. Also, in the present embodiment, as in the case of the modification of the first embodiment, after a photoresist pattern 6 for forming a wiring groove is formed and etched first, a photoresist pattern for forming a via hole is formed. May be etched.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the first wiring layer is the metal wiring 2 has been described, but an impurity diffusion layer such as a source / drain layer formed on the surface of a silicon substrate may be used. In addition, various modifications can be made without departing from the scope of the present invention.

[0082]

As described above in detail, according to the present invention, even if the second insulating film is over-etched in the step of forming the connection hole, the first insulating film functions as an etching stopper. It is possible to prevent formation of voids in the first insulating film by etching the base of the first insulating film.

In the step of forming the wiring groove, when the fourth insulating film is etched, the third insulating film functions as an etching stopper. It is possible to form a wiring groove having no variation.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a first half of a dual damascene process according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the latter half of the dual damascene process according to the first embodiment of the present invention.

FIG. 3 is a process sectional view showing a modification of the dual damascene process according to the first embodiment;

FIG. 4 is a diagram showing an increase rate of a wiring parasitic capacitance as a function of a distance between a silicon nitride film and a metal wiring;

FIG. 5 is a process cross-sectional view showing the first half of a dual damascene process according to a second embodiment of the present invention.

FIG. 6 is a process sectional view showing the latter half of the dual damascene process according to the second embodiment of the present invention.

FIG. 7 is a process sectional view showing a conventional dual damascene process.

FIG. 8 is a cross-sectional view for explaining a problem of a conventional dual damascene process.

[Explanation of symbols]

1 ₁ 1st interlayer insulating film 1 ₂ 2nd interlayer insulating film (2nd insulating film) 1 ₃ 3rd interlayer insulating film (4th insulating film) 2 1st metal wiring (1st first wiring layer) 3 ₁ ... first etching stopper film (first insulating film) 3 ₂ ... second etching stopper film (third insulating film) 4 ... photoresist pattern 5 ... via hole 6 ... photoresist Pattern 7: wiring groove 8: metal film (connection plug electrode, second wiring layer) 9: spacer insulating film (fifth insulating film)

Claims (6)

[Claims] A first wiring layer formed on a semiconductor substrate; and first, second, and third insulating layers sequentially formed on the semiconductor substrate and having connection holes reaching the first wiring layer. A fourth insulating film formed on the third insulating film and having a wiring groove reaching the first wiring layer through the connection hole; and a fourth insulating film formed inside the connection hole and the wiring groove. The connection plug electrode and a conductive film as a second wiring layer, wherein the first insulating film and the second insulating film are insulating films made of different materials, and A semiconductor device, wherein the third insulating film and the fourth insulating film are insulating films made of different materials. 2. A semiconductor device comprising: a first wiring layer formed on a semiconductor substrate; and first, second, third, and fourth insulating films sequentially formed on the semiconductor substrate, wherein 2nd and 3rd
The insulating film has a connection hole reaching the first wiring layer, and the second, third, and fourth insulating films have a wiring groove reaching the first wiring layer via the connection hole. Comprising: the first, second, third and fourth insulating films; a connection plug electrode formed inside the connection hole and the wiring groove; and a conductive film as a second wiring layer, The first insulating film and the second insulating film are insulating films made of different materials, and the third insulating film and the fourth insulating film are insulating films made of different materials. A semiconductor device characterized by the above-mentioned. 3. A fifth insulating film having a dielectric constant lower than that of the first insulating film is formed between the first insulating film and the first wiring layer. The semiconductor device according to claim 1 or 2, wherein 4. A step of forming a first wiring layer on a semiconductor substrate; and forming a first wiring layer on the semiconductor substrate so as to cover the first wiring layer.
Sequentially forming a first insulating film, a second insulating film different in material from the first insulating film, a third insulating film, and a fourth insulating film different in material from the third insulating film; A step of sequentially etching the fourth, third, second, and first insulating films to form connection holes reaching the first wiring layer in these insulating films; , Sequentially etching the second insulating film,
Forming a groove that penetrates the fourth and third insulating films and does not penetrate the second insulating film, and then forms a bottom portion of the groove under etching conditions in which the first insulating film is not substantially etched; Forming the connection hole by removing the second insulating film by over-etching and then etching and removing the first insulating film at the bottom of the groove under different etching conditions. Before or after forming the connection hole, the third
The fourth insulating film is over-etched under an etching condition in which the insulating film is not substantially etched, and a wiring groove reaching the first wiring layer through the connection hole is formed in the fourth insulating film. And forming a connection plug electrode and a second wiring layer by filling the inside of the connection hole and the wiring groove with a conductive film. 5. A step of forming a first wiring layer on a semiconductor substrate; and forming a first wiring layer on the semiconductor substrate so as to cover the first wiring layer.
Sequentially forming a first insulating film, a second insulating film different in material from the first insulating film, a third insulating film, and a fourth insulating film different in material from the third insulating film; A step of sequentially etching the fourth, third, second, and first insulating films to form connection holes reaching the first wiring layer in these insulating films; , Sequentially etching the second insulating film,
Forming a groove that penetrates the fourth and third insulating films and does not penetrate the second insulating film, and then forms a bottom portion of the groove under etching conditions in which the first insulating film is not substantially etched; Forming the connection hole by removing the second insulating film by over-etching and then etching and removing the first insulating film at the bottom of the groove under different etching conditions. Before or after forming the connection hole, the third
The fourth insulating film is over-etched under etching conditions under which the insulating film is not substantially etched.
Forming a through hole in the insulating film, and then etching the third insulating film below the through hole by changing etching conditions, and further etching halfway through the second insulating film therebelow. Forming a wiring groove reaching the first wiring layer through the connection hole in the fourth, third and second insulating films; and forming a conductive film inside the connection hole and the wiring groove. Forming a connection plug electrode and a second wiring layer by burying the connection plug electrode and the second wiring layer. 6. A method according to claim 6, further comprising: forming a fifth insulating film having a lower dielectric constant than said first insulating film on said semiconductor substrate, forming said first insulating film, and forming said first insulating film at a bottom of said groove. After the insulating film is removed by etching, the fifth portion at the bottom of the groove is removed.
The connection hole is formed by etching and removing the insulating film.
13. The method for manufacturing a semiconductor device according to item 5.