KR100617059B1 - A method for fabricating a damascene of a semiconductor device - Google Patents

Abstract

The present invention relates to a dual damascene formation method capable of increasing the reliability of the device by reducing the etching method and reducing the number of processes, comprising: forming a first photoresist pattern on a predetermined region of the conductive agent; Forming a first insulating film on the entire surface of the conductor including the first photoresist pattern; Planarizing the first insulating film until the first photoresist pattern is exposed; Forming a second photoresist pattern on the exposed first photoresist pattern; Forming a second insulating film on the entire surface of the conductor including the second photoresist pattern; Planarizing the second insulating film until the second photoresist pattern is exposed; And removing the second photoresist pattern to form a trench, and removing the first photoresist pattern to form a hole.

Semiconductor devices, damascene, trenches, holes, chemical mechanical polishing (CMP)

Description

A method for fabricating a damascene of a semiconductor device

1 is a cross-sectional view schematically showing a process of forming a via hole and a trench by the damascene method

2A through 2P are cross-sectional views illustrating a method of forming damascene of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

PR1: First photosensitive film pattern 211: First insulating film

201: diffusion barrier 200: conductor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming damascene of a semiconductor device capable of avoiding an etching method to increase the reliability of the device and reduce the number of processes.

In general, in the manufacture of semiconductor devices, metal wires are used to electrically connect devices and devices, or wires and wires.

Aluminum (Al) or tungsten (W) is widely used as the metal wiring material. However, due to low melting point and high resistivity, it is no longer applicable to ultra-high density semiconductor devices. Due to the high integration of semiconductor devices, it is necessary to use materials with low specific resistance and highly reliable materials such as electromigration (EM) and stress migration (SM). Has become an object of interest.

The reason why copper is used as a metal wiring material is that the melting point of copper is relatively high as 1080 ° C. (aluminum: 660 ° C., tungsten: 3400 ° C.), and the specific resistance is 1.7 μm cm, aluminum (2.7 μΩ cm) and tungsten (5.6 μΩ). It is because it is much lower than cm).

However, copper wiring has a problem that etching is difficult and corrosion is diffused, and thus it has a considerable difficulty in practical use.

The single damascene process or the dual damascene process is applied to improve and put this into practical use. In particular, the dual damascene process is mainly applied.

Here, the damascene process is used to form a trench by etching an insulating layer (Dielectric layer) by photo and etching, and the conductive material such as tungsten (W), aluminum (Al), copper (Cu), etc. It is a technique of forming wiring in the trench shape formed initially by filling it and removing conductive material other than necessary wiring.

In the damascene process, in particular, the dual damascene process is mainly used for forming bit lines, word lines, and metal wirings such as DRAM, and in particular, the upper metal wiring and the lower metal wiring in multi-layer metal wiring. Not only can holes be formed at the same time to be connected, but also steps can be eliminated caused by metal wiring, thereby facilitating subsequent processes.

The dual damascene process includes a via first method, a trench first method, and a self-align method, and FIG. 1 shows holes and trenches formed by the three methods. It is sectional drawing which shows schematically a process.

In the SADD, the etch stop layer 11, the interlayer insulating layer 12, and the etch stop layer 13 are sequentially formed on the conductive layer 10, and then etched using the photoresist pattern 21 for defining the via contact. The via contact region is defined by selectively etching the barrier layer 13.

Subsequently, after the photoresist layer pattern 21 is removed, the interlayer insulating layer 14 and the etch stop layer 15 are sequentially formed, and then the photoresist layer pattern 16 for defining the via contact and the trench structure is formed. At this time, the via contact forming region is to overlap the initially defined region,

Subsequently, the etch stop layer 15 and the interlayer insulating layer 14 are selectively etched using the photoresist pattern 16 as a mask. In the via contact planned area, the etch stop layer (ie, the etched anti-etched film) 13) Self-alignment is performed by etching to the lower interlayer insulating film 12. At this time, the etching process of the via contact and the trench formation region is stopped at the etch stop layers '11' and '13', respectively.

Next, by removing the exposed etch stop layer (11, 13), the hole (V) and trench (T) of the dual damascene structure is formed.

Meanwhile, in the case of the illustrated VFDD and TFDD, the same process is performed. Each of the VFDD and TFDD is slightly different depending on whether the trenches T are formed or the holes V are formed first. Cannot be clarified.

Here, reference numerals '17', '18', '19', and '20' denote photosensitive film patterns, respectively.

However, the conventional dual damascene process has the following problems.

That is, as described above, in order to form holes and trenches, a process of etching the insulating film is essential. However, many problems associated with the etching process have been reported in the damascene process, and the considerable economic, human and time consumption of the damascene process is an obstacle to development.

The present invention has been made to solve the above problems, by using a photosensitive film pattern to define the shape of the hole and the trench, and then patterning the insulating film forming the inner wall of the hole and the trench by chemical mechanical polishing process, etching It is an object of the present invention to provide a method for forming damascene of a semiconductor device that can avoid the process.

Method for forming a damascene of a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a first photosensitive film pattern in a predetermined region on the conductive layer; Forming a first insulating film on an entire surface of the conductive layer including the first photoresist pattern; Planarizing the first insulating film until the first photoresist pattern is exposed; Forming a second photoresist pattern on the exposed first photoresist pattern; Forming a second insulating film on an entire surface of the conductive layer including the second photosensitive film pattern; Planarizing the second insulating film until the second photoresist pattern is exposed; And forming a trench by removing the second photoresist pattern, and forming a hole by removing the first photoresist pattern.

The method may further include forming a diffusion barrier layer between the conductive layer and the first insulating layer.

Forming a barrier layer on the conductive layer exposed through the hole, the inner wall of the hole, the inner wall of the trench, and the second insulating film; Forming a copper seed on the barrier layer; And embedding copper in the holes and trenches to form copper wiring.

The first photoresist pattern and the second photoresist pattern may be removed through an ashing process.

The second photoresist pattern may have a larger width than the first photoresist pattern.

In addition, another method of forming a damascene of a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a first photosensitive film pattern on a predetermined region on a conductive layer; Forming an insulating film on the entire surface of the conductive layer including the photosensitive film pattern; Planarizing the insulating film until the photoresist pattern is exposed; And removing the photoresist pattern to form a hole.

Here, the method further comprises the step of forming a diffusion barrier between the conductive layer and the insulating film.

Forming a barrier layer on the conductive layer exposed through the hole, an inner wall of the hole, and the insulating film; Forming a copper seed on the barrier layer; And embedding copper in the hole to form a copper wiring.

The photoresist pattern may be removed through an ashing process.

Hereinafter, a method of forming damascene of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2P are cross-sectional views illustrating a method of forming damascene of a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in Figure 2a, to prepare a conductor (200). The conductor 200 may be a semiconductor substrate or a semiconductor substrate on which lower wirings are formed.

As shown in FIG. 2B, a diffusion barrier 201 is formed on the entire surface of the conductor 200.

The diffusion barrier 201 prevents oxidation of copper and external diffusion of copper ions when the lower wiring is copper, and protects the lower wiring when the hole 205 to be formed in a subsequent process is formed.

Thereafter, as illustrated in FIG. 2C, the first photoresist film PR11 is coated on the entire surface of the conductor 200 including the diffusion barrier film 201.

As shown in FIG. 2D, the first photoresist film PR11 is patterned through a photo and development process to form a first photoresist pattern PR1 on the diffusion barrier film 201. The first photoresist pattern PR1 is formed in a region corresponding to a hole to be formed later, and has a size corresponding to the size of the hole.

Subsequently, as illustrated in FIG. 2E, a first insulating layer 211 is deposited on the entire surface of the conductor 200 including the first photoresist pattern PR1.

The first insulating layer 211 is formed of a material having a low dielectric constant value in order to solve the problem caused by the parasitic capacitor between the wiring and the wiring. In this case, the first insulating layer 211 is formed to completely cover the first photoresist layer pattern PR1.

Subsequently, as illustrated in FIG. 2F, the first insulating layer 211 is planarized through a chemical mechanical polishing (CMP) process. In this case, the first insulating layer 211 is planarized until the first photoresist layer pattern PR1 is exposed.

Alternatively, an etch back process may be used instead of the chemical mechanical polishing process.

Next, as illustrated in FIG. 2G, the second photosensitive film PR22 is coated on the entire surface of the conductor 200 on which the structure as described above is formed.

Subsequently, as illustrated in FIG. 2H, the second photoresist film PR22 is patterned through a photo and development process to form a second photoresist film pattern PR2 on the first insulating film 211. In detail, the second photoresist pattern PR2 is formed on the first insulating layer 211 so as to completely cover the first photoresist pattern PR1. The second photoresist pattern PR2 corresponds to the trench 204 to be formed later, and has a size corresponding to the size of the trench 204.

Subsequently, as shown in FIG. 2I, a second insulating film 212 is formed on the entire surface of the conductor 200 on which the structure as described above is formed. The second insulating layer 212 is formed to completely cover the second photoresist layer pattern PR2.

The first insulating layer 211 is formed of a material having a low dielectric constant value in order to solve the problem caused by the parasitic capacitor between the wiring and the wiring. In this case, the first insulating layer 211 is formed to completely cover the first photoresist layer pattern PR1.

Next, as shown in FIG. 2J, the second insulating film 212 is planarized through a chemical mechanical polishing process. In this case, the second insulating layer 212 is planarized until the second photoresist layer pattern PR2 is exposed.

Alternatively, an etch back process may be used instead of the chemical mechanical polishing process.

Thereafter, as illustrated in FIG. 2K, the trench 204 is formed by removing the second photoresist pattern PR2 through an ashing process, and also through the ashing process, the first photoresist pattern PR1. Is removed to form the hole 205. In this case, the trench 204 and the hole 205 communicate with each other. The hole 205 exposes a portion of the diffusion barrier film 201.

Next, as shown in FIG. 2L, a portion of the diffusion barrier film 201 exposed through the hole 205 is removed through a wet etching or a reactive ion etching (RIE) process. In this case, a portion of the conductor 200 is exposed while the diffusion barrier layer 201 is removed.

Subsequently, as shown in FIG. 2M, the barrier layer 206 is disposed on the exposed portion of the conductor 200, the inner wall of the hole 205, the inner wall of the trench 204, and the second insulating layer 212. To form. Here, the barrier layer 206 serves to prevent diffusion of copper atoms to be buried later into the first and second insulating layers 212.

The barrier layer 206 may be formed by depositing silver titanium nitride (TiN) by any one of ionization PVD, CVD, and organometallic chemical vapor deposition (MOCVD), or tantalum (Ta) or tantalum nitride. (TaN) is formed by evaporation by ionization PVD method or CVD method, or is formed by depositing tungsten nitride (WN) by CVD method, or titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), tantalum silicon nitride Formed by depositing any one of the ride (TaSiN) by PVD or CVD method

Thereafter, as shown in FIG. 2N, a copper seed layer 207 (Cu seed) is formed on the barrier layer 206. Here, the copper seed layer 207 is formed using any one of titanium (Ti), aluminum (Al), and copper (Cu).

Next, as shown in FIG. 2O, a metal wiring layer 218 is formed on the second insulating film 212 to be filled in the hole 205 and the trench 204. Preferably, the metal wiring layer 218 is formed by depositing copper by a method such as electroless plating, electroplating, sputtering, CVD, ECP (Electro Chemical Plating).

Subsequently, as shown in FIG. 2P, the metal wiring layer 218 is polished to a point where the surface of the second insulating film 212 is sufficiently exposed by chemical mechanical polishing (CMP), and thus the hole 205 and the trench 204 are polished. The metal wires 208 are formed only by leaving the metal wires 208 and the layers 218 inside. At this time, the first chemical mechanical polishing process uses the barrier film 206 as the polishing stop layer, and the copper polishing rate is high, and the diffusion barrier polishing rate is relatively low, and the second chemical mechanical polishing process is copper and the barrier. The film 206 and the second insulating film 212 are polished with no selectivity.

As described above, in the first embodiment of the present invention, when the damascene pattern formed of the holes 205 and the trenches 204 is formed, the conventional etching process is performed by using a chemical mechanical polishing process to avoid the conventional etching process. To solve the problem.

In addition, in the related art, the process of forming the etch stop film on the bottom surface of the hole 205 was essential due to the use of the etching process. However, since the chemical mechanical polishing process is used in the present invention, the etch stop film is formed. Can reduce the process.

On the other hand, the process described above is a dual damascene process consisting of the hole 205 and the trench 204.

Hereinafter, a single damascene process consisting of only the holes 205 will be described.

On the other hand, the drawings will be described with reference to 2a to 2f of the first embodiment.

First, as shown in Figure 2a, to prepare a conductor (200). The conductor 200 may be a semiconductor substrate or a semiconductor substrate on which lower wirings are formed.

As shown in FIG. 2B, a diffusion barrier 201 is formed on the entire surface of the conductor 200.

The diffusion barrier 201 prevents oxidation of copper and external diffusion of copper ions when the lower wiring is copper, and protects the lower wiring when the hole 205 to be formed in a subsequent process is formed.

Thereafter, as illustrated in FIG. 2C, the first photosensitive film PR11 is coated on the entire surface of the conductor 200 including the diffusion barrier film 201.

As shown in FIG. 2D, the photoresist layer is patterned through a photo and development process to form a first photoresist pattern PR1 on the diffusion barrier layer 201. The first photoresist pattern PR1 is formed in a region corresponding to the hole 205 to be formed later, and has a size corresponding to the size of the hole 205.

Subsequently, as illustrated in FIG. 2E, a first insulating layer 211 is deposited on the entire surface of the conductor 200 including the first photoresist pattern PR1.

The first insulating layer 211 is formed of a material having a low dielectric constant value in order to solve the problem caused by the parasitic capacitor between the wiring and the wiring. In this case, the first insulating layer 211 is formed to completely cover the first photoresist layer pattern PR1.

Subsequently, as illustrated in FIG. 2F, the first insulating layer 211 is planarized through a chemical mechanical polishing (CMP) process. In this case, the first insulating layer 211 is flat until the first photoresist layer pattern PR1 is exposed.

Alternatively, an etch back process may be used instead of the chemical mechanical polishing process.

Next, although not shown in the drawing, the hole 205 is formed by removing the first photoresist pattern PR1 through the ashing process. In this case, the hole 205 exposes a portion of the diffusion barrier 201.

Next, a portion of the diffusion barrier layer 201 exposed through the hole 205 is removed through a wet etching or reactive ion etching (RIE) process. In this case, a portion of the conductor 200 is exposed while the diffusion barrier layer 201 is removed.

Subsequently, a barrier layer 206 is formed on the exposed portion of the conductor 200, the inner wall of the hole 205, and the first insulating layer 211. Here, the barrier film 206 serves to prevent diffusion of copper atoms to be buried later into the first insulating film 211.

Here, the material and properties of the barrier film 206 are the same as in the first embodiment described above.

Thereafter, a thin copper seed layer 207 (Cu seed) is formed on the barrier layer 206. Here, the material and properties of the copper seed layer 207 are the same as in the first embodiment described above.

Next, a metal wiring layer 218 is formed on the first insulating film 211 so as to be filled in the hole 205 and the trench 204. Here, the material and characteristics of the metal wiring layer 218 are the same as in the above-described first embodiment.

Subsequently, the metal wiring layer 218 is polished to the point where the first insulating film 211 is sufficiently exposed by chemical mechanical polishing (CMP) method, leaving the metal wiring layer 218 only inside the hole 205 to close the metal wiring 208. Form. At this time, the first chemical mechanical polishing process uses the barrier film 206 as the polishing stop layer, and the copper polishing rate is high, and the diffusion barrier polishing rate is relatively low, and the second chemical mechanical polishing process is copper and the barrier. The film 206 and the first insulating film 211 are polished with no selectivity.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the method for forming damascene of a semiconductor device according to the present invention has the following effects.

In the present invention, the first photoresist pattern is used to define a shape of a hole to be formed later, and a first insulating layer is formed to completely cover the first photoresist pattern. Thereafter, the first insulating film is planarized through a chemical mechanical polishing process until the first photoresist film pattern is exposed. Next, a second photoresist pattern is formed on the first photoresist pattern to define a shape of a trench to be formed later, and a second insulating layer is formed to completely cover the second photoresist pattern. Thereafter, the second insulating film is planarized through a chemical mechanical smoke film process until the second photoresist film pattern is exposed. The first photoresist pattern and the second photoresist pattern are removed to form holes and trenches.                     

As such, since the holes and trenches are formed by the chemical mechanical polishing method, the problems occurring during the conventional etching process may be solved.

In addition, there is an advantage in that the number of steps can be reduced, since a conventional step of forming an etch stop film is not necessary.

Claims (9)

Forming a first photosensitive film pattern on a predetermined region of the conductive agent; Forming a first insulating film on the entire surface of the conductor including the first photoresist pattern; Planarizing the first insulating film until the first photoresist pattern is exposed; Forming a second photoresist pattern on the exposed first photoresist pattern; Forming a second insulating film on the entire surface of the conductor including the second photoresist pattern; Planarizing the second insulating film until the second photoresist pattern is exposed; And, And removing the second photoresist pattern to form a trench, and removing the first photoresist pattern to form a hole. The method of claim 1, And forming a diffusion barrier between the conductor and the first insulating film. The method of claim 1, Forming a barrier layer on the conductor exposed through the hole, the inner wall of the hole, the inner wall of the trench, and the second insulating film; Forming a metal seed on the barrier layer; Forming a metal wiring layer to be buried in the hole and the trench; And, And planarizing the metal interconnection layer to expose the second insulating layer, thereby forming metal interconnections only in the holes and trenches. The method of claim 1, And removing the first photoresist pattern and the second photoresist pattern through one of an ashing process and a wet etching process. The method of claim 1, And the second photoresist pattern has a greater width than the first photoresist pattern. Forming a photoresist pattern on a predetermined region on the conductor; Forming an insulating film on the entire surface of the conductor including the photoresist pattern; Planarizing the insulating film until the photoresist pattern is exposed; Removing the photoresist pattern to form holes; And, And forming a diffusion barrier between the conductor and the insulating film. delete The method of claim 6, Forming a barrier layer on the conductor exposed through the hole, the inner wall of the hole, and the insulating film; Forming a metal seed on the barrier layer; Forming a metal wiring layer to be buried in the hole; And, And planarizing the metal wiring layer to expose the insulating layer, thereby forming metal wiring only in the hole. The method of claim 6, The photosensitive film pattern is a damascene forming method of a semiconductor device, characterized in that the removal through any one of the ashing process and wet etching process.

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