KR100701426B1 - Multi layer metal in semiconductor device and method for manufacturing the same - Google Patents

Abstract

A multilayer metal line of a semiconductor device and a manufacturing method thereof are provided to prevent the degradation of a transistor due to the diffusion of copper atoms and to reduce resistance of the multilayer metal line itself by using an aluminium line as a lower metal line and a copper line as an upper metal line. A multilayer metal line of a semiconductor device includes an aluminium line, an insulating layer and a copper line. The aluminium line(M11) is connected with a transistor through a plug(52). The aluminium line is composed of a diffusion barrier, an aluminium film and an ARC(Anti-Reflective Coating). The insulating layer is formed on the aluminium line. The insulating layer includes a via hole for exposing partially the aluminium line to the outside and a line type trench on the via hole. The copper line(M22) fills the via hole and trench of the insulating layer in order to be electrically connected with the aluminium line.

Description

MULTI LAYER METAL IN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

1 is a structural diagram of a multilayer metal wiring using an aluminum film according to the prior art,

2 is a structural diagram of a multilayer metal wiring using a copper film according to the prior art,

3 is a view illustrating a structure of a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention;

4A to 4E are cross-sectional views illustrating a method of manufacturing a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

51 interlayer insulating film 52 tungsten plug

53: first titanium 54: aluminum film

55: second titanium 56: titanium nitride film

58: first intermetallic insulating film 59: first diffusion barrier film

60: second intermetallic insulating film 61: etching barrier film

62: third intermetallic insulating film 63: second diffusion barrier film

65: via hole 68: trench

69: barrier metal 70: copper seed layer

71: copper film

M11: Aluminum Wiring

M22: Copper Wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a multilayer metallization of a semiconductor device and a manufacturing method thereof.

In general, as the semiconductor device is highly integrated, an aluminum film Al or a copper film Cu is used in forming metal wirings of the semiconductor device.

In the multi-layer metal wiring (MLM) process, the lower metal wiring and the upper metal wiring are both used as aluminum films (Al), and recently, both the lower metal wiring and the upper metal wiring are copper films. It is used as (Cu).

In addition, the multilayer metallization process using the aluminum film was performed through deposition and etching, and the multilayer metallization process using the copper film used a dual damascene process because the copper film was not easily etched.

1 is a structural diagram of a multilayer metal wiring using an aluminum film according to the prior art, Figure 2 is a structural diagram of a multilayer metal wiring using a copper film according to the prior art.

As shown in FIG. 1, in a multilayer metal wiring using an aluminum film according to the related art, a tungsten plug 12 is embedded in an interlayer insulating film 11, and a lower aluminum wiring M1 is connected to a tungsten plug 12. The first intermetallic insulating layer IMD 17 is formed on the lower aluminum interconnection M1, and the vias 18 and vias penetrate the first intermetallic insulating layer 17 and are connected to the lower aluminum interconnection M1. It is formed on the 18 and made of an upper aluminum wiring (M2) connected to the lower aluminum wiring (M1) through the via (18).

Here, the lower layer aluminum wiring M1 is laminated in the order of the first titanium 13, the first aluminum 14, the second titanium 15, and the first titanium nitride film 16, and the upper aluminum wiring M2 is formed. The third titanium 19, the second aluminum 20, and the second titanium nitride film 21 are stacked in this order.

As shown in FIG. 2, in the multilayer metal wiring using the copper film according to the related art, the tungsten plug 32 is embedded in the interlayer insulating film 31, and the first intermetallic insulating film 33 is disposed on the tungsten plug 32. And a lower copper interconnect M1 buried in a trench provided by the first etching barrier layer 34, and a second intermetallic insulating layer 37 and a second etching barrier layer 38 are formed on the lower copper interconnect M1. ), The third intermetallic insulating layer 39 and the third etching barrier layer 40 may include a via hole and an upper copper wiring M2 buried in the trench.

Here, the lower copper wiring M1 is formed of the first barrier metal 35 and the first copper film 36, and the upper copper wiring M2 is the second barrier metal 42 and the second copper film 42. Is done.

However, the multi-layered metal wiring using the aluminum film shown in FIG. 1 has a problem that the resistance increases as the line width of the aluminum wiring decreases, resulting in a decrease in performance of the semiconductor device (particularly, high-speed operation interference), and the copper shown in FIG. In the multilayer metal wiring using the film, there is a problem in that copper atoms in the first copper film 36 constituting the lower copper wiring diffuse through the tungsten plug 32 to the lower transistor to attack and degrade the transistor.

That is, the aluminum wiring does not attack the transistor, but the resistance increases as the line width decreases. In the copper wiring, the resistance does not increase even when the line width decreases.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a multilayer metal wiring of a semiconductor device and a method of manufacturing the same, which prevents an increase in resistance of the metal wiring and does not attack the transistor.

The metal wiring of the semiconductor device of the present invention for achieving the above object is connected to the transistor through a plug and the aluminum wiring stacked in the order of the diffusion barrier film, the aluminum film and the anti-reflection film, covering the upper portion of the aluminum wiring and the surface of the aluminum wiring And an insulating film providing a trench having a via hole and a trench having a line shape over the via hole, and a copper wiring embedded in the via hole and the trench provided by the insulating film and connected to the aluminum wiring.

In addition, the method of manufacturing a multilayer metal wiring of the semiconductor device of the present invention comprises the steps of forming an interlayer insulating film on the semiconductor substrate on which the transistor is formed, forming a plug connected to the transistor through the interlayer insulating film, on the interlayer insulating film Forming an aluminum wiring connected to the plug, forming an intermetallic insulating film covering a top of the aluminum wiring and providing a trench having a line shape over the via hole and a via hole for opening the surface of the aluminum wiring; And embedding a via hole and a trench provided in the intermetallic insulating film to form a copper wiring connected to the aluminum wiring.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a diagram illustrating a structure of a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3, the surface of the aluminum wiring M11 is opened while covering the upper portion of the aluminum wiring M11 and the aluminum wiring M11 connected to the transistor through the tungsten plug 52 embedded in the interlayer insulating layer 51. Insulating films 58, 59, 60, 61, 62, 63, and insulating films 58, 59, 60, 61, 62 for providing a via hole 65 and a trench 68 having a line shape above the via hole 65 And a copper wire M22 embedded in the via hole 65 and the trench 68 provided by the metal wire 63 and connected to the aluminum wire M11.

Here, the aluminum wiring M11 is laminated in the order of the diffusion barrier film 53, the aluminum film 54, and the antireflection film 56/55. The diffusion barrier film 53 is Ti, and the antireflection film is TiN. / Ti (56/55).

The copper wiring M22 includes a barrier metal 69, a copper seed layer 70 on the barrier metal 69, and a copper film 71 on the copper seed layer 70, wherein the barrier metal 69 is formed of Ta. Or TaN.

The insulating films 58, 59, 60, 61, 62, and 63 may include a first intermetallic insulating film 58, a first diffusion barrier film 59, and a second intermetallic insulating film 60 that provide a via hole 65. And an etching barrier film 61 formed on the second intermetallic insulating film 60 to provide the trench 68, a third intermetallic insulating film 62, and a second diffusion barrier film 63. . Here, the first intermetallic insulating film 58, the second intermetallic insulating film 60, and the third intermetallic insulating film 62 are silicon oxide films or dielectric films having a dielectric constant of less than 3.5, and the first diffusion barrier film 59 and the etching barrier. The film 61 and the second diffusion barrier film 63 are silicon nitride films (SiN).

According to FIG. 3, the multi-layered metal wiring of the present invention is formed by a dual damascene process on the aluminum wiring M11 and the aluminum wiring M11 connected to the transistor, and is connected to the copper wiring M22 connected to the aluminum wiring M11. Is done.

As described above, when the lower metal wiring is formed of the aluminum wiring M11 and the upper metal wiring is formed of the copper wiring M22 in the multilayer metal wiring, the deterioration of the transistor due to the diffusion of the copper atoms is prevented and the resistance of the metal wiring is reduced at the same time. Get

4A to 4E are cross-sectional views illustrating a method of manufacturing a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 4A, an interlayer insulating film 51 is formed on a semiconductor substrate (not shown) in which a predetermined process is completed. In this case, before the interlayer insulating layer 51 is formed, lower semiconductor devices such as transistors, bit lines, and capacitors are typically formed, whereby the interlayer insulating layer 51 may have a multilayer structure.

Subsequently, the interlayer insulating layer 51 is etched to form a contact hole to be connected to a part of the lower semiconductor device, and the tungsten plug 52 is embedded in the contact hole. In this case, it is assumed that the tungsten plug 52 is connected to a transistor (not shown).

Subsequently, a first titanium 53, an aluminum film 54, a second titanium 55, and a titanium nitride film 56 are sequentially formed on the interlayer insulating film 52 having the tungsten plug 52 embedded therein, and then a titanium nitride film. A photosensitive film is applied on the pattern 56 and patterned by exposure and development to form the M11 mask 57.

Subsequently, a patterning process is performed by using a reactive ion etching (RIE) method using the M11 mask 57 as an etch barrier to form an aluminum wiring M11 connected to the tungsten plug 52. Therefore, the aluminum wiring M11 has a structure in which the first titanium 53, the aluminum film 54, the second titanium 55, and the titanium nitride film 56 are stacked in this order.

In the aluminum wiring M11, the first titanium 53 is formed to have a thickness of 10 nm to 50 nm to serve as a diffusion barrier, and the second titanium (Ti, 55) and the titanium nitride film (TiN, 56) are anti-reflective (Anti- It serves as a reflecting layer), each film constituting the aluminum wiring (M11) is preferably deposited at a temperature of 100 ℃ to 300 ℃ using Physical Vapor Deposition (PVD). Meanwhile, a titanium nitride film may be used alone as a film that serves as an antireflection film.

As shown in FIG. 4B, after removing the M11 mask 57, a first intermetallic insulating layer 58 is formed on the aluminum wiring M11. Subsequently, the first intermetallic insulating layer 58 is planarized through a chemical mechanical polishing (CMP) process.

Here, the first intermetallic insulating layer 58 may be formed as a single layer, but may also be formed as a double layer or a triple layer to effectively gap-fill the aluminum wiring M11 in which the bending occurs. The first intermetallic insulating layer 58 uses a silicon oxide film or a dielectric film having a dielectric constant of less than 3.5.

The first intermetallic insulating film 58 is formed to be 200 nm to 300 nm thicker than the aluminum wiring M11.

Subsequently, the first diffusion barrier layer 59, the second intermetallic insulation layer 60, the etching barrier layer 61, the third intermetallic insulation layer 62, and the second intermetallic insulating layer 58 may be formed on the planarized first intermetallic insulating layer 58. The diffusion barrier film 63 is formed in sequence. Here, the first diffusion barrier film 59, the etching barrier film 61, and the second diffusion barrier film 63 are formed of silicon nitride film SiN. The second intermetallic insulating film 60 and the third intermetallic insulating film 62 use a silicon oxide film or a dielectric film having a dielectric constant of less than 3.5.

Subsequently, a photoresist film is coated on the second diffusion barrier film 63 and patterned by exposure and development to form a via mask 64. Then, the second diffusion barrier film 63 is formed using the via mask 64 as an etch barrier. , The third intermetallic insulating layer 62, the etching barrier layer 61, the second intermetallic insulating layer 60, the first diffusion barrier layer 59 and the first intermetallic insulating layer 57 are sequentially etched to form an aluminum wiring. A via hole 65 that opens the surface of M11 is formed.

As shown in FIG. 4C, after removing the via hole mask 64, a protective film 66 is formed on the bottom of the via hole 65. At this time, the protective film 66 is to prevent the aluminum wiring (M11) surface of the bottom of the via hole 65 from being attacked during the etching process for the subsequent trench formation, and is etched back after applying the photosensitive film to the bottom of the via hole 65. It was left in the form of filling.

As shown in FIG. 4D, a photoresist film is coated on the entire surface where the protective film 66 is formed, and patterned by exposure and development to form a trench mask 67. At this time, the trench mask 67 is, as is well known, for forming a trench having a line width larger than that of the via hole 65.

Subsequently, the trench 68 is formed by sequentially etching the second diffusion barrier layer 63, the third intermetallic insulation layer 62, and the etching barrier layer 61 using the trench mask 67 as an etch barrier.

Accordingly, the via hole 65 is provided by the lamination of the first intermetallic insulating film 58, the first diffusion barrier film 59, and the second intermetallic insulating film 60, and the trench 68 is formed by the etching barrier film 61. A stack of the third intermetallic insulating film 62 and the second diffusion barrier film 63 is provided.

As shown in FIG. 4E, the trench mask 67 is removed, at which time the protective film 66 formed of the photosensitive film is also removed.

Subsequently, a barrier metal 69 is formed on the entire surface of the via hole 65 and the trench 68, and a copper seed layer 70 made of a copper film is formed on the barrier metal 69. Here, the barrier metal 69 is formed of Ta or TaN, and the barrier metal 69 is for preventing mutual diffusion between the copper wiring M22 and the aluminum wiring M11.

Subsequently, a copper film is formed using the copper seed layer 70 as a seed until the via holes 65 and the trenches 68 are buried, and then the CMP process is performed to serve as vias embedded in the via holes 65. A copper wiring M22 embedded in 68 is formed. At this time, the copper film to be the copper wiring (M22) is formed by electroplating (Electro-plating) using the copper seed layer 70, another method is chemical vapor deposition (CVD) or atoms using the copper seed layer 70 Layer deposition (ALD) can also be used.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the present invention described above, the lower metal wiring is formed of aluminum wiring and the upper metal wiring is formed of copper wiring in the multilayer metal wiring process, thereby preventing deterioration of the transistor due to diffusion of copper atoms, and at the same time, reducing the resistance of the metal wiring to obtain a semiconductor. There is an effect that can increase the speed of the device.

Claims (19)

delete An aluminum wiring connected to the transistor through a plug and stacked in the order of the diffusion barrier film, the aluminum film, and the anti-reflection film; An insulating layer covering the upper portion of the aluminum wiring and providing a trench having a line shape over the via hole, the via hole opening the surface of the aluminum wiring; And A copper wiring embedded in the via hole and the trench provided by the insulating layer and connected to the aluminum wiring Multilayer metallization of a semiconductor device comprising a. The method of claim 2, Wherein the diffusion barrier film is Ti, and the anti-reflection film is TiN / Ti or TiN. The method of claim 2, The copper wiring, And a barrier metal, a copper seed layer on the barrier metal, and a copper film on the copper seed layer. The method of claim 4, wherein The barrier metal is Ta or TaN multilayer metal wiring of the semiconductor device, characterized in that. The method of claim 2, The insulating film, Stacking a first intermetallic insulating film, a first diffusion barrier film, and a second intermetallic insulating film providing the via hole; And A stack of an etching barrier film, a third intermetallic insulating film, and a second diffusion barrier film formed on the second intermetallic insulating film to provide the trench. Multi-layer metallization of a semiconductor device comprising a. The method of claim 6, The first intermetallic insulating film, the second intermetallic insulating film, and the third intermetallic insulating film A multilayer metal wiring of a semiconductor device, characterized in that the silicon oxide film or the dielectric film having a dielectric constant of less than 3.5. The method of claim 6, And the first diffusion barrier film, the etching barrier film and the second diffusion barrier film are silicon nitride films. Forming an interlayer insulating film over the semiconductor substrate on which the transistor is formed; Forming a plug connected to the transistor through the interlayer insulating film; Forming an aluminum wiring connected to the plug on the interlayer insulating film; Forming an intermetallic insulating film covering the upper portion of the aluminum wiring and providing a trench having a line shape on the upper portion of the via hole; And Forming a copper wiring embedded in the via hole and the trench provided by the intermetallic insulating layer and connected to the aluminum wiring; Multi-layer metallization manufacturing method of a semiconductor device comprising a. The method of claim 9, Forming the intermetallic insulating film, Forming a first intermetallic insulating film covering the upper portion of the aluminum wiring; Planarizing the first intermetallic insulating film; Sequentially forming a first diffusion barrier film, a second intermetallic insulation film, an etching barrier film, a third intermetallic insulation film, and a second diffusion barrier film on the planarized first intermetallic insulating film; Etching the second diffusion barrier film, the third intermetallic insulating film, the etching barrier film, the second intermetallic insulating film, the first diffusion barrier film, and the first intermetallic insulating film to form a via hole for opening the surface of the aluminum wiring. step; Forming a protective film on a bottom of the via hole; Etching the second diffusion barrier layer, the third intermetallic insulating layer, and the etching barrier layer to form a trench; And Removing the protective film Multi-layer metallization manufacturing method of a semiconductor device comprising a. The method of claim 9, The protective film is formed of a photosensitive film, characterized in that the multilayer metal wiring manufacturing method of a semiconductor device. The method of claim 9, The first intermetallic insulating film, the second intermetallic insulating film, and the third intermetallic insulating film are A method for producing a multilayer metal wiring of a semiconductor device, characterized in that it is formed of a silicon oxide film or a dielectric film having a dielectric constant of less than 3.5. In accordance with claim 9, The first diffusion barrier film, the etching barrier film and the second diffusion barrier film, A method for producing a multilayer metal wiring of a semiconductor device, characterized by forming a silicon nitride film. The method of claim 9, Forming the aluminum wiring, Stacking in order of a diffusion barrier film, an aluminum film and an antireflection film; Coating a photoresist film on the antireflection film and patterning the photoresist film by exposure and development to form a mask; And Patterning the anti-reflection film, the aluminum film, and the diffusion barrier film in a reactive ion etching manner using the mask as an etch barrier. Multi-layer metallization manufacturing method of a semiconductor device comprising a. The method of claim 14, And the diffusion barrier film is formed of Ti, and the anti-reflection film is formed of TiN / Ti or TiN. The method of claim 14, The diffusion barrier film, the aluminum film and the anti-reflection film are formed by a physical vapor deposition method. The method of claim 9, Forming the copper wiring, Forming a barrier metal on a front surface of the via hole and the trench; Forming a copper seed layer on the barrier metal; Forming a copper film filling the via hole and the trench by using the copper seed layer as a seed; And Planarizing the copper film through chemical mechanical polishing until the surface of the intermetallic insulating film is exposed Multi-layer metallization manufacturing method of a semiconductor device comprising a. The method of claim 17, The copper film, A method for producing a multilayer metal wiring of a semiconductor device, characterized by forming by electroplating, chemical vapor deposition or atomic layer deposition. The method of claim 17, The barrier metal is, Method for manufacturing a multi-layer metal wiring of a semiconductor device, characterized in that formed by Ta or TaN.

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