KR101133527B1 - Method of forming semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device suitable for implementing a MIM pattern module and a capping metal at the same time. And a capacitor having a structure in which the first metal capped on the first metal wire and the first metal / metal oxide film / second metal are stacked on the second metal wire.

Description

Semiconductor device manufacturing method {METHOD OF FORMING SEMICONDUCTOR DEVICE}

1 is a process cross-sectional view showing a semiconductor device manufacturing method according to the prior art,

2A through 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

3 is a cross-sectional view illustrating a structure of a semiconductor device in accordance with an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

21: insulating film pattern 22: barrier metal

23 photoresist pattern 24 lower electrode

24a: metal oxide film 25: upper electrode

M1: first metal wiring M2: second metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a semiconductor device manufacturing method for simultaneously forming a metal wiring and a capacitor.

In order to increase the speed of the semiconductor device, it is required to reduce the thickness of the gate oxide film and reduce the gate length. However, the RC delay caused by the resistance of the wiring and the interlayer insulating film capacitance has a negative effect on the speed of the device to be improved.

Conventionally, aluminum (Al) was used as a wiring material. However, copper (Cu) has higher resistance to electromigration than aluminum, thereby improving the reliability of the semiconductor device, and increasing the signal transmission rate even if the resistivity is half that of aluminum to form a small width. As a result, it is emerging as a useful wiring material for integrated circuits. In addition, copper consumes less power and is cheaper than aluminum. However, copper is a material that is difficult to etch, and thus it is difficult to pattern into a desired wiring shape after deposition. Therefore, a damascene method is used in which an interconnection groove is formed in advance with an interlayer insulating film and then filled with copper.

Sputtering or chemical vapor deposition (CVD) is commonly used to fill the grooves with copper. However, this method is expensive, requires a lot of energy and is complicated to obtain copper from the copper raw material. Moreover, sputtering is not very good in step applicability. In order to solve such a problem, the plating method (including the electroplating method and the electroless plating method) has recently attracted attention.

On the other hand, a capacitor in a DRAM storage element is responsible for storing a certain amount of charge for storing and reading information. Capacitors with this function must first ensure sufficient capacitance and have the insulating properties of the dielectric film with low leakage current.

Initially, a capacitor was formed using a simple method of stacking structure, but a concave or cylinder structure is used to increase the surface area according to the high integration of devices.

In addition, a metal-insulator-metal (MIM) cylindrical capacitor is used to implement a high capacity capacitor. MIM cylindrical capacitors are mainly used for high performance semiconductor devices because of their low resistivity and no parasitic capacitance due to depletion.

1 is a process cross-sectional view showing a semiconductor device manufacturing method according to the prior art.

As illustrated in FIG. 1, a copper wiring for forming a first insulating film pattern 11 on a semiconductor substrate (not shown) and connecting a lower structure and an upper structure to a portion of the first insulating film pattern 11 ( 12) form.

Subsequently, the lower electrode 13 / dielectric film 14 / upper electrode 15 is sequentially formed on the entire structure including the copper wiring 12, and selectively patterned to form a capacitor.

Next, the second insulating layer 16 is deposited on the entire surface including the capacitor, and the via hole is formed to expose a portion of the upper electrode 15 of the capacitor, and the via hole is buried to form the via 17.

As described above, capacitors (U-type and T-type capacitors) of a conventional metal film-dielectric film-metal film (MIM) structure generally have a complicated manufacturing method and form a separate MIM layer during the device integration process. In order to manufacture a highly integrated device in which a MIM capacitor is embedded, an improvement in the structure of the existing MIM capacitor involves a characteristic and structural limitation.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for simultaneously implementing a MIM pattern module and a capping metal.

According to one or more exemplary embodiments of the present inventive concept, a semiconductor device includes: first and second metal wires embedded up to a partial height of an insulating layer, and first and second metal wires capped on the first metal wires; A capacitor formed in a structure in which the first metal / metal oxide film / second metal is stacked is provided.

The present invention also provides a method of forming an insulating film pattern in which a first metal wire and a second metal wire are embedded on a substrate, etching the first and second metal wires in a partial thickness, and selectively forming the second metal wire. Further etching, forming a first metal along a surface of the resultant including the etched first and second metal wires, oxidizing a portion of the thickness of the first metal to form a metal oxide film; Forming a second metal on the entire surface of the resultant product including one metal, and planarizing etching to a target to which the non-oxidized first metal formed on the first metal wire is exposed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

3 is a cross-sectional view illustrating a structure of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3, an insulating film pattern 21 is formed on a substrate (not shown), and the first metal wire M1 and the second metal wire M2 are formed to a predetermined height inside the insulating film pattern 21. ), A first metal 24 is formed on the first metal wire M1, a metal capped structure is formed on the wire, and a capacitor structure is formed on the second metal wire M2. The first metal 24 is formed as an electrode, the metal oxide film 24a in which the first metal is oxidized, and the second metal 25a is formed as an upper electrode on the metal oxide film 24a.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a lower structure is formed on a substrate (not shown), and an insulating film pattern 21 is formed on the lower structure by a damascene process. At this time, the insulating film pattern 21 is a low-k oxide, which is deposited by a spin coating method.

On the other hand, when applying the spin coating method, due to the adhesion (Viscidity) of the low dielectric constant oxide is not applied to the same thickness on the lower structure, it is applied differently depending on the area and density of the lower metal structure.

That is, in general, the case where the area of the lower structure is large is thicker than the case where the area is small, and the area where the density between wirings is high is thicker than the area where the area is low.

Subsequently, a barrier metal 22 is deposited along the profile of the insulating film pattern 21 by applying a damascene process, and copper for metal wiring is deposited on the entire surface of the resultant product including the barrier metal 22. Subsequently, a chemical mechanical polishing (CMP) process is performed to planarize the upper portion of the insulating film pattern 21 and to perform a wire disconnection process to perform the first metal wiring M1 and the second metal wiring ( M2).

On the other hand, the barrier metal 22 is a film for preventing the diffusion of the valence for the metal wiring to fill the open portion (not shown) of the insulating film pattern 21 to the insulating film pattern 21, a material selected from Ta, TaN, TiN and TaSiN Using chemical vapor deposition (CVD) or sputtering.

As shown in FIG. 2B, the first and second metal interconnects M1 and M2 are first etched using a nitric acid solution (eg, a mixed solution of dilute nitric acid, phosphoric acid + nitric acid + acetic acid with HNO ₃ ). The step height is lower than the height of the insulating film pattern 21. At this time, the process is performed so that the thickness of 600 kPa to 700 kPa of the first and second metal wires M1 and M2 can be etched.

As shown in FIG. 2C, a photoresist pattern is formed on the first and second metal wires M1 and M2 subjected to primary chemical etching, and patterned by exposure and development to form via holes. (23) is formed.

At this time, the photoresist pattern 23 is formed so as to open the upper portion of the second metal wiring M2 on which the MIM is to be formed, and then the second chemical etching is performed to etch 900 Å to 1000 Å thickness of the second metal wiring M2. do. On the other hand, the secondary chemical etching also uses a nitric acid solution.

As shown in FIG. 2D, the second metal wire M2 is secondly etched, and then the photoresist pattern 23 is stripped.

Subsequently, a reduction process using a hydrogen plasma is performed to remove the polymer remaining on the first and second metal lines M1 and M2. As the hydrogen plasma, those obtained by applying RF to a gas containing Ar, He, H _2, or the like can be used.

In other words, hydrogen RPC (H ₂ Reactive Pre-Cleaning). Instead of reduction, cleaning may be carried out by chemical etching. In chemical etching methods, inorganic or organic acids are used, such as hydrofluoric acid or hydrochloric acid.

As shown in FIG. 2E, after performing the hydrogen RPC process, the lower electrode 24 of the capacitor is formed on the entire surface of the resultant by CVD.

In this case, the lower electrode 24 serves as a barrier metal in the first metal wire M1 and is selected from a group of heat resistant metals such as tantalum (Ta), tungsten (W), and molybdenum (Mo) or a heat resistant nitride film. The material is formed to a thickness of 700 mm 3.

As shown in FIG. 2F, a surface treatment (O ₂ plasma) and a heat treatment are performed on the entire surface of the resultant on which the lower electrode 24 is formed to oxidize a part thickness of the lower electrode 24 to form a metal oxide film 24a. . The metal oxide film 24a for the capacitor dielectric film can be deposited not only by surface treatment but also by a CVD process in the form of a double film of a metal / metal oxide film, and thus is used in an advantageous process in terms of electrical properties.

As shown in FIG. 2G, copper is deposited on the upper electrode 25 on the front surface of the metal oxide film 24a.

As shown in FIG. 2H, the first metal wiring is planarized by performing a CMP or an entire surface etching process until the unoxidized lower electrode 24 of the first metal wiring M1 that does not constitute the MIM module is exposed. The metal capping 24 is formed on the M1, and the MIM capacitors 24 / 24a / 25a are formed on the second metal wiring M2 having the MIM pattern module.

As described above, when forming the MIM capacitor, by using a two-step chemical etching process to form different step metal steps in the trench pattern, depositing the lower electrode, and oxidizing the lower electrode using heat treatment, An upper electrode may be formed on the upper portion to fabricate a MIM capacitor in the trench.

In addition, this technique can form a MIM structure in a trench pattern, which enables high integration, and can control the thickness of the lower electrode capped in a subsequent CMP process by using a step between a deeply etched pattern and a shallowly etched pattern. In addition, the MIM pattern module and the capping metal can be implemented at the same time, thereby simplifying the process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can implement a MIM structure and metal capping at the same time after a series of processes by forming a metal wiring of different steps by applying a two-step etching process to the metal wiring when manufacturing the MIM capacitor.

In addition, by forming a metal capacitor on the copper metal wiring, there is an advantage that the etch stop layer can be removed during the upper metal wiring forming process, thereby improving the electrical characteristics of the device.

In addition, the optical characteristics of the optical device can be improved by forming the MIM capacitor in the metal wiring.

In addition, since the MIM capacitor can be formed in the metal wiring, high integration of the device can be achieved.

Claims (16)

And first and second metal wires spaced apart from each other and buried at different heights in the insulating film, respectively. And a first metal is laminated on the first metal wiring, and a first metal, a metal oxide film, and a second metal are sequentially stacked on the second metal wiring to form a capacitor. The method of claim 1, The first and second metal wires are formed of a material selected from copper, tungsten and aluminum. The method of claim 1, The first metal is a semiconductor device formed of a material selected from tantalum, tungsten and molybdenum to a thickness of 700 Å. The method of claim 1, The metal oxide layer is formed of a material obtained by partially oxidizing the first metal. The method of claim 1, The second metal is a semiconductor device formed of copper. Forming an insulating layer pattern in which the first metal wiring and the second metal wiring are buried in the substrate; Partially etching the first and second metal wires; Selectively etching the second metal wire further; Forming a first metal along a surface of the resultant product including the etched first and second metal wires; Oxidizing a portion of the thickness of the first metal to form a metal oxide film; Forming a second metal on the entire surface of the resultant including the first metal; And Planar etching of the non-oxidized first metal formed on the first metal wiring is exposed; Semiconductor device manufacturing method comprising a. The method of claim 6, In the step of selectively etching the first and second metal wires, A method of manufacturing a semiconductor device which is etched in 700Å thickness using a nitrate-based chemical solution. The method of claim 7, wherein The nitric acid-based chemical solution is a semiconductor device manufacturing method using a diluted nitric acid solution or a solution of phosphoric acid / nitric acid / acetic acid. The method of claim 6, Selectively etching the second metal wire further includes: Forming a mask for opening the second metal wiring on a predetermined region of the resultant; And And etching the second metal wiring by 900 Å to 1000 Å thickness using the mask as an etching barrier using a nitrate-based chemical solution. The method of claim 6, The first metal is a semiconductor device manufacturing method for forming a material selected from tantalum (Ta), tungsten (W), molybdenum (Mo) and the heat-resistant nitride film-based material to a thickness of 700 Å. The method of claim 6, Oxidizing a portion of the thickness of the first metal to form a metal oxide film, A method of manufacturing a semiconductor device in which an O ₂ plasma treatment is performed to oxidize the first metal to 200 mW to 300 mW thickness. The method of claim 6, Oxidizing a portion of the thickness of the first metal to form a metal oxide film, A semiconductor device manufacturing method formed by using a chemical vapor deposition method. The method of claim 6, The second metal is a semiconductor device manufacturing method formed of copper. The method of claim 6, Forming the second metal on the entire surface of the resultant containing the first metal, Forming the second metal and simultaneously performing a plating process with the seed layer. The method of claim 6, The planarization etching of the unoxidized first metal formed on the first metal wire may be performed by planar etching. A method of manufacturing a semiconductor device by chemical mechanical polishing or full surface etching. The method of claim 6, Forming an insulating film pattern in which a first metal wire and a second metal wire is embedded on the substrate, Forming a barrier metal along the profile of the insulating film pattern.

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