KR20020055309A - Method of manufacturing a metal wiring in a semiconductor device - Google Patents
Method of manufacturing a metal wiring in a semiconductor device Download PDFInfo
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- KR20020055309A KR20020055309A KR1020000084733A KR20000084733A KR20020055309A KR 20020055309 A KR20020055309 A KR 20020055309A KR 1020000084733 A KR1020000084733 A KR 1020000084733A KR 20000084733 A KR20000084733 A KR 20000084733A KR 20020055309 A KR20020055309 A KR 20020055309A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 자기 정렬 다마신 공정 기법으로 비아홀 콘택을 형성할 때 동시에 금속 배선용 홀 패턴을 형성하므로, 비아홀 배선 및 다양한 역할이 가능한 금속 배선을 효과적으로 형성할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, when forming a via hole contact using a self-aligned damascene process technique, a hole pattern for a metal wiring is formed at the same time. A metal wiring formation method of the semiconductor element which can be provided.
반도체 소자가 고집적화 되어 감에 따라 금속 배선의 폭은 좁아지고, 다층 구조를 이루고, 하부 도전층과 상부 도전층을 전기적으로 연결시켜주기 위한 비아 콘택홀의 크기 역시 작아지고 있는 추세이다. 금속 배선의 폭이 좁아지므로 인해 발생되는 저항의 증가를 방지하기 위해 전기 전도도가 우수한 대체 물질에 대한 연구가 진행되고 있는데, 전기 비저항이 낮고 EM(electromigration) 특성 및 SM(stressmigration) 특성이 우수한 구리 배선에 대한 연구가 크게 부각되고 있다. 하지만 구리 박막은 현재까지 반도체 소자의 금속 배선으로 사용하고 있는 알루미늄 박막과는 달리 구리 박막의 재료의 물성적인 특징에 기인하는 문제점이 있다.As semiconductor devices have been highly integrated, the width of metal wirings has narrowed, and the size of via contact holes for forming a multilayer structure and electrically connecting the lower conductive layer and the upper conductive layer is also decreasing. In order to prevent the increase in resistance caused by the narrowing of the metal wiring, research is being conducted on alternative materials having excellent electrical conductivity.Copper wiring with low electrical resistivity and excellent electromigration (EM) and stress migration (SM) characteristics There is a great deal of research on. However, unlike the aluminum thin film, which has been used as metal wiring for semiconductor devices, the copper thin film has a problem due to the physical properties of the material of the copper thin film.
구리 박막은 실리콘 또는 실리콘 산화막 내로 구리 원자가 쉽게 침투하여 들어가 소자의 전기적 특성 및 절연 특성을 악화시키는 문제점이 있으며, 산소와 쉽게 반응하여 구리 산화물을 형성하는 등 내 산화성이 매우 취약하다. 또한, 구리 박막의 증착 방법으로 연구되고 있는 금속유기 화학기상증착(MOCVD) 방법은 양산 공정에 적용될 만큼 안정된 공정을 보이지 않고 있으며, 기존의 플라즈마 방법으로식각시 낮은 증기압으로 인해 식각 공정 진행상 난제가 많다.The copper thin film has a problem in that copper atoms easily penetrate into the silicon or silicon oxide film, thereby deteriorating the electrical and insulating properties of the device. The copper thin film is very vulnerable to oxidation resistance such as easily reacting with oxygen to form copper oxide. In addition, the metal organic chemical vapor deposition (MOCVD) method, which is being studied as a method of depositing a copper thin film, does not show a stable process so as to be applied to a mass production process. .
구리를 반도체 공정에 적용하기 위해서는 위에 열거한 많은 문제점을 고려하여 진행해야한다. 현재 구리를 배선재료로 사용함에 있어 자기 정렬 다마신 공정 기법이 널리 적용하고 있다.In order to apply copper to semiconductor processes, it is necessary to take into consideration many of the problems listed above. Currently, the self-aligned damascene process technique is widely applied to copper as a wiring material.
따라서, 본 발명은 자기 정렬 다마신 공정 기법으로 비아홀 콘택을 형성할 때 동시에 금속 배선용 홀 패턴을 형성하므로, 비아홀 배선 및 다양한 역할이 가능한 금속 배선을 효과적으로 형성할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention forms a metal wiring hole pattern at the same time when forming a via hole contact by a self-aligned damascene process technique, a method of forming a metal wiring of a semiconductor device capable of effectively forming via hole wiring and metal wiring capable of various roles. The purpose is to provide.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 기판12: 층간 절연막11: substrate 12: interlayer insulating film
13: 측부 배리어 절연층14: 하부 금속 배선13: side barrier insulating layer 14: lower metal wiring
15: 상부 배리어 금속층16: 제 1 에치 배리어 박막15: upper barrier metal layer 16: first etch barrier thin film
17: 제 1 절연막18: 제 2 에치 배리어 박막17: first insulating film 18: second etch barrier thin film
19: 제 2 절연막20: 제 1 포토레지스트 패턴19: second insulating film 20: first photoresist pattern
21: 홀 패턴22: 제 2 포토레지스트 패턴21: hole pattern 22: second photoresist pattern
23: 비아홀 패턴24: 금속 배선용 홀 패턴23: Via hole pattern 24: Hole pattern for metal wiring
25: 배리어 금속층26A: 비아홀 배선25: barrier metal layer 26A: via hole wiring
26B: 상부 금속 배선26B: Top metal wiring
본 발명의 반도체 소자의 금속 배선 형성 방법은 하부 금속 배선이 형성된 층간 절연막상에 하부 금속 배선 부분이 개방된 제 1 에치 배리어 박막을 형성하는 단계; 상기 제 1 에치 배리어 박막을 포함한 전체 구조상에 제 1 절연막, 제 2 에치 배리어 박막 및 제 2 절연막을 순차적으로 형성하는 단계; 상기 제 2 절연막 및 제 2 에치 배리어 박막의 일부분을 제거하여 비아홀 패턴이 형성될 부분에 대응되는 홀 패턴을 형성하는 단계; 홀 패턴 아래의 제 1 절연막을 제거하여 비아홀 패턴을 형성함과 동시에 제 2 절연막의 일부분을 제거하여 금속 배선용 홀 패턴을 형성하는 단계; 및 상기 비아홀 패턴 및 금속 배선용 홀 패턴에 비아홀 배선 및 상부금속 배선을 형성하는 단계를 포함하여 이루어진다.A method of forming a metal wiring of a semiconductor device according to the present invention may include forming a first etch barrier thin film on which an lower metal wiring portion is opened on an interlayer insulating film on which a lower metal wiring is formed; Sequentially forming a first insulating film, a second etch barrier thin film, and a second insulating film on the entire structure including the first etch barrier thin film; Removing a portion of the second insulating layer and the second etch barrier thin film to form a hole pattern corresponding to a portion where a via hole pattern is to be formed; Removing the first insulating layer under the hole pattern to form a via hole pattern and simultaneously removing a portion of the second insulating layer to form a hole pattern for metal wiring; And forming a via hole wiring and an upper metal wiring in the via hole pattern and the metal wiring hole pattern.
상기에서, 비아홀 패턴 형성시에 홀 패턴 주변의 제 2 에치 배리어 박막은 자기 정렬 마스크 역할을 하며, 금속 배선용 홀 패턴 형성시에 제 2 에치 배리어 박막은 제 1 절연막을 보호하는 식각 방지 역할을 한다.In the above description, when forming the via hole pattern, the second etch barrier thin film around the hole pattern serves as a self-aligning mask, and when forming the hole pattern for metal wiring, the second etch barrier thin film serves as an etching prevention role to protect the first insulating layer.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11)상에 층간 절연막(12)을 형성한다. 층간 절연막(12)에 측부 배리어 절연층(13) 및 상부 배리어 금속층(15)으로 둘러싸인 하부 금속 배선(14)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a substrate 11 on which various elements for forming a semiconductor device are formed. The lower metal wiring 14 surrounded by the side barrier insulating layer 13 and the upper barrier metal layer 15 is formed in the interlayer insulating film 12.
상기에서, 측부 배리어 절연층(13)은 SiON, Al2O3, SiOF, 플라즈마 질화막(PENITRIDE) 등으로 형성하고, 하부 금속 배선(14)은 구리(Cu), 알루미늄(Al), 텅스텐(W), 폴리실리콘, 금속 폴리사이드 등으로 형성한다.In the above, the side barrier insulating layer 13 is formed of SiON, Al 2 O 3 , SiOF, plasma nitride film (PENITRIDE) or the like, and the lower metal wiring 14 is copper (Cu), aluminum (Al), tungsten (W). ), Polysilicon, metal polysides and the like.
도 1b를 참조하면, 하부 금속 배선(14)이 형성된 층간 절연막(12)상에 하부 금속 배선(14) 부분이 개방된 제 1 에치 배리어 박막(16)을 형성하고, 제 1 절연막(17), 제 2 에치 배리어 박막(18) 및 제 2 절연막(19)을 순차적으로 형성한다.Referring to FIG. 1B, the first etch barrier thin film 16 having the lower metal wiring 14 portion open is formed on the interlayer insulating film 12 on which the lower metal wiring 14 is formed, and the first insulating film 17, The second etch barrier thin film 18 and the second insulating film 19 are sequentially formed.
상기에서, 제 1 및 제 2 에치 배리어 박막(16 및 18)은 SiON, Al2O3, SiOF, 플라즈마 질화막 등으로 형성하고, 제 1 절연막(17)은 BPSG, SOG, TEOS, 플라즈마 산화막(PEOXIDE) 등으로 형성하며, 제 2 절연막(19)은 SiOF, HSOP, PTFE, HSQ, Flare와 같이 낮은 유전 상수값을 갖는 물질로 형성한다.In the above, the first and second etch barrier thin films 16 and 18 are formed of SiON, Al 2 O 3 , SiOF, plasma nitride film, and the like, and the first insulating film 17 is formed of BPSG, SOG, TEOS, and plasma oxide film (PEOXIDE). The second insulating film 19 is formed of a material having a low dielectric constant such as SiOF, HSOP, PTFE, HSQ, and Flare.
도 1c를 참조하면, 비아홀 패턴이 형성될 부분이 개방된 제 1 포토레지스트 패턴(20)을 제 2 절연막(19)상에 형성하고, 식각 공정을 통해 제 2 절연막(19) 및 제 2 에치 배리어 박막(18)을 제거하여 작은 크기의 홀 패턴(21)을 형성한다.Referring to FIG. 1C, the first photoresist pattern 20 having the portion where the via hole pattern is to be formed is formed on the second insulating layer 19, and the second insulating layer 19 and the second etch barrier are etched through an etching process. The thin film 18 is removed to form a hole pattern 21 having a small size.
도 1d를 참조하면, 제 1 포토레지스트 패턴(20)을 제거한 후, 비아홀 패턴이 형성될 부분과 상부 금속 배선이 형성될 부분이 개방된 제 2 포토레지스트 패턴(22)을 제 2 절연막(19)상에 형성하고, 자기 정렬 다마신 공정 기법을 이용한 식각 공정을 통해 홀 패턴(21)의 부분에 노출된 제 1 절연막(17) 및 상부 배리어 금속층(15)을 제거하여 하부 금속 배선(14)이 저면을 이루는 비아홀 패턴(23)을 형성하고, 비아홀 패턴(23)을 형성하기 위한 식각 공정 동안 상부 금속 배선이 형성될 부분의 제 2 절연막(19)이 제거되어 금속 배선용 홀 패턴(24)이 형성된다.Referring to FIG. 1D, after removing the first photoresist pattern 20, the second insulating layer 19 may include the second photoresist pattern 22 having the portion where the via hole pattern will be formed and the portion where the upper metal wiring will be formed. The lower metal interconnection 14 is formed by removing the first insulating layer 17 and the upper barrier metal layer 15 that are formed on the upper surface of the hole pattern 21 through an etching process using a self-aligned damascene process technique. The via hole pattern 23 forming the bottom surface is formed, and the second insulating layer 19 of the portion where the upper metal wiring is to be formed is removed during the etching process for forming the via hole pattern 23 to form the hole pattern 24 for the metal wiring. do.
상기에서, 비아홀 패턴(23) 형성시에 홀 패턴(21) 주변의 제 2 에치 배리어 박막(18)은 자기 정렬 마스크 역할을 하며, 금속 배선용 홀 패턴(24) 형성시에 제 2 에치 배리어 박막(18)은 제 1 절연막(17)을 보호하는 식각 방지 역할을 한다.In the above description, when the via hole pattern 23 is formed, the second etch barrier thin film 18 around the hole pattern 21 serves as a self-alignment mask, and when the hole pattern 24 for metal wiring is formed, the second etch barrier thin film ( 18 serves to prevent etching to protect the first insulating layer 17.
도 1e를 참조하면, 비아홀 패턴(23) 및 금속 배선용 홀 패턴(24) 각각에 배리어 금속층(25)을 형성한 후, 배선용 금속으로 채워 비아홀 배선(26A) 및 다양한역할이 가능한 상부 금속 배선(26B)을 형성한다.Referring to FIG. 1E, the barrier metal layer 25 is formed in each of the via hole pattern 23 and the metal wiring hole pattern 24, and then filled with the metal for wiring to form the via hole wiring 26A and the upper metal wiring 26B capable of various roles. ).
상기에서, 비아홀 배선(26A) 및 상부 금속 배선(26B)은 구리를 사용하여 형성하며, 구리 이외에 WN, TaN, TiW, CrN, Al, AlSi, Ag, Au, Pt 등을 사용하여 형성할 수 있다.In the above, the via hole wiring 26A and the upper metal wiring 26B are formed using copper, and may be formed using WN, TaN, TiW, CrN, Al, AlSi, Ag, Au, Pt, etc. in addition to copper. .
상술한 바와 같이, 본 발명은 자기 정렬 다마신 공정 기법으로 비아홀 콘택을 형성할 때 동시에 금속 배선용 홀 패턴을 형성하므로, 비아홀 배선 및 다양한 역할이 가능한 금속 배선을 효과적으로 형성할 수 있다.As described above, when the via hole contact is formed by the self-aligned damascene process technique, the hole pattern for the metal wiring is formed at the same time, so that the via hole wiring and the metal wiring capable of various roles can be effectively formed.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0084733A KR100368320B1 (en) | 2000-12-28 | 2000-12-28 | Method of manufacturing a metal wiring in a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0084733A KR100368320B1 (en) | 2000-12-28 | 2000-12-28 | Method of manufacturing a metal wiring in a semiconductor device |
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| Publication Number | Publication Date |
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| KR20020055309A true KR20020055309A (en) | 2002-07-08 |
| KR100368320B1 KR100368320B1 (en) | 2003-01-24 |
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| KR10-2000-0084733A KR100368320B1 (en) | 2000-12-28 | 2000-12-28 | Method of manufacturing a metal wiring in a semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7084056B2 (en) | 2003-07-01 | 2006-08-01 | Samsung Electronics Co., Ltd. | Electrical interconnection, method of forming the electrical interconnection, image sensor having the electrical interconnection and method of manufacturing the image sensor |
| KR100701426B1 (en) * | 2005-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Multi layer metal in semiconductor device and method for manufacturing the same |
| CN113811988A (en) * | 2019-05-01 | 2021-12-17 | 应用材料公司 | Full alignment erase process and electronic device from the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
| KR0144913B1 (en) * | 1995-03-03 | 1998-08-17 | 김광호 | Method of forming metal connection layer |
| GB2325083B (en) * | 1997-05-09 | 1999-04-14 | United Microelectronics Corp | A dual damascene process |
| KR100280288B1 (en) * | 1999-02-04 | 2001-01-15 | 윤종용 | Method for fabricating capacitor of semiconcuctor integrated circuit |
| JP2000232106A (en) * | 1999-02-10 | 2000-08-22 | Tokyo Electron Ltd | Semiconductor device and manufacture of semiconductor device |
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2000
- 2000-12-28 KR KR10-2000-0084733A patent/KR100368320B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7084056B2 (en) | 2003-07-01 | 2006-08-01 | Samsung Electronics Co., Ltd. | Electrical interconnection, method of forming the electrical interconnection, image sensor having the electrical interconnection and method of manufacturing the image sensor |
| KR100701426B1 (en) * | 2005-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Multi layer metal in semiconductor device and method for manufacturing the same |
| CN113811988A (en) * | 2019-05-01 | 2021-12-17 | 应用材料公司 | Full alignment erase process and electronic device from the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100368320B1 (en) | 2003-01-24 |
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