KR20080062025A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
KR20080062025A
KR20080062025A KR1020060137281A KR20060137281A KR20080062025A KR 20080062025 A KR20080062025 A KR 20080062025A KR 1020060137281 A KR1020060137281 A KR 1020060137281A KR 20060137281 A KR20060137281 A KR 20060137281A KR 20080062025 A KR20080062025 A KR 20080062025A
Authority
KR
South Korea
Prior art keywords
layer
pmd
etching
contact hole
etch stop
Prior art date
Application number
KR1020060137281A
Other languages
Korean (ko)
Other versions
KR100859474B1 (en
Inventor
황상일
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020060137281A priority Critical patent/KR100859474B1/en
Publication of KR20080062025A publication Critical patent/KR20080062025A/en
Application granted granted Critical
Publication of KR100859474B1 publication Critical patent/KR100859474B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor device is provided to implement stable self aligned contact hole by using a TaN with high selectivity to an oxide layer instead of SiN used as a etch stopp layer. A gate electrode(210) including a spacer is formed on a semiconductor substrate(200). An etch stopp layer(230) is formed on the semiconductor substrate. A negative photoresist layer is coated on the etch stop layer. A contact mask pattern defining a contact hole is formed on the negative photoresist layer. The negative photoresist layer is patterned by using a contact mask pattern. The etch stopp layer is etched by using the patterned negative photoresist layer. An ashing and cleaning processes are performed to remove the negative photoresist layer. A PMD(premetal dielectric) layer(260) is formed on the substrate, and a contact hole is formed by etching the PMD layer.

Description

반도체 소자의 제조 방법{Method of Manufacturing Semiconductor Device}Method of manufacturing semiconductor device {Method of Manufacturing Semiconductor Device}

도 1은 종래 기술에 따른 반도체 소자의 콘택 홀을 형성하는 과정에서 발생한 게이트 전극의 로스(loss) 문제를 나타낸 단면도. 1 is a cross-sectional view illustrating a loss problem of a gate electrode generated in a process of forming a contact hole of a semiconductor device according to the related art.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 콘택 홀 제조 방법을 설명하기 위한 순차적인 공정 단면도.2A to 2E are sequential cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

200 : 반도체 기판200: semiconductor substrate

210 : 게이트 전극210: gate electrode

220 : 스페이서220: spacer

230 : 식각정지막230: etching stop film

240 : 네거티브 포토레지스트 패턴240: negative photoresist pattern

250 : 콘택 마스크 패턴250: contact mask pattern

260 : PMD층260: PMD layer

본 발명은 반도체 소자의 제조 방법에 관한 것으로. 특히 PMD(Premetal Dielectric) 층에 대해 콘택 홀을 형성하는 과정에서, 식각정지막으로 PMD층과의 선택비가 높은 물질을 사용함으로써 보다 안정된 자기 정렬 콘택 홀을 형성할 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device. In particular, in the process of forming a contact hole for a PMD (Premetal Dielectric) layer, a method of manufacturing a semiconductor device capable of forming a more stable self-aligned contact hole by using a material having a high selectivity with the PMD layer as an etch stop layer will be.

컴퓨터나 텔레비전과 같은 전자 제품은 다이오드나 트랜지스터 등의 반도체 소자가 포함되며, 이러한 반도체 소자는 산화실리콘을 성장시켜 만든 웨이퍼에 막을 형성하고, 막의 필요한 부분에 불순물 이온을 주입하여 전기적으로 활성화시킨 후, 이들을 전기적으로 배선하는 일련의 과정을 통하여 제조된다. Electronic products such as computers and televisions include semiconductor devices such as diodes and transistors. Such semiconductor devices form a film on a wafer made by growing silicon oxide, inject impurity ions into a required portion of the film, and then electrically activate it. It is manufactured through a series of processes for electrically wiring them.

한편, 반도체 소자의 고집적화 경향에 따라 하나의 금속 배선만으로 반도체 소자의 작동이 어려워져 다층 구조로 된 반도체 소자가 개발되었으며, 이러한 다층 구조에 있어서는 전도층과 전도층 사이에 절연을 위한 층간절연막이 형성되고 적층된 전도층을 전기적으로 연결시켜 주기 위하여 층간절연막에 콘택 홀을 형성하고 전도체로 매립하는 별도의 콘택 공정이 필요하다. On the other hand, according to the tendency of high integration of semiconductor devices, it is difficult to operate semiconductor devices with only one metal wiring, and thus a semiconductor device having a multilayer structure has been developed. In such a multilayer structure, an interlayer insulating film for insulation is formed between a conductive layer and a conductive layer. In order to electrically connect the stacked conductive layers, a separate contact process is required in which a contact hole is formed in the interlayer insulating layer and is filled with a conductor.

또한, 다층의 금속 배선에서 첫 번째 금속 배선(first metal line)을 연결하는 콘택 홀을 형성하기 위한 PMD(Premetal Dielectric)층에 대해 식각하여 콘택 홀을 형성하는 공정은 디자인 룰(design rule)을 막론하고 트랜지스터(transistor)를 포함한 하부 구조물과 상부 금속 배선을 연결하는 콘택을 구비하는 데 중요한 역할을 한다. In addition, the process of forming a contact hole by etching a PMD layer to form a contact hole connecting a first metal line in a multi-layered metal wire is a design rule. And a contact connecting the lower structure including the transistor and the upper metal wiring.

따라서, 반도체 장치가 고집적화됨에 따라 소자의 크기 및 선폭 등의 감소는 필연적인 사항이 되었으며, 이에 따라 미세 선폭의 구현 기술은 반도체 장치 제작에 핵심 기술이 되고 있다. 하지만, 노광 기술을 이용하여 점점 더 얇은 선폭 및 작은 크기의 콘택 홀을 패터닝(patterning)하는데 어려움이 따르는 문제가 있다.Therefore, as semiconductor devices have been highly integrated, reductions in device size and line width have become inevitable. Accordingly, a technology for implementing fine line widths has become a core technology for manufacturing semiconductor devices. However, there is a problem in that it is difficult to pattern an increasingly thin line width and a small contact hole using an exposure technique.

또한, 자기정렬 콘택 홀을 구현하기 위해서는 통상적인 식각정지막으로 실리콘 질화막(SiN)에 대한 산화막(Oxide)으로 이루어진 PMD(Premetal Dielectric)의 높은 선택비가 요구된다. In addition, in order to implement a self-aligned contact hole, a high selectivity ratio of PMD (Premetal Dielectric) composed of an oxide film (Oxide) to a silicon nitride film (SiN) is required as a conventional etch stop film.

하지만, 도 1에 도시된 바와 같이, 선택비가 낮을 경우 다결정 실리콘막으로 이루어진 게이트 전극의 손실 및 스페이서의 손실이 초래되어 디바이스 특성에 악영향을 줄 수 있다.However, as shown in FIG. 1, when the selectivity is low, a loss of a gate electrode and a spacer of a polycrystalline silicon film may be caused, which may adversely affect device characteristics.

전술한 문제를 해결하기 위해 본 발명은, 특히 PMD(Premetal Dielectric) 층에 대해 콘택 홀을 형성하는 과정에서, 식각정지막으로 PMD층과의 선택비가 높은 물질을 사용함으로써 보다 안정된 자기 정렬 콘택 홀을 형성할 수 있는 반도체 소자의 제조 방법을 제공하는데 목적이 있다.In order to solve the above-described problem, the present invention, in the process of forming a contact hole for the PMD (Premetal Dielectric) layer, in particular, by using a material having a high selectivity with the PMD layer as an etch stop layer, a more stable self-aligned contact hole It is an object to provide a method of manufacturing a semiconductor device that can be formed.

전술한 목적을 달성하기 위해 본 발명은, 스페이서를 포함한 게이트 전극이 반도체 기판상에 구비된 상태에서, 상기 게이트 전극이 형성된 반도체 기판 전면에 식각정지막을 형성하는 단계와, 상기 식각정지막 상에 네거티브 포토레지스트막을 도포하는 단계와, 상기 네거티브 포토레지스트막 상에 콘택 홀을 정의하는 콘택 마스크 패턴을 형성하는 단계와, 상기 콘택 마스크 패턴을 이용하여 상기 네거티브 포토레지스트막을 패터닝하는 단계와, 상기 패터닝된 네거티브 포토레지스트막을 이용하여 상기 식각정지막을 식각하는 단계와, 상기 네거티브 포토레지스트막을 제 거하기 위한 애싱 공정과 세정 공정을 수행하는 단계와, 상기 게이트 전극 포함한 상기 기판 전면에 PMD(Premetal Dielectric)층을 형성하고, 상기 PMD층에 대해 식각하여 상기 콘택 홀을 형성하는 단계를 포함하는 반도체 소자의 제조 방법을 제공한다.In order to achieve the above object, the present invention, in a state in which a gate electrode including a spacer is provided on a semiconductor substrate, forming an etch stop layer on the entire surface of the semiconductor substrate on which the gate electrode is formed, and a negative on the etch stop layer Applying a photoresist film, forming a contact mask pattern defining contact holes on the negative photoresist film, patterning the negative photoresist film using the contact mask pattern, and patterning the negative Etching the etch stop layer using a photoresist film, performing an ashing process and a cleaning process to remove the negative photoresist film, and forming a PMD layer on the entire surface of the substrate including the gate electrode And the contact hole is etched with respect to the PMD layer. It provides a method for producing a semiconductor device comprising the step of sex.

본 발명에서, 상기 콘택 홀을 형성하는 단계는, 상기 게이트 전극을 포함한 상기 기판 전면에 BPSG(Boro-phospho Silicate Glass) 또는 PSG(Phosphorus Silicate Glass)계열의 산화막을 이용하여 PMD(Premetal Dielectric)층을 형성하는 단계와, 상기 PMD층 상에 상기 콘택 홀을 정의하는 포지티브 포토레지스트 패턴을 형성하는 단계와, 상기 PMD층에 대해 상기 포지티브 포토레지스트 패턴을 이용하여 식각함으로써 상기 콘택 홀을 형성하는 단계를 포함한다.In the present invention, the forming of the contact hole may include forming a premetal dielectric (PMD) layer using an oxide film of a boro-phospho silicate glass (BPSG) or a phosphorus silica glass (PSG) based on the entire surface of the substrate including the gate electrode. Forming a positive photoresist pattern defining the contact hole on the PMD layer, and forming the contact hole by etching the PMD layer using the positive photoresist pattern. do.

본 발명에서, 상기 식각정지막은 탄탈륨나이트라이드(TaN)을 이용하여 300 ~ 500Å의 두께로 형성한다.In the present invention, the etch stop layer is formed to a thickness of 300 ~ 500Å by using tantalum nitride (TaN).

본 발명에서, 상기 TaN으로 이루어진 식각 정지막의 증착 공정 조건은, 4200 ~ 4800 mTorr의 압력범위로 설정하고, 18000 ~ 22000W의 DC 파워와, 210 ~ 250W의 AC 바이어스 파워를 인가하며, 3 ~ 7 sccm 유량의 Ar 가스를 유입하여 4 ~ 8초 동안의 증착 시간을 갖는다.In the present invention, the deposition process conditions of the etch stop film made of TaN is set to a pressure range of 4200 ~ 4800 mTorr, applying a DC power of 18000 ~ 22000W, AC bias power of 210 ~ 250W, 3 ~ 7 sccm The Ar gas at the flow rate was introduced to have a deposition time of 4 to 8 seconds.

본 발명에서, 상기 네커티브 포토레지스트막은 4000 ~ 5000Å의 두께로 형성한다.In the present invention, the negative photoresist film is formed to a thickness of 4000 ~ 5000Å.

본 발명에서, 상기 식각정지막의 식각 공정 조건은 7 ~ 9 mTorr의 압력 범위로 설정하고, 900 ~ 1100W의 소스 파워(source power)와 90 ~ 110W의 바이어스 파 워(bias power)를 인가하며, 50 ~ 100 sccm 유량의 Cl2 기체, 50 ~ 100 sccm 유량의 BCl3 기체 및 30 ~ 60 sccm 유량의 Ar 기체를 유입하여 10 ~ 20초 동안의 식각 시간을 갖는다.In the present invention, the etching process conditions of the etch stop film is set to a pressure range of 7 ~ 9 mTorr, a source power of 900 ~ 1100W and a bias power of 90 ~ 110W is applied, 50 The etching time is 10 to 20 seconds by introducing Cl 2 gas at a flow rate of ~ 100 sccm, BCl 3 gas at a flow rate of 50 to 100 sccm, and Ar gas at a flow rate of 30 to 60 sccm.

본 발명에서, 상기 PMD층은 5500 ~ 6500Å의 두께로 형성한다.In the present invention, the PMD layer is formed to a thickness of 5500 ~ 6500Å.

본 발명에서, 상기 PMD층을 식각하는 과정에서, 상기 PMD층과 상기 식각정지막은 10 ~ 15 : 1 비율의 식각비를 갖는다.In the present invention, in the process of etching the PMD layer, the PMD layer and the etch stop layer has an etching ratio of 10 ~ 15: 1 ratio.

이하에서는 첨부한 도면을 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 자세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

본 발명이 속하는 기술 분야에 익히 알려져 있고 본 발명과 직접적으로 관련이 없는 기술 내용에 대해서는 설명을 생략한다. 이는 불필요한 설명을 생략함으로써 본 발명의 요지를 흐리지 않고 더욱 명확히 전달하기 위함이다.Descriptions of technical contents that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

먼저, 도 2a에 도시된 바와 같이, 스페이서(220)를 포함한 게이트 전극(210)이 반도체 기판(200)상에 구비된 상태에서, 게이트 전극(210)이 형성된 반도체 기판(200) 전면에 식각정지막(230)을 형성한다. 이때, 식각정지막(230)은 탄탈륨나이트라이드(TaN)을 이용하여 300 ~ 500Å의 두께로 증착한다. 여기서, TaN으로 이루어진 식각정지막(230)의 증착 공정 조건은 다음과 같다.First, as shown in FIG. 2A, in the state where the gate electrode 210 including the spacer 220 is provided on the semiconductor substrate 200, an etch stop is formed on the entire surface of the semiconductor substrate 200 on which the gate electrode 210 is formed. A film 230 is formed. At this time, the etch stop film 230 is deposited to a thickness of 300 ~ 500Å by using tantalum nitride (TaN). Here, the deposition process conditions of the etch stop film 230 made of TaN is as follows.

즉, 4200 ~ 4800 mTorr의 압력범위로 설정하고, 18000 ~ 22000W의 DC 파워와, 210 ~ 250W의 AC 바이어스 파워를 인가하며, 3 ~ 7 sccm 유량의 Ar 가스를 유입하여 4 ~ 8초 동안의 증착 시간을 갖는 것이 적합하다.In other words, it is set in the pressure range of 4200 ~ 4800 mTorr, applying DC power of 18000 ~ 22000W, AC bias power of 210 ~ 250W, deposition for 4 ~ 8 seconds by introducing Ar gas at a flow rate of 3 ~ 7 sccm It is appropriate to have time.

전술한 바와 같이, 이러한 탄탈륨나이트라이드(TaN)으로 이루어진 금속의 식각정지막(230)은 종래의 식각정지막으로 사용했었던 실리콘 질화막(SiN)에 비해 산화막에 대한 식각 선택비가 높기 때문에 후속의 PMD층에 대한 콘택 홀 식각시, 보다 안정되게 자기정렬 콘택을 구현할 수 있을 뿐만 아니라, 확산 방지막으로도 뛰어나며 전도성이 크기 때문에 종래보다 우수하며 안정된 자기정렬 콘택을 구현할 수 있다.As described above, the metal etch stop layer 230 made of tantalum nitride (TaN) has a higher etching selectivity for the oxide film than the silicon nitride film (SiN) used as a conventional etch stop layer, and thus the subsequent PMD layer. When the contact hole is etched, the self-aligned contact can be more stably implemented. Also, the self-aligned contact is superior to the conventional one because it is excellent as a diffusion barrier and has high conductivity.

다음으로, 도 2b에 도시된 바와 같이, 식각정지막(230) 상에 네거티브 포토레지스트막(negative photoresist)(240)을 4000 ~ 5000Å의 두께로 도포한 후, 네거티브 포토레지스트막(240) 상에 콘택 홀을 정의하는 콘택 마스크 패턴(250)을 형성한다.Next, as shown in FIG. 2B, a negative photoresist 240 is applied on the etch stop layer 230 to a thickness of 4000 to 5000 GPa, and then onto the negative photoresist layer 240. A contact mask pattern 250 defining a contact hole is formed.

다음으로, 도 2c에 도시된 바와 같이, 콘택 홀을 정의하는 콘택 마스크 패턴(250)을 이용하여 네거티브 포토레지스트막(240)에 대해 패터닝한다. Next, as shown in FIG. 2C, the negative photoresist layer 240 is patterned using the contact mask pattern 250 defining the contact hole.

이어서, 콘택 마스크 패턴을 제거한 후, 패터닝된 네거티브 포토레지스트막을 이용하여 TaN으로 이루어진 식각정지막(230)을 식각한다. 여기서, 식각정지막(230)의 식각 공정 조건은 다음과 같다.Subsequently, after removing the contact mask pattern, the etch stop layer 230 made of TaN is etched using the patterned negative photoresist layer. Here, the etching process conditions of the etch stop film 230 are as follows.

즉, 7 ~ 9 mTorr의 압력 범위로 설정하고, 900 ~ 1100W의 소스 파워(source power)와 90 ~ 110W의 바이어스 파워(bias power)를 인가하며, 50 ~ 100 sccm 유량의 Cl2 기체, 50 ~ 100 sccm 유량의 BCl3 기체 및 30 ~ 60 sccm 유량의 Ar 기체를 유입하여 10 ~ 20초 동안의 식각 시간을 갖는 것이 적합하다.That is, it is set in the pressure range of 7 to 9 mTorr, applying a source power of 900 ~ 1100W and a bias power of 90 ~ 110W, Cl 2 gas of 50 ~ 100 sccm flow rate, 50 ~ It is suitable to have an etching time of 10 to 20 seconds by introducing BCl 3 gas at a flow rate of 100 sccm and Ar gas at a flow rate of 30 to 60 sccm.

따라서, 콘택 홀이 형성될 영역 예컨대, 적층된 전도층을 전기적으로 연결시켜 주기 위한 영역 예를 들어, 게이트 전극(210) 상부 또는, 소스 및 드레인 접합층(미도시)의 상부 등의 도전층 상에 TaN 금속의 식각정지막(230)이 남도록 한다.Therefore, the area where the contact hole is to be formed, for example, the area for electrically connecting the stacked conductive layers, for example, on the gate electrode 210 or on the conductive layer such as on the source and drain junction layer (not shown). The etch stop layer 230 of the TaN metal remains on the substrate.

그 후, 도 2d에 도시된 바와 같이, 네거티브 포토레지스트막(240)을 제거하기 위한 애싱(ashing) 공정과 소정의 세정 공정을 수행할 수 있다.Thereafter, as illustrated in FIG. 2D, an ashing process and a predetermined cleaning process for removing the negative photoresist film 240 may be performed.

다음으로, 도 2e에 도시된 바와 같이, 게이트 전극(210)을 포함한 기판(200) 전면에 PMD(Premetal Dielectric)층(260)을 형성하고 PMD층(260)에 대해 식각하여 전술한 바와 같은, 콘택 홀을 형성한다. 구체적으로, 게이트 전극(210)을 포함한 기판(200) 전면에 PMD(Premetal Dielectric)층(260)을 5500 ~ 6500Å의 두께로 형성한다. 이때, PMD층(260)을 형성하는 물질은 BPSG(Boro-phospho Silicate Glass) 또는 PSG(Phosphorus Silicate Glass)계열의 산화막을 이용할 수 있다. Next, as shown in FIG. 2E, a PMD (Premetal Dielectric) layer 260 is formed on the entire surface of the substrate 200 including the gate electrode 210 and etched with respect to the PMD layer 260. Form a contact hole. Specifically, a PMD (Premetal Dielectric) layer 260 is formed on the entire surface of the substrate 200 including the gate electrode 210 to a thickness of 5500 ~ 6500Å. In this case, the material forming the PMD layer 260 may use an oxide film of BPSG (Boro-phospho Silicate Glass) or PSG (Phosphorus Silicate Glass).

이어서, PMD층(260) 상에 콘택 홀을 정의하는 포지티브 포토레지스트 패턴(미도시)을 형성하고, 이러한 포지티브 포토레지스트 패턴을 이용하여 PMD층(260)에 대해 식각함으로써 콘택 홀을 형성할 수 있다. 이때, 산화막으로 이루어진 PMD층(260)과 금속의 TaN막으로 이루어진 식각정지막(230)은 10 ~ 15 : 1 비율의 식각비를 갖으며 식각될 수 있다. 즉, 콘택 홀을 형성하기 위한 PMD층(260)의 식각시, 식각정지막으로 기존의 식각정지막으로 사용했었던 실리콘 질화막(SiN) 대신 산화막에 대한 식각 선택비가 높은 TaN을 사용함으로써 보다 안정된 자기정렬 콘택 홀을 구현할 수 있을 뿐 아니라, 확산 방지막의 기능도 뛰어나며 전도성이 우수한 장점이 있다.Subsequently, a positive photoresist pattern (not shown) defining a contact hole may be formed on the PMD layer 260, and the contact hole may be formed by etching the PMD layer 260 using the positive photoresist pattern. . In this case, the PMD layer 260 made of an oxide film and the etching stop film 230 made of a metal TaN film may be etched with an etching ratio of 10 to 15: 1. That is, when etching the PMD layer 260 to form the contact hole, the self-alignment is more stable by using TaN, which has a high etching selectivity for the oxide film, instead of the silicon nitride film (SiN), which was used as an etch stop film. Not only the contact hole can be realized, but also the diffusion barrier is excellent and the conductivity is excellent.

지금까지 본 발명의 구체적인 구현예를 도면을 참조로 설명하였지만 이것은 본 발명이 속하는 기술분야에서 평균적 지식을 가진 자가 쉽게 이해할 수 있도록 하기 위한 것이고 발명의 기술적 범위를 제한하기 위한 것이 아니다. 따라서 본 발명의 기술적 범위는 특허청구범위에 기재된 사항에 의하여 정하여지며, 도면을 참조로 설명한 구현예는 본 발명의 기술적 사상과 범위 내에서 얼마든지 변형하거나 수정할 수 있다. Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention.

이상에서 설명한 바와 같이 본 발명에 의하면, PMD층에 대해 콘택 홀을 형성하기 위하여 식각하는 과정에서, 기존의 식각정지막으로 사용했었던 실리콘 질화막(SiN) 대신 산화막에 대한 식각 선택비가 높은 탄탈륨 나이트라이드(TaN)를 사용함으로써 보다 안정된 자기정렬 콘택 홀을 구현할 수 있다. 또한, 확산 방지막의 기능도 뛰어나며 전도성이 우수한 장점이 있어 공정의 신뢰성이 크게 향상될 수 있다.As described above, according to the present invention, in the process of etching to form a contact hole in the PMD layer, tantalum nitride having a high etching selectivity with respect to the oxide film instead of the silicon nitride film (SiN) used as the conventional etching stop film ( By using TaN), more stable self-aligned contact holes can be realized. In addition, the function of the diffusion barrier is also excellent and has the advantage of excellent conductivity can greatly improve the reliability of the process.

Claims (8)

스페이서를 포함한 게이트 전극이 반도체 기판상에 구비된 상태에서,In a state where a gate electrode including a spacer is provided on a semiconductor substrate, 상기 게이트 전극이 형성된 반도체 기판 전면에 식각정지막을 형성하는 단계와,Forming an etch stop layer on the entire surface of the semiconductor substrate on which the gate electrode is formed; 상기 식각정지막 상에 네거티브 포토레지스트막을 도포하는 단계와,Applying a negative photoresist film on the etch stop film; 상기 네거티브 포토레지스트막 상에 콘택 홀을 정의하는 콘택 마스크 패턴을 형성하는 단계와,Forming a contact mask pattern defining a contact hole on the negative photoresist film; 상기 콘택 마스크 패턴을 이용하여 상기 네거티브 포토레지스트막을 패터닝하는 단계와,Patterning the negative photoresist film using the contact mask pattern; 상기 패터닝된 네거티브 포토레지스트막을 이용하여 상기 식각정지막을 식각하는 단계와,Etching the etch stop layer by using the patterned negative photoresist layer; 상기 네거티브 포토레지스트막을 제거하기 위한 애싱 공정과 세정 공정을 수행하는 단계와,Performing an ashing process and a cleaning process for removing the negative photoresist film; 상기 게이트 전극 포함한 상기 기판 전면에 PMD(Premetal Dielectric)층을 형성하고, 상기 PMD층에 대해 식각하여 상기 콘택 홀을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.Forming a contact hole by forming a premetal dielectric (PMD) layer on the entire surface of the substrate including the gate electrode and etching the PMD layer. 제 1 항에 있어서,The method of claim 1, 상기 콘택 홀을 형성하는 단계는,Forming the contact hole, 상기 게이트 전극을 포함한 상기 기판 전면에 BPSG(Boro-phospho Silicate Glass) 또는 PSG(Phosphorus Silicate Glass)계열의 산화막을 이용하여 PMD(Premetal Dielectric)층을 형성하는 단계와,Forming a premetal dielectric (PMD) layer on the entire surface of the substrate including the gate electrode by using an oxide film of BPSG (Phosphorus Silicate Glass) or PSG (Phosphorus Silicate Glass) series; 상기 PMD층 상에 상기 콘택 홀을 정의하는 포지티브 포토레지스트 패턴을 형성하는 단계와,Forming a positive photoresist pattern defining the contact hole on the PMD layer; 상기 PMD층에 대해 상기 포지티브 포토레지스트 패턴을 이용하여 식각함으로써 상기 콘택 홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.And forming the contact hole by etching the PMD layer by using the positive photoresist pattern. 제 1 항에 있어서,The method of claim 1, 상기 식각정지막은 탄탈륨나이트라이드(TaN)을 이용하여 300 ~ 500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The etch stop layer is formed using a tantalum nitride (TaN) to a thickness of 300 ~ 500Å, the manufacturing method of a semiconductor device. 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 TaN으로 이루어진 식각 정지막의 증착 공정 조건은, 4200 ~ 4800 mTorr의 압력범위로 설정하고, 18000 ~ 22000W의 DC 파워와, 210 ~ 250W의 AC 바이어스 파워를 인가하며, 3 ~ 7 sccm 유량의 Ar 가스를 유입하여 4 ~ 8초 동안의 증착 시간을 갖는 것을 특징으로 하는 반도체 소자의 제조 방법.Deposition process conditions of the etch stop film made of TaN is set to a pressure range of 4200 ~ 4800 mTorr, applying a DC power of 18000 ~ 22000W, AC bias power of 210 ~ 250W, Ar gas at a flow rate of 3 to 7 sccm Method of manufacturing a semiconductor device, characterized in that having a deposition time for 4 to 8 seconds by introducing a. 제 1 항에 있어서,The method of claim 1, 상기 네커티브 포토레지스트막은 4000 ~ 5000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The negative photoresist film is a semiconductor device manufacturing method, characterized in that formed to a thickness of 4000 ~ 5000 ~. 제 1 항에 있어서,The method of claim 1, 상기 식각정지막의 식각 공정 조건은 7 ~ 9 mTorr의 압력 범위로 설정하고, 900 ~ 1100W의 소스 파워(source power)와 90 ~ 110W의 바이어스 파워(bias power)를 인가하며, 50 ~ 100 sccm 유량의 Cl2 기체, 50 ~ 100 sccm 유량의 BCl3 기체 및 30 ~ 60 sccm 유량의 Ar 기체를 유입하여 10 ~ 20초 동안의 식각 시간을 갖는 것을 특징으로 하는 반도체 소자의 제조 방법.The etching process condition of the etch stop layer is set to a pressure range of 7 ~ 9 mTorr, applying a source power of 900 ~ 1100W and a bias power of 90 ~ 110W, the flow rate of 50 ~ 100 sccm A method of manufacturing a semiconductor device, characterized by having an etching time for 10 to 20 seconds by introducing Cl 2 gas, BCl 3 gas at a flow rate of 50 to 100 sccm, and Ar gas at a flow rate of 30 to 60 sccm. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 PMD층은 5500 ~ 6500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The PMD layer is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 5500 ~ 6500Å. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 PMD층을 식각하는 과정에서, 상기 PMD층과 상기 식각정지막은 10 ~ 15 : 1 비율의 식각비를 갖는 것을 특징으로 하는 반도체 소자의 제조 방법.And etching the PMD layer, wherein the PMD layer and the etch stop layer have an etching ratio of 10 to 15: 1.
KR1020060137281A 2006-12-29 2006-12-29 Method of Manufacturing Semiconductor Device KR100859474B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060137281A KR100859474B1 (en) 2006-12-29 2006-12-29 Method of Manufacturing Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060137281A KR100859474B1 (en) 2006-12-29 2006-12-29 Method of Manufacturing Semiconductor Device

Publications (2)

Publication Number Publication Date
KR20080062025A true KR20080062025A (en) 2008-07-03
KR100859474B1 KR100859474B1 (en) 2008-09-24

Family

ID=39814208

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060137281A KR100859474B1 (en) 2006-12-29 2006-12-29 Method of Manufacturing Semiconductor Device

Country Status (1)

Country Link
KR (1) KR100859474B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517810B (en) * 2013-09-30 2019-08-20 三星电子株式会社 The method for forming semiconductor pattern and semiconductor layer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040063352A (en) * 2003-01-07 2004-07-14 삼성전자주식회사 Method of forming semiconductor devices
KR100489657B1 (en) * 2003-02-21 2005-05-17 삼성전자주식회사 Method for forming patterns in a semiconductor device and method for a semiconductor device using the same

Also Published As

Publication number Publication date
KR100859474B1 (en) 2008-09-24

Similar Documents

Publication Publication Date Title
US7772112B2 (en) Method of manufacturing a semiconductor device
KR100297966B1 (en) Process for forming multilevel interconnection structure
US6413438B1 (en) Method of forming via hole by dry etching
KR20030058853A (en) Method for Forming of Semiconductor Device
KR100859474B1 (en) Method of Manufacturing Semiconductor Device
KR100778869B1 (en) Method for forming contact of semiconductor device
KR100604920B1 (en) Method for manufacturing semiconductor device having dual plug
CN103165515B (en) Manufacture method of semiconductor device
CN109300847B (en) Semiconductor structure and forming method thereof
KR100876532B1 (en) Manufacturing Method of Semiconductor Device
KR20010059540A (en) Method for forming metal line of semiconductor device
KR100588665B1 (en) Method for fabricating barrier metal of semiconductor device
US20210050258A1 (en) Semiconductor structure and formation method thereof
KR100307968B1 (en) Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly
KR20100076548A (en) Method for forming semiconductor device
KR20010048350A (en) Method for fabricating a semiconductor device
KR100808369B1 (en) Method of manufacturing a semiconductor device
KR100349346B1 (en) Method of defining a wire pattern in a semiconductor device
KR100702798B1 (en) Method of fabricating semiconductor device
KR100815940B1 (en) Smiconductor device and method for forming the same
KR100591838B1 (en) Method for forming inter-layer connection of semiconductor device
KR20030056917A (en) Method for manufacturing of capacitor of semiconductor device
KR100831572B1 (en) Method of forming metal line for semiconductor device
TW201505125A (en) Metal interconnect structure and process thereof
KR20040058907A (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110809

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee