KR20040063352A - Method of forming semiconductor devices - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device is provided to reduce a short-circuit phenomenon between a gate electrode and a contact by prevent an etch stop layer covering a substrate from being eliminated while forming a deep contact hole in a core region and a peripheral region in a process for forming a bitline contact hole. CONSTITUTION: A transistor structure is formed in a substrate(1), including a gate whose upper part and sidewall are surrounded by a silicon nitride layer. A bitline contact pad in contact with a drain region in a cell region is formed. An interlayer dielectric is formed on the substrate having the bitline contact pad. The interlayer dielectric is patterned to form a bitline contact hole exposing the bitline contact pad in the cell region. A contact hole exposing an active region covered with an etch stop layer(17) formed of a silicon nitride layer is formed in the core region and the peripheral region. An exposure process is performed to form a photoresist pattern(39) that covers the cell region and exposes the core region and the peripheral region. The etch stop layer on the bottom of the contact hole in the core and peripheral regions is removed by using the photoresist pattern as an etch mask. By using the photoresist pattern as an ion implantation mask, Impurity ions are implanted into the bottom of the contact hole from which the etch stop layer is removed.

Description

Method of forming semiconductor devices

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a bit line contact in a memory semiconductor device having a cell region and a core and ferry region.

As the device integration of semiconductor devices increases, the area occupied by each region of individual devices is decreasing. On the other hand, compared with the semiconductor element area, the formation height thereof does not decrease significantly, so the aspect ratio of contact holes and the like is increased. When it is difficult to form a deep contact hole or the like at a precise location in a narrow area, self-aligned contact pads are first formed in active regions between densely formed gates, and contact plugs are formed on the pads to form overall contacts. It is becoming common.

1 and 2 are cross-sectional views illustrating a process of forming a bit line contact plug after a MOS transistor structure is formed in a DRAM semiconductor device having a capacitor over bit line (COB) structure in a cell region and a core or peripheral region.

Referring to FIG. 1, the problem of the prior art is first described. First, device isolation is performed on the substrate 1 to form a MOS transistor having a gate and a source / drain in an active region and a core region of a cell. In this case, the gate electrode 13 is formed by depositing a gate conductive film on the gate insulating film 11, forming a protective silicon nitride film 15 thereon, forming a gate pattern through a patterning operation, and forming a silicon nitride film on the sidewall of the gate pattern. The spacer 19 is formed and completed. Meanwhile, before or after the spacer 19 is formed, a thin silicon nitride film is normally stacked as an etch stop layer 17 on the entire surface of the substrate so that the active region is covered with the etch stop layer 17.

After the transistor structure is formed, a first interlayer insulating film is formed over the entire substrate 1 and planarized. In the planarization, the protective silicon nitride film 15 or the etch stop film 17 on the gate electrode usually serves as a blocking film. In the cell region, a patterning operation is performed to form a pad hole by removing the first interlayer insulating layer and the etch stop layer 17 from the source / drain regions of each cell, and the patterning operation is performed by an exposure and etching process. A conductive film such as polysilicon is stacked on the substrate, and device isolation is performed to form a bit line contact pad 21 and a storage node contact pad 21 filling a pad hole.

The bit line contact hole 25 exposing the bit line contact pad 21 is formed in the cell area by stacking the second interlayer insulating layer 23 over the formed pads 21 and patterning. On the other hand, in the core region, a contact hole 27 is formed in the source / drain region of the transistor at this time.

According to FIG. 2, a bit line contact hole 25 is formed in a cell region, a deep contact hole 27 is formed in a source / drain region in a peripheral region, and the cell region is covered using an exposure process. The exposed photoresist pattern 29 is formed. Then, high concentration impurity ions are implanted into the exposed core / drain regions to reduce contact interface resistance.

However, according to the related art, the source / drain region of the substrate of the core region is covered with the etch stop layer 17 in the forming of the bit line contact, unlike the cell region. The etch stop layer 17 functions to protect the substrate in the process of making the deep contact hole 27 in the core region, but requires the process of removing the etch stop layer 17 itself to complete the contact hole 27. do.

Since the etch stop layer 17 is formed of a silicon nitride layer, the protective silicon nitride layer 15 or the sidewall spacers of the upper gate line exposed to the pad 21 in the cell region in the process of removing the etch stop layer 17 from the core region. 19) is a problem that is damaged. As the size of each structure and the thickness of each structure become smaller in the highly integrated semiconductor device, even a small damage to the film quality can cause serious problems of the semiconductor device, and an upper protective silicon nitride film that protects the gate during the core region etch stop film removal process. Damage to the silicon nitride film 15 or the side spacers 19 is likely to cause a short circuit between the gate electrode 13 and the contact plug.

The present invention is to solve the above-mentioned problems of the prior art, it is easy to form a deep contact hole in the core or peripheral region while preventing damage to the upper protective layer and sidewall spacer of the gate line in the cell region when forming the bit line contact hole without additional process burden It is an object to provide a method of manufacturing a semiconductor device to be formed.

1 and 2 are cross-sectional views illustrating a process of forming a bit line contact plug after a MOS transistor structure is formed in a DRAM semiconductor device having a capacitor over bit line (COB) structure in a cell region and a core or peripheral region,

3 through 6 are cross-sectional views illustrating a process of forming a bit line contact plug in a cell region and a core region after a MOS transistor structure is formed in a DRAM semiconductor device having a capacitor over bit line (COB) structure according to the present invention.

According to an aspect of the present invention, there is provided a transistor structure including a gate structure having a top and sidewalls of a silicon nitride film on a substrate, forming a bitline contact pad in contact with a drain region in a cell region, and a bitline contact pad. Forming an interlayer insulating layer over the substrate on which the silicon oxide film is formed; forming a bit line contact hole exposing the bit line contact pads in the cell region through the interlayer insulating layer patterning, and forming an active region covered with silicon nitride film Forming an exposed contact hole, forming a photoresist pattern covering a cell area and exposing a core or peripheral area through an exposure process, and etching the photoresist pattern with an etching mask in the core or peripheral area using the photoresist pattern as an etching mask Removing the blocking film; In the ion implantation mask is achieved by having the step of performing impurity ion implantation on a bottom of the contact hole to remove said etch stop film.

After implanting impurity ions in the present invention, a process of forming a bit line contact plug and a core or contact plug in a peripheral region is performed by separating a device and a conductive film stack such as polysilicon as usual.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 through 6 are cross-sectional views illustrating a process of forming a bit line contact plug in a DRAM semiconductor device having a capacitor over bit line (COB) structure after a MOS transistor structure is formed in a cell region and a core region.

Referring to FIG. 3, device separation is first performed on the substrate 1 as in the prior art. The gate insulating film 11 is formed in the active region and the core region of the cell, and the gate conductive film and the gate protection silicon nitride film 15 are laminated. Through patterning, a gate pattern is formed using the gate electrode 13 and the protective silicon nitride layer 15, and the etch stop layer 17 is formed by stacking the silicon nitride layer 10 to 500 angstroms thick on the entire surface of the substrate. The spacers 19 are formed on the sidewalls of the gate patterns through the silicon nitride film stack and the etch back. Impurity ion implantation is performed before and after formation of the spacers 19 to form source / drain regions of the MOS transistors. This forms a MOS transistor with a gate and source / drain on the substrate. An etch stop layer 17 may be stacked after the sidewall spacers 19 are formed in the gate pattern.

After the transistor structure is formed, a first interlayer insulating film is formed over the entire substrate 1 and planarized. In planarization, the protective silicon nitride film 15 on the gate electrode usually serves as a blocking film. In the cell region, a patterning operation is performed to form a pad hole by removing the first interlayer insulating layer and the etch stop layer 17 from the source / drain regions of each cell, and the patterning operation is performed by an exposure and etching process. A conductive film such as polysilicon is stacked on the substrate, and device isolation is performed to form a bit line contact pad 21 and a storage node contact pad 21 filling a pad hole.

The second interlayer insulating film 23 is stacked on the formed pads 21. The interlayer insulating layers may be made of a high density plasma (HDP) silicon oxide film, an undoped silicate glass (USG), a plasma enhansed tetraethylorthosilicate (PE-TEOS), a phosphorous silicate glass (PSG), a spin on glass (SOG), or the like. The bit line contact hole 35 exposing the bit line contact pad 21 is formed in the cell region through the patterning operation on the interlayer insulating layer 23. On the other hand, in the core region, a contact hole 37 is formed in the source / drain region of the transistor at this time. A gate electrode covered with a silicon nitride film may be exposed on the bottom of the bit line contact hole 35 along with the pad 21, and an etch stop layer 17 may appear on the bottom of the contact hole in the core region.

Referring to FIG. 4, a photoresist pattern 39 is formed to cover the cell region and expose the core region by using an exposure process in a state in which a bit line contact hole is formed in the cell region and a deep contact hole 37 is formed in the core region. do. The silicon nitride film is etched using the photoresist pattern 39 as an etching mask. In this case, since the cell region is covered and protected by the photoresist pattern 39, the protective silicon nitride layer 15 or the sidewall spacer 19 on the gate is not damaged and the etch stop layer 17 of the core region is removed by etching. Contact holes 37 'are formed. In this case, in addition to the anisotropic dry etching, the etching stop layer 17 may be wet-etched by a phosphoric acid solution.

Referring to FIG. 5, a high concentration of impurity ions are implanted using the photoresist pattern 39 used as an etch mask as an ion implantation mask while the etch stop layer 17 of the core region is removed. Therefore, a highly doped impurity doped region is formed in the bottom substrate 1 of the contact hole 37 'in the core region, and the interface resistance with the contact to be formed in the future can be reduced.

Referring to Fig. 6, the photoresist pattern 39 is removed from the process substrate on which the ion implantation is performed, and a conductive film such as polysilicon is laminated. Therefore, the bit line contact hole in the cell region and the deep contact hole in the core region are filled with a conductive film. The conductive film stacked on the upper surface of the second interlayer insulating film 23 is removed through planarization etching by anisotropic etching or CMP, and only the contact plugs 135 and 137 remain in the contact hole. The process then proceeds as usual, followed by the formation of conductive lines that connect the contacts and subsequent formation of storage node contacts and cell capacitors.

According to the present invention, since the etch stop layer covering the substrate is not removed while the deep contact hole is formed in the region around the core in the process of forming the bit line contact hole, the gate protection silicon nitride layer and the gate sidewall spacer are damaged by damaging the gate. The risk of generating a short between the electrode and the contact can be reduced. In addition, since the etch stop layer of the core around the core is removed using a photoresist pattern formed on the bottom of the contact hole in the core around the hole, a separate exposure process is not required.

Claims (1)

Forming a transistor structure on the substrate, the transistor structure having a gate overlying the sidewalls with a silicon nitride film, Forming a bit line contact pad in contact with the drain region in the cell region, Forming an interlayer insulating film on the substrate on which the bit line contact pad is formed; Forming a bit line contact hole exposing the bit line contact pad in the cell region through patterning the interlayer insulating layer, and forming a contact hole exposing an active region covered with a silicon nitride etch stop layer in a core or a peripheral region , Forming a photoresist pattern covering the cell region and exposing the core or peripheral region through an exposure process; Removing the etch stop layer on the bottom surface of the contact hole from the core or a peripheral area using the photoresist pattern as an etch mask; And implanting impurity ions into the bottom of the contact hole from which the etch stop layer is removed using the photoresist pattern as an ion implantation mask.