KR20060108432A - Dram device and methodp of forming the same - Google Patents

Abstract

The present invention relates to a DRAM device and a method of forming the same. By forming a spacer covering a sidewall of a bitline structure to an upper portion of a bitline contact pad, a short circuit and a bitline contact pad can be prevented from occurring when a storage contact plug is formed. The reliability of the DRAM device can be improved.

DRAM, Bitline Contact Pads, Storage Contact Plugs, Spacers

Description

DRAM DEVICE AND METHODP OF FORMING THE SAME

1 is a cross-sectional view taken along the line II ′ of FIG. 2 for explaining the prior art;

2 is a diagram illustrating a layout of a DRAM device;

3 to 8 are cross-sectional views taken along the line II ′ of FIG. 2 for explaining a method of forming a DRAM device according to an embodiment of the present invention;

9 and 10 are cross-sectional views taken along the line II ′ of FIG. 2 for explaining a modified example of the embodiment of the present invention.

♧ explanation of symbols for main parts of drawing

10, 100: semiconductor substrate 12, 120: device isolation film

14, 140: drain region 16, 160: source region

18, 180: first interlayer insulating film 20, 200: bit line contact pads

22, 220: storage contact pads 24, 240: second interlayer insulating film

26, 260: barrier metal film pattern 28, 280: bit line contact plug

30, 300: bit line pattern 32, 320: hard mask pattern

33, 330: bit line structure 34, 340: spacer

360: third interlayer insulating film 38, 380: storage contact plug

AR: Active area BL: Bit line

WL: Wordline DC: Bitline Contact Plug

BC: Storage Contact Pads

The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a DRAM device and a method of forming the same.

Due to the high integration of semiconductor devices, design rules are continuously decreasing. Decreased design rules mean that the area occupied by unit memory cells in the semiconductor device is reduced. In particular, a DRAM having a 6F² structure is vulnerable to shorting between the storage contact plug and the bitline contact pad because of a lack of a misalignment margin of the storage contact plug to the bitline contact pad. It will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view taken along the line II ′ of FIG. 2 for explaining the prior art. However, illustration of the capacitor located on the storage contact plug is omitted.

An isolation region 12 is formed on the semiconductor substrate 10 to define an active region (not shown). A plurality of word lines parallel to each other (not shown) are formed on the semiconductor substrate. An ion implantation process is performed using the word line as an ion implantation mask to form an impurity doped region, that is, a source region 16 and a drain region 14 in the active region. A first interlayer insulating film 18 is formed on the entire surface of the semiconductor substrate 10 on which the word line is formed. A planarization process is performed on the first interlayer insulating film 18. Certain portions of the first interlayer dielectric layer 18 between the word lines are etched to form contact holes (not shown), and to fill and planarize conductive materials to form bit line contact pads 20 and storage contact pads 22. do. In this case, the bit line contact pad 20 is in contact with the drain region 14, and the storage contact pad is in contact with the source region 16. A second interlayer insulating film 24 is formed on the entire surface of the resultant semiconductor substrate on which the contact pads are formed. The upper surface of the second interlayer insulating film 24 is planarized. The second interlayer insulating layer 24 is patterned to form bit line contact holes (not shown) that expose a center portion of the upper surface of the bit line contact pad 20.

A barrier metal layer, a conductive layer, and a hard mask are sequentially formed on an entire surface of the semiconductor substrate formed with the bit line contact holes. A photo process and an etching process are performed on the entire surface of the semiconductor substrate on which the barrier metal layer, the conductive layer, and the hard mask are formed to expose the upper portion of the bit line structure and the second interlayer insulating layer 24. The barrier metal layer pattern 26 is formed in a concave-convex shape surrounding the lower portion of the bit line contact plug 28. Subsequently, a spacer 34 is formed on the upper sidewall of the bit line structure 33. A third interlayer insulating film (not shown) is formed on the entire surface of the semiconductor substrate product on which the spacers 34 are formed. The third interlayer insulating layer and the second interlayer insulating layer are patterned to form a storage contact hole (not shown) that exposes the spacer 34, the first interlayer insulating layer 18, and the storage contact pad 22. Subsequently, a conductive material, for example, doped polysilicon or the like is deposited in the storage contact hole to form a storage contact plug 38.

Problems in the structure of the DRAM device formed by the prior art are as follows. Since the space between the bit line contact pad 20 and the storage contact pad 22 is very small, the misalignment margin of the storage contact plug formed on the storage contact pad 22 is insufficient. Thus, a short may occur between the storage contact plug 38 and the bitline contact pad 20 as shown in the circle at both ends of the upper portion of the bitline contact pad of FIG. 1.

An object of the present invention is to provide a DRAM device having a high reliability and a method of forming the same by preventing a short circuit between a storage contact plug and a bit line contact pad in a DRAM device, in particular, a DRAM having a 6F² structure.

The DRAM device according to the present invention for achieving the above technical problem is a semiconductor substrate; A first interlayer insulating film covering the semiconductor substrate; A bit line contact pad and a storage contact pad penetrating the first interlayer insulating layer to contact the semiconductor substrate; A second interlayer insulating layer covering the first interlayer insulating layer, the bit line contact pads, and the storage contact pads; A bit line structure formed on the bit line contact pad through the second interlayer insulating film; A spacer covering a sidewall of the bitline structure and an upper surface of the bitline contact pad; A third interlayer insulating film covering the spacer and the second interlayer insulating film; And a storage contact plug penetrating the second interlayer insulating layer and the third interlayer insulating layer to contact the storage contact pad.

Accordingly, in the DRAM device according to the present invention, the spacer covers both ends of the upper portion of the bit line contact pad to prevent a short circuit between the storage contact plug and the bit line contact pad, thereby improving reliability of the DRAM device. Can be improved.

In the DRAM device, the spacer may be formed of a material having a high etching selectivity with respect to the second interlayer insulating layer and the third interlayer insulating layer.

According to an aspect of the present invention, there is provided a method of forming a DRAM device comprising: forming a first interlayer insulating film on a semiconductor substrate; Forming a bit line contact pad and a storage contact pad penetrating the first interlayer insulating layer to be in contact with the semiconductor substrate; Forming a second interlayer dielectric layer on the first interlayer dielectric layer, the bit line contact pads and the storage contact pads; Patterning the second interlayer insulating layer to form a bit line contact hole exposing the bit line contact pad; Forming a bitline structure on the exposed bitline contact pads; Forming a spacer covering a sidewall of the bitline structure and an upper surface of the bitline contact pad; Forming a third interlayer insulating film covering the spacer and the second interlayer insulating film; Patterning the third interlayer insulating film and the second interlayer insulating film to form a storage contact hole exposing the storage contact pad and the first interlayer insulating film; And filling the storage contact hole with a conductive material to form a storage contact plug.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or semiconductor substrate, it may be formed directly on the other layer or semiconductor substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

2 is a diagram illustrating a general layout of a DRAM having a 6F² structure.

3 to 8 are cross-sectional views taken along the line II ′ of FIG. 2 for explaining a method of forming a DRAM device according to an exemplary embodiment of the present invention.

2 and 3, an isolation region 120 is formed on a semiconductor substrate 100 to define an active region AR. The device isolation layer 120 may be formed by a shallow trench isolation (STI) method. Although not shown in FIG. 3, a plurality of word lines WL parallel to each other are formed on the semiconductor substrate 100. The word line WL may be formed to include a gate insulating layer, a gate electrode, a capping layer pattern, and a spacer covering sidewalls, which are sequentially stacked. An ion implantation process is performed using the word line WL as an ion implantation mask to form an impurity doping region, that is, a source region 160 and a drain region 140 in the active region AR. A first interlayer insulating layer 180 is formed on the entire surface of the semiconductor substrate 100 on which the word line WL is formed. A planarization process is performed on the first interlayer insulating layer 180. In this case, a capping layer, which is an upper surface of the word line WL, may be exposed. Certain portions of the first interlayer dielectric layer 180 between the word lines WL are etched to form contact holes (not shown), fill and planarize conductive materials to form the bit line contact pads 200 and the storage contact pads BC. 220. In this case, the bit line contact pad 200 is in contact with the drain region 140, and the storage contact pads BC 220 are in contact with the source region 160. In addition, the contact pads 200 and 220 may be formed by a method of forming a self align contact (SAC). A second interlayer insulating layer 240 is formed on the entire surface of the resultant semiconductor substrate on which the contact pads 200 and 220 are formed. The upper surface of the second interlayer insulating film 240 is planarized. The second interlayer insulating layer 240 is patterned to form a bit line contact hole 280h exposing a center portion of an upper surface of the bit line contact pad 200.

Referring to FIG. 4, the barrier metal layer 250, the conductive layer 270, and the hard mask 310 are sequentially formed on the entire surface of the semiconductor substrate on which the bit line contact holes are formed.

Referring to FIG. 5, a hard mask pattern 320, a bit line pattern 300, and a bit may be formed by performing a photo process and an etching process on the entire surface of the semiconductor substrate on which the barrier metal layer, the conductive layer, and the hard mask are formed. The line contact plug 280 and the barrier metal film pattern 265 are formed. In this case, the second interlayer insulating layer 240 is exposed. The barrier metal layer pattern 265 is formed in a concave-convex shape surrounding a lower portion of the bit line contact plug 280.

Referring to FIG. 6, a barrier metal film interposed between the bit line contact plug 280 and the second interlayer insulating film 240 is formed by further performing an etching process after forming the resultant of the semiconductor substrate shown in FIG. 5. Etch it. In this case, a portion of the second interlayer insulating layer 240 in contact with the barrier metal layer to be etched is also etched to form both ends of the upper portion of the bit line contact pad 200 at the bit line structure 330 and the second layer. The interlayer insulating film 240 is exposed. At this time, a new barrier metal film pattern 260 is formed. Accordingly, the bit line structure 330 formed of a stacked structure of the barrier metal film pattern 260, the bit line contact plug 280, the bit line pattern 300, and the hard mask pattern 320 may be formed in the bit line structure. It is formed on the contact pad 200. The bit line structure 330 is formed to be insulated from the second interlayer insulating layer 240. The barrier metal layer pattern 260 under the bit line structure 330 is formed only under the bit line contact plug 280 unlike the shape of the barrier metal layer pattern shown in FIG. 5 (reference numeral 265 of FIG. 5). do.

Referring to FIG. 7, spacers 340 are formed on sidewalls of the bit line structure 330. A third interlayer dielectric layer 360 is formed to cover the spacer 340 and the second interlayer dielectric layer 240. The spacer 340 is formed of a material having a higher etching selectivity, for example, silicon nitride, etc., than the second interlayer insulating film 240 and the third interlayer insulating film 360, which are typically formed of silicon oxide. Accordingly, in the conventional forming process, the barrier metal film and the second interlayer insulating film cover both ends of the upper portion of the bit line contact pad, whereas the spacer 340 covers the sidewalls of the upper portion of the bit line structure 330 according to the present invention. A lower portion of the bit line structure 330 covers both ends of the upper portion of the bit line contact pad 200.

Referring to FIG. 8, the third interlayer insulating layer 360 and the second interlayer insulating layer 240 are patterned to expose the spacer 340, the first interlayer insulating layer 180, and the storage contact pad 220. To form a storage contact hole (not shown). A conductive material, for example, doped polysilicon or the like, is deposited in the storage contact hole to form a storage contact plug 380.

Therefore, the structure of the DRAM device formed by the present invention is different from that of the DRAM device formed by the prior art described in FIG. Referring back to FIG. 8, unlike the circle shown in FIG. 1, since the spacer 340 covers both ends of the upper portion of the bit line contact pad 200, the bit line contact pad 200 and the storage device are covered with each other. A short circuit does not occur between the contact plugs 380.

9 and 10 are cross-sectional views taken along the line II ′ of FIG. 2 for explaining a modified example of changing the height of the bit line contact holes in the embodiment of the present invention.

Referring to FIG. 9, the process up to forming the second interlayer insulating film 240 is the same as the above embodiment. In the subsequent process, when the second interlayer insulating layer 240 is patterned to form the bit line contact hole 280h, a portion of the upper portion of the bit line contact pad 200 is etched together, unlike in the above embodiment, the bit line contact pad ( The thickness of 200 decreases, and the height of the bitline contact hole 280h increases.

After the process is carried out in the same manner as the embodiment shown in Figures 4 to 8 to form the structure shown in FIG. Referring to FIG. 10, the height of the lower portion of the spacer 340 and the height of the bitline contact plug 280 are increased by the thickness of the bitline contact pad 200 etched and removed. However, unlike the prior art, since the lower portion of the spacer 340 is formed to prevent a short circuit between the bit line contact pad 200 and the storage contact plug 380, the lower bit line has a lower height than the lower portion of the spacer 340. It is not necessary to form up to the contact pad 200. The bottom surface of the lower portion of the spacer 340 only needs to be present between the bottom surface of the storage contact plug 380 and the top surface of the bit line contact pad 200. Therefore, it can be implemented in various modifications.

In addition, the above-described embodiment can be modified in various ways without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, according to the present invention, a spacer covering the sidewalls of the bitline structure is formed by extending the bitline contact pads so that the bitline contact pads and the storage contacts due to the lack of misalignment margin in the DRAM device, in particular, a DRAM device having a 6F² structure. Short circuit between the plugs can be prevented to improve the reliability of the DRAM device.

Claims (6)

Semiconductor substrates; A first interlayer insulating film covering the semiconductor substrate; A bit line contact pad and a storage contact pad penetrating the first interlayer insulating layer to contact the semiconductor substrate; A second interlayer insulating layer covering the first interlayer insulating layer, the bit line contact pads, and the storage contact pads; A bit line structure formed on the bit line contact pad through the second interlayer insulating film; A spacer covering a sidewall of the bitline structure and an upper surface of the bitline contact pad; A third interlayer insulating film covering the spacer and the second interlayer insulating film; And And a storage contact plug penetrating the second interlayer insulating layer and the third interlayer insulating layer to contact the storage contact pad. The method of claim 1, And the bit line contact pad is smaller than a thickness of the first interlayer insulating layer. The method according to claim 1 or 2, And the bit line structure comprises a stacked structure of a barrier metal layer, a bit line contact plug, a bit line pattern, and a hard mask pattern. The method according to claim 1 or 2, And the spacer is formed of a material having an etch selectivity with respect to the second interlayer insulating layer and the third interlayer insulating layer. Forming a first interlayer insulating film on the semiconductor substrate; Forming a bit line contact pad and a storage contact pad penetrating the first interlayer insulating layer to be in contact with the semiconductor substrate; Forming a second interlayer dielectric layer on the first interlayer dielectric layer, the bit line contact pads and the storage contact pads; Patterning the second interlayer insulating layer to form a bit line contact hole exposing the bit line contact pad; Forming a bitline structure on the exposed bitline contact pads; Forming a spacer covering a sidewall of the bitline structure and an upper surface of the bitline contact pad; Forming a third interlayer insulating film covering the spacer and the second interlayer insulating film; Patterning the third interlayer insulating film and the second interlayer insulating film to form a storage contact hole exposing the storage contact pad and the first interlayer insulating film; And And filling the storage contact hole with a conductive material to form a storage contact plug. The method of claim 5, Forming the bit line contact hole; Patterning the second interlayer insulating film to expose a bit line contact pad, and And etching a portion of an upper portion of the bit line contact pad.

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