KR20010048350A - Method for fabricating a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce capacitance of a parasitic capacitor formed between a bit line and a contact plug or between the bit lines, by forming a spacer of the bit line wherein the spacer has a structure of an oxide layer/a nitride layer or a nitride layer/an oxide layer/a nitride layer. CONSTITUTION: A bit line(206) is formed on a semiconductor substrate. The first insulating layer(208) is deposited on the entire surface of the semiconductor substrate to cap the bit line. The second insulating layer(210) is deposited on the first insulating layer to cap the bit line. The third insulating layer(212) is deposited on the entire surface of the semiconductor substrate to form a contact plug(216) between the bit lines.

Description

Method of manufacturing semiconductor device {METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductors, and more particularly, to a method of manufacturing a semiconductor device for forming a spacer in a bit line.

As semiconductor devices become more and more integrated, the size of the required device pattern is gradually decreasing. Therefore, the area where the capacitor is to be formed is reduced, making it difficult to secure the capacity of the capacitor. On the other hand, as the density of the device pattern increases, the spacing between adjacent lines decreases, thereby increasing the parasitic capacitor.

In particular, as the design rule becomes smaller and smaller, the photolitho-graphy process does not form a contact properly due to the proximity effect, and does not form an independent contact by adjoining adjacent contacts. Therefore, in order to solve such a problem, a large pattern itself is formed and a self-aligned contact (SAC) is formed to contact by using a photoresist film and a gate line as an etching mask.

Looking at the structure of the gate line in the process of forming a self-aligned contact, the gate line is a polysilicon and tungsten silicide stack structure, the spacer is formed on the sidewall of the gate line. The conductive material is filled between the spacers to form the contact pads. In this type of structure, the spacer on the sidewall of the gate line acts as a dielectric material to form a parasitic capacitor consisting of the gate line, the contact pad, the contact pad, and the gate line. The capacitance of the parasitic capacitor is dependent on the thickness and dielectric constant of the gate spacer. However, as the material for forming the spacer of the gate line, a nitride film having an etch selectivity with an oxide layer is used in forming a self-aligned contact. In addition, since the nitride film has a high dielectric constant, the thickness of the gate spacer needs to be increased to reduce the capacitance of the parasitic capacitor. However, when the thickness of the spacer is increased, the width between the gate lines is narrowed. When the width between the gate lines is reduced, voids are generated between the gate lines in the subsequent interlayer insulating film formation, thereby causing mutual interference between adjacent cells.

1 is a cross-sectional view showing a conventional method for forming a semiconductor device.

Referring to FIG. 1, a contact pad 2 is formed on a semiconductor substrate. A first insulating film 4 is deposited on the contact pad 2. The bit line 8 is formed on the first insulating film 4. A silicon nitride film 8 is deposited and gapped on the bit line 6. A second insulating film 10 is deposited on the silicon nitride film 8. The second insulating film 10 is etched through the photolithography process so that the silicon nitride film 8 between the bit lines 6 is exposed. The silicon nitride film 8 between the bit lines 6 is etched. The first insulating film 4 is etched to expose the contact pad 2 using the silicon nitride film 8 on the sidewall of the bit line 6 as a mask. As a result, a contact hole is formed between the bit lines 6. Since the contact hole is filled with a conductive film to form a contact plug 12, a self alignment contact (SAC) is performed.

As such, when the contact plug 12 is drawn between the bit lines 6, a parasitic capacitor is formed between the bit line 6 and the contact plug 12. This is because the silicon nitride film 8 capping the bit line 6 serves as a dielectric film and the bit line 6 and the contact plug 12 serve as upper and lower electrodes of the capacitor.

The present invention has been proposed to solve the above-mentioned problems, and provides a method of manufacturing a semiconductor device capable of reducing the capacitance of the parasitic capacitor generated between the bit line and the contact plug formed between the bit line and the bit line. The purpose is.

1 is a cross-sectional view showing the structure of a conventional semiconductor device;

2A to 2D are cross-sectional views sequentially showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention;

3A through 3E are cross-sectional views sequentially illustrating a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

202 and 302: contact pads 204 and 304: first insulating film

206, 306: bit line 208, 310: oxide film

210, 308: first silicon nitride film 312: second silicon nitride film

212 and 314: second insulating film 214 and 316: photoresist film

216, 318: Contact Plug

According to the present invention for achieving the above object, a bit line is formed on a semiconductor substrate. A first insulating film is deposited on the entire surface of the semiconductor substrate to cap the bit line. The bit line is capped by depositing a second insulating film on the first insulating film. After depositing a third insulating film on the entire surface of the semiconductor substrate, a contact plug is formed between the bit lines.

In a preferred embodiment, before depositing the first insulating film, a fourth insulating film is first deposited to cap the bit line.

In a preferred embodiment, the second insulating film and the fourth insulating film are silicon nitride films.

In a preferred embodiment, the first insulating film is an oxide film.

(First embodiment)

Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2D.

The present invention can reduce the capacitance of the parasitic capacitor generated between the bit line and the contact plug formed between the bit line and the bit line by gapping the bit line in the order of oxide-nitride.

2A through 2D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 2A, a contact pad 202 is formed on a semiconductor substrate. The first insulating layer 204 is deposited on the contact pad 202. The first insulating layer 204 is formed of boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), spin on glass (SOG), high density plasma (HDP) oxide, or the like. The bit line 206 is formed on the first insulating layer 204. The bit line 206 is formed of a structure in which polysilicon, doped poly-Si, or polysilicon and a metal silicide are stacked. An oxide film 208 is deposited on the bit line 206 so that the bit line 206 is capped. The oxide film 208 is formed of Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS), USG, or HDP oxide film. The oxide film 208 has a lower dielectric constant than silicon nitride film. The dielectric constant of silicon nitride is about 7.5, while the dielectric constant of HDP oxide is 3.9, the dielectric constant of PE-TEOS is 4.6, and the dielectric constant of USG is 4.6.

Referring to FIG. 2B, a first silicon nitride layer 210 is deposited on the oxide layer 208 to cap the bit line 206. A second insulating film 212 is deposited on the first silicon nitride film 210. The second insulating film 212 is formed of BPSG, USG, SOG, and HDP oxide film. As such, when a double dielectric film is formed using a dielectric film having a low dielectric constant, the capacitance of the parasitic capacitor may be reduced.

Referring to FIG. 2C, a photoresist film 214 is formed on the second insulating film 212. The photoresist film 214 is patterned to form a contact hole forming pattern. Using the photoresist pattern as a mask, the second insulating film, the first silicon nitride film, the oxide film, and the first insulating film 212, 210, 208, and 204 are etched until the contact pad 202 is exposed. As a result, contact holes are formed between the bit lines 206.

Referring to FIG. 2D, since the contact hole is filled with a conductive film, a contact plug 216 is formed. The conductive film is formed of polysilicon, doped polysilicon, metal or metal silicide, or the like.

(Second embodiment)

Hereinafter, a second embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3E.

The present invention can reduce the capacitance of the parasitic capacitor generated between the bit line and the contact plug formed between the bit line and the bit line by gapping the bit line in the order of nitride film-oxide film-nitride film.

3A through 3E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 3A, a contact pad 302 is formed on a semiconductor substrate. The first insulating layer 304 is deposited on the contact pad 302. The first insulating film 304 is formed of BPSG, USG, SOG, and HDP oxide film. The bit line 306 is formed on the first insulating layer 304. The bit line 306 is formed of a structure in which polysilicon, doped polysilicon, or polysilicon and metal silicide are stacked. Since the first silicon nitride layer 308 is deposited on the bit line 306, the bit line 306 is capped.

Referring to FIG. 3B, the bit line 306 is capped because an oxide layer 310 is deposited on the first silicon nitride layer 208. The oxide film 310 is formed of a PE-TEOS, USG, HDP oxide film or the like.

Referring to FIG. 3C, a second silicon nitride layer 312 is deposited on the oxide layer 310 to cap the bit line 306. The oxide film 314 has a lower dielectric constant than that of the silicon nitride film. The dielectric constant of silicon nitride is about 7.5, while the dielectric constant of HDP oxide is 3.9, the dielectric constant of PE-TEOS is 4.6, and the dielectric constant of USG is 4.6. A second insulating film is deposited on the second silicon nitride film. The second insulating film is formed of BPSG, USG, SOG, and HDP oxide film. As such, when a triple dielectric film is formed using a dielectric film having a low dielectric constant, the capacitance of the parasitic capacitor may be reduced.

Referring to FIG. 3D, a photoresist film 316 is formed on the second insulating film 314. The photoresist film 316 is patterned to form a contact hole forming pattern. Using the photoresist pattern as a mask, the second insulating film, the second silicon nitride film, the oxide film, the first silicon nitride film, and the first insulating film 314, 312, 310, 308, and 304 until the contact pad 302 is exposed. ) Is etched. As a result, contact holes are formed between the bit lines 306.

Referring to FIG. 3E, since the contact hole is filled with a conductive film, a contact plug 318 is formed. The conductive film is formed of polysilicon, doped polysilicon, metal or metal silicide, or the like.

According to the present invention, since the spacer of the bit line is formed in an oxide-nitride film or nitride-oxide-nitride film structure, the capacitance of the parasitic capacitor generated between the bit line and the contact plug formed therebetween or between the bit line and the bit line can be reduced. It works.

Claims (3)

Forming bit lines (206, 306) on the semiconductor substrates (200, 300); Capping the bit lines (206. 306) by depositing a first insulating film (208, 310) over the semiconductor substrate (200, 300); Capping the bit lines (206, 306) by depositing a second insulating film (210, 312) on the first insulating film (208, 310); And Manufacturing a semiconductor plug including forming contact plugs 216 and 318 between the bit lines 206 and 306 after depositing third insulating films 212 and 314 on the entire surface of the semiconductor substrates 200 and 300. Way. The method of claim 1, And depositing a fourth insulating film (308) first to cap the bit lines (206, 306) before depositing the first insulating film (208, 310). The method according to claim 1 or 2, And the first insulating film (208, 310) is formed of an oxide film, and the second insulating film (210, 312) and the fourth insulating film (308) are formed of a nitride film.