KR20010061598A - A method for forming a self aligned contact of semiconductor device - Google Patents

A method for forming a self aligned contact of semiconductor device Download PDF

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Publication number
KR20010061598A
KR20010061598A KR1019990064094A KR19990064094A KR20010061598A KR 20010061598 A KR20010061598 A KR 20010061598A KR 1019990064094 A KR1019990064094 A KR 1019990064094A KR 19990064094 A KR19990064094 A KR 19990064094A KR 20010061598 A KR20010061598 A KR 20010061598A
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South Korea
Prior art keywords
forming
contact
self
etching
contact hole
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KR1019990064094A
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Korean (ko)
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김영수
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990064094A priority Critical patent/KR20010061598A/en
Publication of KR20010061598A publication Critical patent/KR20010061598A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

PURPOSE: A method of forming a self-aligned contact is to form another etch stop layer at both sidewall of a contact hole, after performing a contact etching in a self-alined manner, thereby improving insulating properties of a semiconductor device. CONSTITUTION: A conductive layer and the first etch stop layer are deposited on a semiconductor substrate(31) in this order, and are patterned using a photolithography process to form a conductive pattern. The second etch stop layer is formed on the entire surface and an interlayer dielectric(43) is formed thereon for planarizing the surface. The interlayer dielectric is contact-etched in a self-aligned manner to form a contact hole exposing the substrate. The third etch stop layer spacer(47) is then formed at a sidewall of the contact hole. Thereafter, a bit line contact hole is buried in the contact hole.

Description

반도체소자의 자기정렬적인 콘택 형성방법{A method for forming a self aligned contact of semiconductor device}A method for forming a self aligned contact of semiconductor device

본 발명은 반도체소자의 자기정렬적인 콘택 형성방법에 관한 것으로, 특히 각 층 간의 식각선택비 차이를 이용한 자기정렬적인 콘택 식각공정시 도전층 측벽에 형성되는 절연막이 식각되어 소자의 절연특성이 저하되는 현상을 방지할 수 있는 기술에 관한 것이다.The present invention relates to a method of forming a self-aligned contact of a semiconductor device, and in particular, during the self-aligned contact etching process using the difference in etching selectivity between layers, an insulating film formed on the sidewalls of the conductive layer is etched to lower the insulating properties of the device. The present invention relates to a technology capable of preventing the phenomenon.

최초의 반도체소자는 게이트전극 간의 폭이 넓어 상기 게이트전극과 비트라인 또는 상기 게이트전극과 캐패시터의 단락이 거의 없었다.Since the first semiconductor device has a wide width between the gate electrodes, there is almost no short circuit between the gate electrode and the bit line or the gate electrode and the capacitor.

그러나, 반도체소자가 집적화됨에따라 도전층 간의 단락현상이 발생하여 상기 게이트전극의 측벽에 산화막 스페이서를 형성하였다.However, as semiconductor devices are integrated, a short circuit between conductive layers occurs to form oxide spacers on sidewalls of the gate electrode.

그리고, 반도체소자가 고집적화됨에따라 상기 산화막 스페이서만으로는 상기 게이트전극의 절연을 충분하게 할 수 없게 됨으로써 상기 게이트전극의 사이에 형성되며 측벽에 질화막 스페이서가 형성되는 콘택홀을 자기정렬적으로 형성하게 되었다.As the semiconductor device is highly integrated, insulation of the gate electrode cannot be sufficiently performed with only the oxide film spacer, thereby forming contact holes formed between the gate electrodes and having nitride spacers formed on sidewalls.

이때, 상기 자기정렬적인 콘택홀 형성공정은 산화막 대 질화막의 식각선택비 차이가 15 이상이고, 상기 질화막 대 산화막의 식각선택비 차이가 10 이상으로 구현될 때, 상기 식각선택비 차이를 이용하여 공정을 진행하였다.In this case, the self-aligned contact hole forming process may be performed by using an etching selectivity difference of at least 15 when the etching selectivity difference between the oxide film and the nitride film is greater than 10 and an etching selectivity difference between the nitride film and the oxide film is 10 or more. Proceeded.

그러나, 상기 식각선택비 차이를 구현하기 어려워 실제공정에 적용하기 어렵고, 이로인하여 상기 자기정렬적인 콘택홀 형성공정을 실시하기 어렵게 되었다.However, since it is difficult to implement the difference in etching selectivity, it is difficult to apply to the actual process, thereby making it difficult to perform the self-aligned contact hole forming process.

도 1 은 종래기술에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method for forming a self-aligned contact of a semiconductor device according to the prior art.

먼저, 반도체기판(11) 상부에 반도체소자의 활성영역을 정의하는 소자분리막(13)을 형성한다.First, an isolation layer 13 is formed on the semiconductor substrate 11 to define an active region of the semiconductor device.

이때, 상기 소자분리막(13)은 트렌치형으로 형성한 것이다.In this case, the device isolation layer 13 is formed in a trench type.

그 다음, 상기 반도체기판(11) 상부에 워드라인용 도전층(15)을 형성하고 그 상부에 제1식각장벽층(17)을 형성한다.Next, a word line conductive layer 15 is formed on the semiconductor substrate 11, and a first etch barrier layer 17 is formed thereon.

그리고, 상기 도전층(15)과 제1식각장벽층(17)을 게이트전극 마스크를 이용한 사진식각공정으로 식각하여 패터닝한다.The conductive layer 15 and the first etching barrier layer 17 are etched and patterned by a photolithography process using a gate electrode mask.

이때, 상기 제1식각장벽층(17)은 질화막으로 형성한다.In this case, the first etching barrier layer 17 is formed of a nitride film.

그 다음, 상기 반도체기판(11)에 불순물을 이온주입하여 불순물 접합영역(19)을 형성한다.Then, impurities are implanted into the semiconductor substrate 11 to form the impurity junction region 19.

그리고, 전체표면상부에 제2식각장벽층(21)을 일정두께 형성한다.Then, the second etching barrier layer 21 is formed on the entire surface at a constant thickness.

이때, 상기 제2식각장벽층(21)은 질화막으로 형성한다.In this case, the second etching barrier layer 21 is formed of a nitride film.

그 다음, 상기 전체표면상부를 평탄화시키는 층간절연막(23)을 형성한다. 이때, 상기 층간절연막(23)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 와 같이 유동성이 우수한 절연물질로 형성한다.Then, an interlayer insulating film 23 is formed to planarize the entire upper surface portion. At this time, the interlayer insulating film 23 is made of B.S.G. It is formed of an insulating material with excellent fluidity such as boro phospho silicate glass (hereinafter referred to as BPSG).

그 다음, 콘택마스크(도시안됨)를 이용한 자기정렬적인 콘택식각공정으로 상기 반도체기판(11)의 예정된 부분을 노출시키는 콘택홀(25)을 형성한다.Next, a contact hole 25 is formed to expose a predetermined portion of the semiconductor substrate 11 by a self-aligned contact etching process using a contact mask (not shown).

이때, 상기 자기정렬적인 콘택 식각공정은 상기 층간절연막(23)과 제1,2식각장벽층(21,23) 간의 식각선택비 차이를 이용하여 실시한다.In this case, the self-aligned contact etching process may be performed by using an etching selectivity difference between the interlayer insulating layer 23 and the first and second etching barrier layers 21 and 23.

그러나, 반도체소자가 고집적화되어 상기 도전층(15)의 에스펙트비(aspect ratio)가 크게 되고, 그로 인하여 상기 층간절연막(23)과 제1,2식각장벽층(21,23) 간의 식각선택비를 확보하기가 어렵게 된다.However, the semiconductor device is highly integrated, so that the aspect ratio of the conductive layer 15 is increased, and thus the etching selectivity between the interlayer insulating layer 23 and the first and second etching barrier layers 21 and 23 is increased. It becomes difficult to secure.

그로 인하여, 자기정렬적인 콘택공정시 상기 제1,2식각장벽층(21,23)이 많이 식각되어 상기 도전층(15)의 절연특성을 저하시킨다.Therefore, during the self-aligned contact process, the first and second etching barrier layers 21 and 23 are etched a lot, thereby lowering the insulating characteristics of the conductive layer 15.

상기한 바와같이 종래기술에 따른 반도체소자의 자기정렬적인 콘택 형성방법은, 콘택홀을 도전층으로 매립할때 워드라인용 도전층과 쇼트 ( short ) 되어 반도체소자의 특성을 열화시키는 문제점이 있다.As described above, the self-aligned contact forming method of the semiconductor device according to the related art has a problem in that when the contact hole is filled with the conductive layer, the contact line is shorted with the conductive layer for the word line to deteriorate the characteristics of the semiconductor device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 자기정렬적인 콘택 식각공정후에 콘택홀 측벽에 다른 식각장벽층을 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 자기정렬적인 콘택 방법을 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, after forming the self-aligned contact etching process, another etching barrier layer is formed on the sidewalls of the contact holes, thereby improving the characteristics and reliability of the semiconductor device, and thereby enabling high integration of the semiconductor device. It is an object of the present invention to provide a self-aligned contact method of a semiconductor device.

도 1 은 종래기술에 따른 반도체소자의 자기정렬적인 콘택 형성방법?? 도시한 단며도.1 is a method of forming a self-aligned contact of a semiconductor device according to the prior art ?? Illustrated dangodo.

도 2a 내지 도 2b 는 본 발명의 제1실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도.2A to 2B are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to a first embodiment of the present invention.

도 3a 내지 도 3b 는 본 발명의 제2실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도.3A to 3B are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to a second embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11,31 : 반도체기판 13,33 : 소자분리막11,31: semiconductor substrate 13,33: device isolation film

15,35 : 워드라인용 도전층 17,37,59 : 제1식각장벽층15,35: conductive layer for word line 17,37,59: first etching barrier layer

19,39 : 불순물 접합영역 21,41,61 : 제2식각장벽층19,39 Impurity junction region 21,41,61 Second etching barrier layer

23,43 : 층간절연막 25,45,65 : 콘택홀23,43: interlayer insulating film 25,45,65: contact hole

47,67 : 제3식각장벽층47,67: third etching barrier layer

51 : 제1층간절연막 53 : 저장전극 콘택플러그51: first interlayer insulating film 53: storage electrode contact plug

55 : 제2층간절연막 57 : 비트라인용 도전층55: Second interlayer insulating film 57: Bit line conductive layer

63 : 제3층간절연막 65 : 저장전극 콘택홀63: third interlayer insulating film 65: storage electrode contact hole

13 : 도전층13: conductive layer

15 : 제1마스크산화막 17 : 절연막 스페이서15: first mask oxide film 17: insulating film spacer

19 : 오거닉 로우-케이 21 : 제2마스크산화막19: organic low-K 21: second mask oxide film

23 : 감광막패턴 25 : 언더컷23 photosensitive film pattern 25: undercut

27 : 콘택패드 29 : 층간절연막27: contact pad 29: interlayer insulating film

50 : 제1콘택홀 60 : 제2콘택홀50: first contact hole 60: second contact hole

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은,Self-aligned contact forming method of a semiconductor device according to the present invention to achieve the above object,

반도체기판 상부에 도전층과 제1식각장벽층을 적층하고 이를 노광마스크를 이용하여 사진식각공정으로 패터닝하여 도전배선을 형성하는 공정과,Stacking a conductive layer and a first etching barrier layer on the semiconductor substrate and patterning the conductive layer and the first etching barrier layer by a photolithography process using an exposure mask to form a conductive wiring;

상기 도전배선을 포함한 전체표면상부에 제2식각장벽층을 형성하는 공정과,Forming a second etching barrier layer on the entire surface including the conductive wiring;

전체표면상부를 평탄화시키는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film to planarize the entire upper surface;

상기 층간절연막을 자기정렬적으로 콘택 식각하여 상기 반도체기판을 노출시키는 콘택홀을 형성하는 공정과,Forming a contact hole exposing the semiconductor substrate by performing self-aligned contact etching on the interlayer insulating film;

상기 콘택홀 측벽에 제3식각장벽층 스페이서를 형성하는 공정을 포함하는 공정을 포함하는 것을 특징으로한다.And forming a third etch barrier layer spacer on the sidewalls of the contact hole.

이하, 첨부된 도면을 참고로 하여 본 발명은 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 2b 는 본 발명의 제1실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도로서, 워드라인 사이를 통하여 반도체기판의 예정된 부분을 노출시키는 콘택홀을 형성하는 것을 도시한다.2A and 2B are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to a first embodiment of the present invention, which shows forming contact holes for exposing predetermined portions of a semiconductor substrate through word lines. do.

먼저, 반도체기판(도시안됨)에 반도체소자의 활성영역을 정의하는 소자분리막을 형성한다. 이때, 상기 소자분리막(도시안됨)은 트렌치형으로 형성한 것이다.First, an isolation layer defining an active region of a semiconductor device is formed on a semiconductor substrate (not shown). In this case, the device isolation layer (not shown) is formed in a trench type.

그 다음, 상기 반도체기판 상부에 워드라인용 도전층(도시안됨)을 형성하고, 이를 게이트전극 마스크를 이용한 사진식각공정으로 식각하여 패터닝한다.Next, a word line conductive layer (not shown) is formed on the semiconductor substrate, and the pattern is etched by a photolithography process using a gate electrode mask.

그리고, 전체표면상부를 평탄화시키는 제1층간절연막(51)을 형성한다.Then, the first interlayer insulating film 51 is formed to planarize the entire upper surface portion.

이때, 상기 층간절연막(51)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 와 같이 유동성이 우수한 절연물질로 형성한다.At this time, the interlayer insulating film 51 is made of B.S.G. It is formed of an insulating material with excellent fluidity such as boro phospho silicate glass (hereinafter referred to as BPSG).

그 다음, 콘택마스크(도시안됨)를 이용한 자기정렬적인 콘택식각공정으로 상기 반도체기판의 예정된 부분에 접속되는 저장전극 콘택플러그(53)를 형성한다.Next, a storage electrode contact plug 53 connected to a predetermined portion of the semiconductor substrate is formed by a self-aligned contact etching process using a contact mask (not shown).

이때, 상기 콘택플러그(53)는 비트라인 콘택홀을 형성하고 이를 매립하는 콘택플러그용 도전층을 전체표면상부에 형성하고 이를 평탄화식각하여 형성한다.In this case, the contact plug 53 is formed by forming a bit line contact hole and forming a contact plug conductive layer for filling it on the entire surface and flattening etching.

그 다음, 전체표면상부에 제2층간절연막(55)을 형성한다.Next, a second interlayer insulating film 55 is formed over the entire surface.

그리고, 상기 제2층간절연막(55) 상부에 비트라인용 도전층(57)과 제1식각장벽층(59)을 적층한다.The bit line conductive layer 57 and the first etch barrier layer 59 are stacked on the second interlayer insulating layer 55.

이때, 상기 제1식각장벽층(59)은 질화막으로 형성한다.In this case, the first etching barrier layer 59 is formed of a nitride film.

그 다음, 상기 비트라인용 도전층(57)과 제1식각장벽층(59)을 비트라인 마스크(도시안됨)를 이용한 사진식각공정으로 식각하여 패터닝시킨다.Next, the bit line conductive layer 57 and the first etching barrier layer 59 are etched and patterned by a photolithography process using a bit line mask (not shown).

그리고, 전체표면상부에 제2식각장벽층(61)인 질화막으로 형성하고 이를 이방성식각하여 상기 패터닝된 비트라인용 도전층(57)과 제1식각장벽층(59) 적층구조 측벽에 제2식각장벽층(61)으로 스페이서를 형성한다.In addition, a second etching barrier layer 61 is formed on the entire surface of the second etching barrier layer 61 and anisotropically etched to form sidewalls of the patterned bit line conductive layer 57 and the first etching barrier layer 59. The barrier layer 61 forms a spacer.

그 다음, 전체표면상부를 평탄화시키는 제3층간절연막(63)을 형성한다. 이때, 상기 제3층간절연막(63)은 상기 제1층간절연막(51)과 같이 유동성이 우수한 절연물질로 형성한다. (도 3a)Next, a third interlayer insulating film 63 is formed to planarize the entire upper surface portion. In this case, the third interlayer insulating layer 63 is formed of an insulating material having excellent fluidity, like the first interlayer insulating layer 51. (FIG. 3A)

그리고, 저장전극 콘택마스크(도시안됨)를 이용한 자기정렬적인 콘택 식각공정으로 상기 저장전극 콘택플러그(53)를 노출시키는 비트라인 콘택홀(65)을 형성한다.The bit line contact hole 65 exposing the storage electrode contact plug 53 is formed by a self-aligned contact etching process using a storage electrode contact mask (not shown).

그리고, 상기 저장전극 콘택홀(65) 측벽에 제3식각장벽층(67)으로 스페이서를 형성한다. 이때, 상기 제3식각장벽층(67)은 질화막으로 형성한다.A spacer is formed on the sidewall of the storage electrode contact hole 65 as a third etching barrier layer 67. In this case, the third etching barrier layer 67 is formed of a nitride film.

후속공정으로 상기 콘택홀(65)을 매립하는 비트라인 콘택플러그(도시안됨)를 형성한다. (도 3b)In a subsequent process, a bit line contact plug (not shown) filling the contact hole 65 is formed. (FIG. 3B)

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은, 자기정렬적인 콘택 식각공정후 콘택홀 측벽에 식각장벽층을 형성하여 절연특성을 향상시킴으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the self-aligned contact forming method of the semiconductor device according to the present invention improves the characteristics and reliability of the semiconductor device by forming an etch barrier layer on the sidewall of the contact hole after the self-aligned contact etching process to improve the insulating properties. And thereby high integration of the semiconductor device.

Claims (3)

반도체기판 상부에 도전층과 제1식각장벽층을 적층하고 이를 노광마스크를 이용한 사진식각공정으로 패터닝하여 도전배선을 형성하는 공정과,Stacking the conductive layer and the first etching barrier layer on the semiconductor substrate and patterning the conductive layer and the first etching barrier layer by a photolithography process using an exposure mask; 상기 도전배선을 포함한 전체표면상부에 제2식각장벽층을 형성하는 공정과,Forming a second etching barrier layer on the entire surface including the conductive wiring; 전체표면상부를 평탄화시키는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film to planarize the entire upper surface; 상기 층간절연막을 자기정렬적으로 콘택 식각하여 상기 반도체기판을 노출시키는 콘택홀을 형성하는 공정과,Forming a contact hole exposing the semiconductor substrate by performing self-aligned contact etching on the interlayer insulating film; 상기 콘택홀 측벽에 제3식각장벽층 스페이서를 형성하는 공정을 포함하는 공정을 포함하는 반도체소자의 자기정렬적인 콘택 형성방법.And forming a third etch barrier layer spacer on the sidewalls of the contact holes. 제 1 항에 있어서,The method of claim 1, 상기 제1,2,3식각장벽층은 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 자기정렬적인 콘택 형성방법.And the first, second and third etch barrier layers are formed of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 자기정렬적인 콘택 식각공정은 층간절연막과 제1,2식각장벽층의 식각선택비 차이를 이용하여 실시하는 것을 특징으로하는 반도체소자의 자기정렬적인 콘택 형성방법.The self-aligned contact etching process may be performed by using an etching selectivity difference between the interlayer insulating layer and the first and second etching barrier layers.
KR1019990064094A 1999-12-28 1999-12-28 A method for forming a self aligned contact of semiconductor device KR20010061598A (en)

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