KR20010011639A - Method for forming self align type contact plug in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a self aligned contact plug is to prevent from over-etching of a hard mask insulating layer and a spacer, thus to avoid shorting of a semiconductor device and the contact plug. CONSTITUTION: A method for forming a self aligned contact plug comprises the steps of: forming a transistor including a gate electrode and a source/drain junction region, the gate electrode formed by depositing a gate oxide layer on a semiconductor substrate(100) having a field oxide layer(102) and depositing a gate conductive layer and a hard mask insulation layer(106) on an active region of the substrate, the gate electrode having an insulation spacer(108); forming an insulating layer on the substrate and etching the same to form an insulating layer pattern; forming a gap filling layer between the spacer; forming an upper spacer on the sidewall of the pattern; selectively removing the gap filling layer to open the junction region of the substrate; and burying a contact hole of the upper spacer with a conductive layer to form a contact plug.

Description

Method for forming self align type contact plug in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in a highly integrated semiconductor device, mask nitride film and spacer loss are reduced when forming a self-aligned contact plug, thereby increasing the contact area with the silicon substrate or the contact surface, preventing shorting of the device, and providing alignment margin A method of forming a self-aligned contact plug of a semiconductor device capable of increasing the degree.

In recent years, as semiconductor devices become more integrated, memory cell sizes are gradually decreasing, so that margins of word lines, capacitor contacts, bit lines, and capacitor contacts become smaller, resulting in smaller capacitor contacts.

As semiconductor integrated circuits are highly integrated, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. / Developed. The contact hole is formed by using the step of the surrounding structure. The contact hole of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material on which the contact hole is to be formed, and the etching method. It is used in a method suitable for realizing a semiconductor device to be micronized.

1A to 1B are process flowcharts illustrating a method of forming a self-aligned contact plug of a semiconductor device according to the prior art. Referring to this, a process of manufacturing a self-aligned contact plug according to the related art is as follows.

First, as shown in FIG. 1A, a gate oxide film (not shown) is formed in the active region of the semiconductor substrate 12 on which the field oxide film 12 is formed, and the doped polysilicon film 14 and the hard mask are formed thereon. The insulating film 16 is stacked and patterned to form a gate electrode 20 having a spacer 18 of an insulating material on the sidewall thereof. Although not shown, a source / drain junction region in which impurities are implanted is formed in the substrate between the edge of the gate electrode 20 and the field oxide film 12.

Subsequently, after the insulating film 22 is formed on the entire surface of the substrate, a photo process using a mask having a gate mask or a smaller width is performed to form the photoresist pattern 24 on the upper surface of the insulating film 22.

As illustrated in FIG. 1B, the etching process is performed to pattern the lower insulating layer 22 in accordance with the photoresist pattern 24, and then the photoresist pattern 24 is removed. Then, a contact hole 26 is formed in which the substrate surface (bonding region) between the spacers 18 of the gate electrode is opened. The contact hole is a space where a self-aligned contact plug is connected to the bit line or the storage electrode.

However, in the method of forming a conventional self-aligned contact plug as described above, when the spacer 18 and the hard mask insulating film 16 are formed of a nitride film, the nitride film used as an etch barrier during the insulating film patterning process does not act as a barrier and thus a hard mask. There were often cases (F) in which predetermined portions of the insulating film 16 and the spacer 18 were excessively etched.

The loss region due to the excessive etching not only causes a short between the bit line or the plug contact and the word line (gate electrode), but also causes a short between the storage electrode contact and the bit line.

An object of the present invention is to form an insulating film pattern by depositing an insulating film on the lower structure having a self-aligned contact hole, and then etching before the hard mask insulating film or the spacer is exposed until the surface is exposed to form an insulating film pattern and additionally forming a spacer on the sidewall of the insulating film By forming two layers of self-aligned contact holes, it is possible to prevent excessive etching of the hard mask insulating film and the spacers of the word lines and the bit lines, thereby increasing the contact area of the silicon substrate and the contact surface, preventing short circuits of the devices, and increasing the alignment margin. There is provided a method of forming a self-aligned contact plug of a semiconductor device.

1A to 1B are process flowcharts illustrating a method for forming a self-aligned contact plug of a semiconductor device according to the prior art;

2A to 2E are flowcharts illustrating a method of forming a self-aligned contact plug in a semiconductor device according to an embodiment of the present invention;

3 is a cross-sectional view illustrating a method of forming a self-aligned contact plug of a semiconductor device according to another embodiment of the present disclosure;

4A to 4C are flowcharts illustrating a method of forming a self-aligned contact plug in a semiconductor device according to still another embodiment of the present invention;

5 is a cross-sectional view illustrating a method of forming a self-aligned contact plug of a semiconductor device according to still another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100, 200: semiconductor substrate 102, 202: field oxide film

104, 214: doped polysilicon film 106, 216: hard mask insulating film

108: lower spacer 110, 210: gate electrode

112 ', 113: insulating film pattern 114, 120: junction region contact hole

116: gap fill film 118: upper spacer

220, 226: insulating film 224: contact plug for storage electrode

226 wiring contact plug 228 storage electrode

230: plate electrode 232: lower spacer

234 insulating film pattern 236 upper spacer

238: gap fill film 240: lower contact plug contact hole

In order to achieve the above object, the present invention is to form a contact oxide for vertically interconnecting a semiconductor device formed on the active region of the semiconductor substrate and the upper wiring, forming a gate oxide film on the semiconductor substrate formed with the field oxide film, A gate conductive layer and a hard mask insulating film are stacked on an active region of a substrate, and a gate electrode having a spacer made of an insulating material on its sidewall and a transistor having a source / drain junction region in a substrate between the gate electrode edge and the field oxide film are formed. Forming an insulating film pattern on the gate electrode and forming a gap fill film between the spacers on the sidewalls of the gate electrode, by forming an insulating film on the entire surface of the substrate on which the transistor is formed, and then etching the same using a photomask and an etching process using a contact mask. And the upper spar on the sidewalls of the insulating film pattern. Forming a contact; forming a contact hole to open the junction region of the substrate by selectively removing the gap fill layer with the upper spacer and the lower spacer as an etch barrier; and filling the source / contact with the contact hole of the upper spacer. And forming a contact plug in which the drain junction region and the bit line or storage electrode to be formed later are vertically connected.

Another method of the present invention for achieving the above object is to form a contact plug for vertically interconnecting a semiconductor device and an upper capacitor formed on the active region of the semiconductor substrate, the semiconductor device and the bit Forming a line, forming a spacer on the side of the bit line, forming an insulating film pattern in alignment with the bit line, forming a gap fill film between the sidewall spacers of the bit line, and forming an upper spacer on the sidewall of the insulating film pattern. Forming a contact hole to form an upper barrier and a lower spacer as an etch barrier, and selectively removing a gapfill film to form a contact hole for opening a junction portion or a lower contact plug of the substrate; and filling a conductor to the contact hole of the upper spacer. The source / drain junction region and the storage electrode to be formed later Forming an upper contact plug to connect vertically.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are process flowcharts illustrating a method of forming a self-aligned contact plug in a semiconductor device according to an embodiment of the present invention, which is a bit line contacting a source / drain junction region between spacers of a gate electrode. To a contact plug manufacturing process for a storage electrode.

First, as shown in FIG. 2A, a gate oxide film is formed in an active region of the semiconductor substrate 100 on which the field oxide film 100 is formed. A gate electrode 110 having a doped polysilicon film 104 and a nitride film as a hard mask insulating film 106 stacked thereon as a gate conductive layer and having a spacer 108 made of an insulating material (for example, a nitride film) on the sidewall thereof; A transistor having a source / drain junction region (not shown) is formed in the substrate between the edge of the gate electrode 110 and the field oxide film 102. After the insulating film 112 is formed on the entire surface of the substrate on which the transistor is formed, the photoresist pattern 114 is formed on the upper surface of the insulating film 112 using a photolithography process using a contact mask. Here, the insulating film 112 is preferably an oxidizing material.

Next, as illustrated in FIG. 2B, the insulating layer 112 is etched to match the photoresist pattern 114 to form an insulating layer pattern 112 ′ on the top surface of the gate electrode 110. In this case, the etching process of the insulating film 112 is performed before the hard mask insulating film 106 to the spacer 108 is exposed to the surface until the surface is exposed to prevent the excessive etching, thereby contact plug to the gate electrode To prevent short between.

As illustrated in FIG. 2C, a gap fill layer 116 is formed in the self-aligned contact hole 114 exposed between the spacers 108 on the sidewalls of the gate electrode 110. Here, the gap fill film 116 is preferably one of a doped polysilicon film, a metal compound, and a metal.

Subsequently, as shown in FIG. 2D, the upper spacers 118 are formed on the sidewalls of the insulating film pattern 112 ′. At this time, it is preferable to use a nitride film as the material of the spacer 118.

As shown in FIG. 2E, the upper spacer 118 and the lower spacer 108 are used as an etch barrier, and the gap fill layer 116 is selectively removed to form a contact hole 120 for opening a junction portion of the substrate. do.

Subsequently, although not shown in the drawings, a conductor is embedded in the contact hole 120 to the upper spacer 118 to form a contact plug in which the source / drain junction region and the bit line or storage electrode to be formed later are vertically connected.

3 is a cross-sectional view illustrating a method of forming a self-aligned contact plug of a semiconductor device according to another embodiment of the present invention. Another embodiment of the present invention is an insulating film pattern during a gap fill film removing process in the embodiment of FIGS. 2A to 2E. In order to prevent the upper surface of the (112 ') from being etched, a protective insulating film 113 is added to the upper portion of the insulating film pattern 112'.

4A through 4C are process flowcharts illustrating a method of forming a self-aligned contact plug of a semiconductor device according to another embodiment of the present invention, which is a vertical contact with a source / drain junction region between sidewall spacers of a capacitor. A contact plug manufacturing process for wiring.

First, as shown in FIG. 4A, a gate oxide film is formed in an active region of the semiconductor substrate 200 on which the field oxide film 202 is formed. A gate polysilicon film 214 is deposited thereon as a gate conductive layer, and a nitride film, which is a hard mask insulating film 216, is stacked and a gate electrode having a spacer 218 made of an insulating material (for example, a nitride film) on the sidewall thereof. A transistor having a source / drain junction region (not shown) is formed in the substrate between the 210 and the edge of the gate electrode 210 and the field oxide film 202. In addition, after the insulating film 220 is stacked on the gate electrode 210 where the transistor is formed, a conductor is buried between the spacers 218 to form lower contact plugs 222 and 224 for the bit line and the storage electrode. Next, after forming the interlayer insulating film 226 on the resultant, the interlayer insulating film 226 is etched to open the contact plugs 222 and 224, and then a bit line connected to the lower contact plug 222 for the bit line is formed. . Here, the bit line includes an insulating layer pattern 230 that contacts the contact plug 222 and an insulator spacer 232 on a sidewall thereof.

As shown in FIG. 4B, an insulating film 234 is deposited on the resultant and patterned to form an insulating film pattern 234 to be aligned with the bit line 228. A gap fill layer 236 is formed between the sidewall spacers 232 of the bit line. Next, an upper spacer 238 is formed on sidewalls of the insulating film pattern 234.

Subsequently, as shown in FIG. 4C, the upper spacer 238 and the lower spacer 232 are used as an etch barrier, and the gap fill layer 236 is selectively removed to open the lower contact plug 222 for the storage electrode. The contact hole 240 is formed.

Subsequently, although not shown in the drawing, the conductor is filled up to the contact hole 240 of the upper spacer 238 to form an upper contact plug in which the source / drain junction region and the storage electrode to be formed later are vertically connected.

5 is a cross-sectional view illustrating a method of forming a self-aligned contact plug of a semiconductor device according to still another embodiment of the present invention.

Referring to this, another embodiment of the present invention is to protect the upper surface of the insulating film pattern 234 'in order to prevent the upper surface of the insulating film pattern 234' during the gap fill film removal process in the embodiment of Figures 4a to 4c. The addition of the insulating film pattern 235 is shown.

As described above, when the self-aligned contact plug forming method of the semiconductor device according to the present invention is used, the silicon substrate (or lower structure) as well as the word line (gate electrode) or bit line surrounding the contact hole in the self-aligned manner are formed. Since the etching loss of the insulating layer (hard mask and spacer) is reduced, the short between the word line or the bit line and the contact electrode can be prevented, and the alignment margin of the contact electrode can be increased.

In addition, the present invention can reduce the burden on the production of additional mask because the insulating film pattern and the upper spacers to be added on the word line and the bit line can be formed using the mask of the existing word line and bit line.

Claims (7)

In forming a contact plug for vertically interconnecting a semiconductor device formed on the active region of the semiconductor substrate and the wiring thereon, A gate oxide film is formed on the semiconductor substrate having the field oxide film formed thereon, and a gate conductive layer and a hard mask insulating film are stacked on an active region of the substrate, and a gate electrode having a spacer made of an insulating material on a sidewall thereof, between the gate electrode edge and the field oxide film. Forming a transistor having a source / drain junction region in the substrate; Forming an insulating film pattern on the gate electrode by forming an insulating film on the entire surface of the substrate on which the transistor is formed and then etching the same using a photo mask and an etching process using a contact mask; Forming a gap fill layer between the spacers on the sidewalls of the gate electrode; Forming an upper spacer on sidewalls of the insulating film pattern; Forming a contact hole for opening the junction portion of the substrate by using the upper spacer and the lower spacer as an etch barrier and selectively removing the gap fill layer; And Embedding a conductor to the contact hole of the upper spacer to form a contact plug in which a source / drain junction region and a subsequent bit line or storage electrode are vertically connected. Contact plug formation method. The method of claim 1, wherein the insulating film over the gate electrode is an oxide film. The method of claim 1, wherein the upper spacers of the sidewalls of the insulating film pattern are nitride films. 2. The method of claim 1, wherein the gap fill film is any one of a doped polysilicon film, a metal compound, and a metal. The method of claim 1, wherein the etching process is performed only before the hard mask insulating layer or the spacer is exposed or until the surface thereof is exposed during the etching process. The method of claim 1, further comprising forming another insulating film pattern on the insulating film pattern to protect the pattern when the gap fill film is removed. In forming a contact plug for vertically interconnecting a semiconductor device and an upper capacitor formed on the active region of the semiconductor substrate, Forming a semiconductor device and a bit line on the semiconductor substrate on which the field oxide film is formed, and forming a spacer on the side of the bit line; Forming an insulating layer pattern to be aligned with the bit line; Forming a gap fill layer between sidewall spacers of the bit line; Forming an upper spacer on sidewalls of the insulating film pattern; Forming a contact hole for opening the junction region or the bottom contact plug of the substrate by using the upper spacer and the lower spacer as an etch barrier and selectively removing the gap fill layer; And Embedding a conductor up to the contact hole of the upper spacer to form an upper contact plug vertically connecting a source / drain junction region and a storage electrode to be formed later, the self-aligned contact plug of the semiconductor device. Formation method.