KR20010008589A - Method of forming bit-line of semiconductor device utilized damascene process - Google Patents

Abstract

PURPOSE: A bit line formation method is provided to be capable of effectively forming a plug and bit lines, by forming a metal bit line connected to the plug. CONSTITUTION: A gate electrode is first formed on the semiconductor substrate. An impurity implantation region is then formed between the gate electrode and a device isolation film(12). Only the impurity implantation region corresponding to bit lines(72) is epitaxially grown to form plugs(36,40). Next, after forming an interlayer insulating film/an etch stop film/an interlayer insulating film are formed on the resulting surface, a contact hole for performing a damascene pattern is formed within the interlayer insulating film. A metal film is filled up to a given region of the contact hole. An insulating film is filled within the remaining contact hole. Then, an upper portion of the interlayer insulating film is selectively removed using the insulating film and the etch stop film within the contact hole, thus forming an electrode of the metal bit lines connected to an underlying plugs or the gate electrode. Then, the etch stop film is removed and spacers (28,70') made of an insulating material are then formed at the sidewall of the bit lines.

Description

Method of forming bit-line of semiconductor device utilized damascene process}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a bit line of a new semiconductor device using a damascene technique capable of lowering wiring resistance of a highly integrated semiconductor device and increasing a manufacturing yield.

Higher integration of semiconductor devices requires lithography, cell structures, new materials related to wiring, and physical property limits related to insulating films. In addition, as the cell area is reduced due to the higher integration of semiconductor devices, the reduction of the contact hole area is also essential.

In 64M DRAM devices with a design rule of 0.3 ?? m to 0.4 ?? m, even if the contact hole is formed with a feature size of about 0.5 ?? m, the peripheral structure may be caused by misalignment of the mask. That is, the exposure of the gate electrode or the bit line occurs frequently, which causes the contact between the gate electrode and the storage electrode and the bit line and the storage electrode, which is a major factor in reducing the reliability of the memory device.

Accordingly, many methods for reliably achieving miniaturization of contact holes without exposure of peripheral structures due to misalignment of masks, etc. have been researched and developed, and one of them is a method of forming a self-aligned contact. .

The self-aligned contact forming method is a method of opening only the contact portion by adjusting the etching amount by using the uneven portion on the semiconductor substrate, the height of the surrounding structure, the thickness of the insulating material to form the contact and the etching method of various sizes Since a contact can be obtained, it is suitable for realization of the semiconductor device miniaturized by high integration.

However, the above self-aligned contact forming method also has a limitation in securing the area because the contact electrode is usually formed between the spacer insulating films when the source / drain area is continuously reduced due to the high integration of the semiconductor device. The substrate may be damaged by an alignment or excessive etching process, resulting in deterioration of the device, or a bridge between the bit line contact plug and the storage node electrode contact plug.

On the other hand, in recent years, in order to increase the operation speed of semiconductor devices, wiring lines have been replaced with metals to greatly reduce wiring resistance, which has led to the use of metals for bit lines. The metal bit line may not only shorten the manufacturing process but also improve the performance of the semiconductor device if the metal bit line is processed in the same process as the manufacturing process of the metal insulator metal capacitor.

However, the positive photoresist mainly used in semiconductor device processing leaves the bit line metal in regions where masking is not performed even after the bit line etching process due to its material characteristics. When the residual metal of the bit line is large, the stress of the metal itself also occurs, but there is a problem of lowering the yield of the semiconductor device due to the lifting of the residual metal by the subsequent thermal process.

An object of the present invention is to form a bit line made of metal in order to solve the problems of the prior art as described above, by forming a plug in contact with the active region of the substrate by the epitaxial growth process and etching by forming the bit line in the inlay process Disclosed is a method of forming a bit line of a semiconductor device using a damascene technique that can prevent a decrease in manufacturing yield due to a process.

1 to 16 are process flowcharts illustrating a bit line forming method of a semiconductor device using the damascene technique according to the present invention.

Explanation of symbols on the main parts of the drawings

10 silicon substrate 12 device isolation film

22 gate oxide film 24 doped polysilicon film

26: hard mask 28, 70 ': spacer

30, 32: impurity junctions 34, 38, 50, 54: photoresist pattern

36, 40 Plug 42 First interlayer insulating film

44: second interlayer insulating film 46: etch stop film

48: third interlayer insulating film 52, 53: first contact hole

56: second contact hole 58: etching prevention film

60: adhesive film 62: diffusion barrier film

64 metal 68 insulating film pattern

72: bit line

In order to achieve the above object, the present invention provides a method of forming a bit line of a semiconductor device, comprising: forming a gate electrode on an upper surface of a semiconductor substrate, and forming a conductive impurity implantation region between the gate electrode edge and the device isolation film; Selectively epitaxially grow only the conductive impurity implantation region corresponding to the bit line to form a plug, and embed and planarize the first interlayer insulating film in the resultant, and a second interlayer insulating layer to insulate the bitline to be formed later on the resultant. And sequentially forming an etch stop film and a third interlayer insulating film, selectively etching the third interlayer insulating film and an etch stop film to form a first contact hole, and selecting a second interlayer insulating film exposed by the first contact hole. Etching to form a second contact hole through which the surface of the plug or gate electrode is opened; and forming a metal up to a predetermined region of the first contact hole. Forming an insulating film pattern for forming the insulating film for electrical insulation with the upper structure in the contact hole not filled with the metal film, and using the insulating film pattern and the etch stop film in the contact hole as an etching mask to selectively etch the third interlayer insulating film. Forming a bit line formed of an insulating layer pattern and a metal layer and connected to a lower plug or gate electrode, and forming a spacer of an insulating material on the sidewalls of the bit line and removing the etch stop layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 through 16 are flowcharts illustrating a method of forming a bit line of a semiconductor device using the damascene technique according to the present invention.

Referring to this, the manufacturing process of a composite memory device according to an embodiment of the present invention is as follows.

First, as shown in FIG. 1, as a semiconductor substrate, a well (not shown) is formed by ion implanting a desired kind of impurity into a desired portion of the silicon substrate 10, and the active region of the device in the substrate 10 is formed. An isolation layer 12 having a shallow trench isolation (STI) structure is formed to define an isolation region.

The doped polysilicon film 24 and the hard mask film 26 are sequentially formed as the gate oxide film 22 and the gate conductive layer on the entire substrate, and then the etching process using the gate mask is performed to stack the hard mask. The film 26 and the doped polysilicon film 24 are selectively etched to form patterns of the gate electrodes 20a and 20b, and the gate oxide film 22 is also etched so as to self-align with the gate electrodes. In this case, the hard mask film 19 is formed of an oxide film or a nitride film to insulate the upper structure. Then, the cell gate electrode 20a and the gate electrode 20b of the peripheral circuit are formed in the memory cell array region 100 and the peripheral circuit region 200 of the substrate 10, respectively. The cell gate electrode 20a has a higher density than the gate electrode 20b of the peripheral circuit.

Next, an insulating material, for example, a nitride film is deposited on the entire surface of the resultant material, and the nitride film is etched by the entire surface etching process to form spacers 28 on sidewalls of the gate electrodes 20a and 20b. Then, using the gate electrodes 20a and 20b and the spacers 28 as masks, ion-implanted conductive impurities are implanted into the substrate exposed between the gate electrodes 20a and 20b and the device isolation layer 12, thereby providing source / drain and impurity junctions. To form (30,32). In this embodiment, the source / drain junction 30 of the memory cell array region 100 is implanted with p-type impurities, and the source / drain and impurity junctions 30 and 32 of the peripheral circuit region 200 are n-type and Ions are implanted with p-type impurities, respectively.

2 and 3, the photoresist pattern 34 masking the p-type impurity junction 32 of the peripheral circuit region is applied to the resultant, followed by the memory cell array and the peripheral circuit region 100 and 200. Only the n-type impurity junction 30 of is selectively grown epitaxially. Thus, a plug 36 made of polysilicon doped with n-type impurities is formed on the n-type impurity junction 30. The photoresist pattern 34 is removed.

Next, as shown in FIG. 4, after the photoresist pattern 38 masking the n-type impurity junction 30 of the cell region 100 and the peripheral circuit region 100 is applied to the resultant, the p-type impurity is applied. Only the junction 32 is selectively epitaxially grown to form a polysilicon plug 40 doped with p-type impurities on the p-type impurity junction 32. Then, the photoresist pattern 38 is removed.

Subsequently, as shown in FIG. 5, a silicon oxide-based material is deposited to insulate the result between the gate electrodes 20a and 20b and the selective epitaxially grown plugs 36 and 40 to form the first interlayer insulating layer 42. Then, a chemical mechanical polishing (CMP) process is performed to planarize the resultant surface. In this case, the planarization process is performed until the top surfaces of the gate electrodes 20a and 20b are exposed.

Subsequently, as shown in FIG. 6, a second interlayer insulating film 44 is formed on the planarized resultant to insulate the bit line to be formed thereafter, and thereon, to prevent excessive etching during etching of the insulating material in the bit line. An etch stop layer 46 is stacked, and a third interlayer dielectric layer 48 is sequentially stacked. Here, the second and third interlayer insulating films 44 and 48 use a silicon oxide-based material, and the etch stop film 46 uses SiON or SiN.

A photoresist pattern 50 having a window W ₁ for securing a predetermined region in which a bit line is to be formed is first formed on the third interlayer insulating layer 48.

Subsequently, as illustrated in FIG. 7, the lower third interlayer insulating layer 48 ′ and the etch stop layer 46 opened by the window W ₁ of the photoresist pattern 50 are selectively etched to form the first contact hole ( 52 and 53, the pattern 50 is removed. Here, reference numeral 52 denotes a contact hole corresponding to an upper portion of the plugs 36 and 40 and 53 denotes a contact hole corresponding to an upper portion of the gate electrode.

Subsequently, as shown in FIGS. 8 and 9, a photoresist pattern 54 having W ₂ relatively narrower than W ₁ is formed in the resultant, and the second interlayer exposed by the window of the pattern 54 is formed. The insulating layer 44 is selectively etched to form second contact holes 56 narrower than the width of the first contact holes 52 and 53. At this time, the etching process not only opens the upper surfaces of the plugs 36 and 40 by etching the second interlayer insulating film 44, but also by etching the hard mask 26 of the gate electrode selected by the photoresist pattern 54. The upper surface of the polysilicon film 24 is opened. Reference numeral 56 'denotes a second contact hole in which the doped polysilicon film 24 is opened.

These two contact hole etching processes can be applied to the damascene technique, which is typically used for vertical wiring, to form metal bitlines, so that subsequent follow-up due to metal residues that occur during bitline etching processes To prevent deterioration of the process.

Subsequently, as shown in FIG. 10, an etch stop layer 58 is further formed on the inner wall of the resultant contact hole. Here, the etch barrier 58 serves to prevent the adhesive material, the diffusion barrier, and the inner metal of the bit line from being etched, and uses SiON or SiN.

Subsequently, as shown in FIG. 11, an adhesive film 60 is further formed on the resultant to improve adhesion between the metal of the bit line and the plug, and the ion diffusion reaction between the metal of the bit line and the plug is prevented thereon. The diffusion barrier 62 is laminated. At this time, the adhesive film 60 is Ti or WN, the diffusion barrier 62 is any one of TiN, TiAlN, WN.

12 and 13, the metal filled in the contact hole until the surface of the third interlayer insulating film 48 is exposed after embedding the metal 64 suitable for the electrical characteristics of the bit line in the contact hole. (64), the diffusion barrier film 62 and the adhesive film 60 are planarized using a CMP process. Subsequently, the metal 64, the diffusion barrier 62, and the adhesive layer 60, which are filled in the contact holes, are recessed again by a dry etching process, but the height of 1000-1500Å is increased from the surface of the third interlayer dielectric layer 48. Remove until Here, reference numeral 66 denotes a result remaining in the contact hole by the above-described etching process.

Subsequently, as shown in FIG. 14, an insulating material (SiON or SiN) is deposited to completely fill the contact hole, and the insulating material is etched to the surface of the interlayer insulating film by a CMP process or an etching process to form an insulating pattern 68. Form. Here, the insulating film pattern 68 is to insulate it from the conductor of the upper structure while protecting the metal of the bit line.

Then, only the third interlayer insulating film 48 is selectively etched using the insulating film pattern 68 and the etch stop film as an etching mask.

15 and 16, an insulating film 70 (SiON or SiN) is deposited to electrically insulate with other conductors while protecting the sidewalls of the bit lines. The insulating layer 70 and the etch stop layer 58 are etched by a dry etching process to form spacers 70 'on sidewalls of the bit lines. In this case, since the etch stop layer 58 makes the etching process difficult during the formation of the contact electrode for another wiring to be performed later, all of the portions except the bit line region are removed to expose the surface of the second interlayer insulating layer 44. It is preferable.

By this manufacturing process, the metal bit line 72 of the present invention connected to the lower plugs 36 and 40 and the gate electrodes 20a and 20b is completed.

Therefore, as described above, in the method of forming a bit line of a semiconductor device according to the present invention, a highly integrated composite semiconductor is formed by epitaxially growing a doped impurity junction region to form a plug and then forming a metal bit line connected to the plug by using a damascene technique. Even if the gate electrode or the semiconductor device is narrow in the device, the plug and the bit line can be effectively formed, thereby increasing the reliability of the wiring process.

In addition, the present invention can minimize the metal residue generated during the etching process for the bit line to prevent the stress of the metal itself constituting the bit line or the lifting of the metal by the subsequent thermal process.

Claims (10)

In the method of forming a bit line of a semiconductor device, Forming a gate electrode over the semiconductor substrate and forming a conductive impurity implantation region between the gate electrode edge and the device isolation film; Selectively epitaxially growing only the conductive impurity implantation region corresponding to the bit line to form a plug, and embedding the first interlayer insulating film in the resultant and planarizing it; Sequentially forming a second interlayer insulating film, an etch stop film, and a third interlayer insulating film on the resultant layer to insulate a bit line to be formed later; Selectively etching the third interlayer insulating layer and the etch stop layer to form a first contact hole; Selectively etching the second interlayer insulating layer exposed by the first contact hole to form a second contact hole in which a plug or gate electrode surface is opened; Filling a metal film to a predetermined region of the first contact hole; Forming an insulating film pattern for electrical insulation with an upper structure in a contact hole not filled with the metal film; Selectively etching the third interlayer insulating layer using the insulating layer pattern and the etch stop layer of the contact hole as an etch mask to form a bit line formed of the insulating layer pattern and the metal layer and connected to a lower plug or gate electrode; And And forming a spacer of an insulating material on the sidewalls of the bitline and removing the etch stop layer. 2. The method of claim 1, wherein the first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film are silicon oxide films. The method of claim 1, wherein the etch stop layer is any one of SiON and SiN. The method of claim 1, wherein after forming the second contact hole, an etch stop layer is further formed on the interlayer insulating layer inside the contact hole. The method of claim 4, wherein the etch stop layer is any one of SiON and SiN. The method of claim 1, wherein after the etching prevention layer is formed, an adhesive layer is further formed to bond the metal layer to the lower plug or the gate electrode on the entire surface of the resultant formed first and second contact holes. A method of forming a bit line in a semiconductor device. 7. The method of claim 6, wherein the adhesive layer is Ti or WN. The method of claim 6, further comprising forming a diffusion barrier layer on the adhesive layer to prevent conductive ion diffusion of the plug or gate electrode. The method of claim 8, wherein the diffusion barrier is any one of TiN, TiAlN, and WN. The method of claim 1, wherein the insulating film over the bit line and the insulating film over the spacer are any one of SiON and SiN.