KR20030002749A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A fabrication method of a semiconductor device is provided to reduce plug resistance and to simplify manufacturing processes by performing single SAC(Self Aligned Contact) processing. CONSTITUTION: Word lines(43) having a hard mask(44) and a spacer(46) are formed on a substrate(41). After forming the first insulating layer(47), a bit line contact hole and a storage node contact hole are formed by selectively etching the first insulating layer(47). A bit line and storage node contact plug(50a,50b) are formed in the bit line and storage node contact hole, respectively. After forming the second insulating layer(51) on the resultant structure, a bit line damascene pattern is formed to expose the bit line contact plug(50a) by selectively etching the second insulating layer. A bit line(54) and a bit line hard mask(55) are sequentially formed in the bit line damascene pattern.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to simplify and stabilize the process of forming a bit line contact plug and a storage node contact plug, and to manufacture a semiconductor device capable of stabilizing contact resistance of a bit line. It is about a method.

In general, as semiconductor devices are highly integrated, the size of each pattern is also reduced, and difficult problems in the pattern forming process occur. In particular, in patterning the bit line contact plug and the storage node contact plug of a cell, it is difficult to define each contact pattern separately because the contact size and the distance between the contacts are very small. To solve this problem, a large contact pattern is formed at a time by a self-aligned contact etching process, and then the bit line contact plug and the storage node contact plug are separately formed by a chemical mechanical polishing method using a word line hard mask layer as an etching barrier. The way to make it is universal. A method of fabricating a semiconductor device to which the self-aligned contact etching process and the contact plug forming process are applied will be described below with reference to FIGS. 1A to 1F.

1A to 1F are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation region 12 is formed on a semiconductor substrate 11 to define an active region. The word line 13 is formed on the semiconductor substrate 11 on which the device isolation layer 12 is formed. The word line hard mask layer 14 is formed on the word line 13. Source and drain ion implantation forms drain and source junctions 15a and 15b in the semiconductor substrate 11. The word line spacers 16 are formed on sidewalls of the stacked structure of the word line 13 and the word line hard mask layer 14. The first insulating layer 17 is formed on the entire structure including the word line spacer 16, and the first photoresist pattern 18 to be used in the first self-aligned contact etching process is formed on the first insulating layer 17. Form. The first insulating layer 17 is etched by using a first self-aligned etching process using the first photoresist pattern 18 as an etching mask to expose the drain and source junctions 15a and 15b, thereby draining the junction 15a. The first bit line contact hole 19a is formed in the first junction, and the first storage node contact hole 19b is formed in the source junction 15b.

In the above, the device isolation layer 12 is preferably formed by a shallow trench isolation (STI) process for high integration of the device. The word line hard mask layer 14 is preferably formed of a nitride-based material, and is formed by depositing a thick layer in consideration of the thickness removed during the first chemical mechanical polishing process. The word line spacer 16 may be formed of a nitride-based material in order to prevent the word line 13 from being exposed during the first self-aligned contact etching process. The first insulating layer 17 mainly deposits an oxide-based material in order to protect the cells while electrically insulating the surrounding cells, and performs a post-deposition planarization process to facilitate the first self-aligned contact etching process.

Referring to FIG. 1B, the first photoresist pattern 18 is removed and a contact plug material, such as polysilicon, is deposited so that the contact holes 19a and 19b are sufficiently buried. Thereafter, the first chemical mechanical polishing process is polished to a part of the word line hard mask layer 14 to form the bit line contact plug 20a and the first storage node contact plug 20b, respectively. The bit line contact plug 20a is connected to the drain junction 15a, and the first storage node contact plug 20b is connected to the source junction 15b.

Referring to FIG. 1C, the second insulating layer 21 is formed on the entire structure including the contact plugs 20a and 20b. A second photoresist pattern 22 having a portion of the bit line contact plug 20a open is formed on the second insulating layer 21. The second insulating layer 21 is etched by an etching process using the second photoresist pattern 22 as an etching mask to form a second bit line contact hole 23 through which the bit line contact plug 20a is exposed.

In the above, the second insulating layer 21 is formed by depositing a thickness considering the depth of the second bit line contact hole 23 using an oxide-based material.

Referring to FIG. 1D, a bit line 24 connected to the bit line contact plug 20a is formed in the second bit line contact hole 23. The bit line hard mask layer 25 is formed on the bit line 24. The bit line spacers 26 are formed on sidewalls of the structure in which the bit lines 24 and the bit line hard mask layer 25 are stacked.

In the above, the bit line hard mask layer 25 is preferably formed of a nitride-based material, and is formed by depositing thickly in consideration of the thickness removed during the second chemical mechanical polishing process. The bit line spacer 26 may be formed of a nitride based material to prevent the bit line 24 from being exposed during the self-aligned contact etching process.

Referring to FIG. 1E, a third insulating layer 27 is formed on the entire structure including the bit line spacers 26, and a third photo to be used in the second self-aligned contact etching process on the third insulating layer 27. The resist pattern 28 is formed. The first storage node contact plug 20b is sequentially etched by sequentially etching the third insulating layer 27 and the second insulating layer 21 by a second self-aligned etching process using the third photoresist pattern 28 as an etching mask. The second storage node contact hole 29 to which the is exposed is formed.

In the above, the third insulating layer 27 deposits an oxide-based material and performs a post-deposition planarization process to facilitate the second self-aligned contact etching process.

Referring to FIG. 1F, the third photoresist pattern 28 is removed and a contact plug material, for example polysilicon, is deposited so that the second storage node contact hole 29 is sufficiently filled. Thereafter, the second chemical mechanical polishing process is polished to a part of the bit line hard mask layer 25 to form a second storage node contact plug 20b connected to the first storage node contact plug 20b.

Thereafter, the capacitor forming step, the wiring forming step, and the like are performed according to a general step to complete the semiconductor device.

The above-described method for manufacturing a semiconductor device according to the prior art causes some of the following problems.

First, the self-aligned contact etching process is performed twice. When the self-aligned contact etching process is incorrectly set, the contact plugs 20a and 20b and the word line 13 are formed in the first self-aligned contact etching process step. There is a possibility of causing an electrical short between, and there is a possibility of causing an electrical short between the contact plug 30 and the bit line 24 in the second self-aligned contact etching process step.

Second, the chemical mechanical polishing process is performed twice to form the contact plugs 20a, 20b, and 30, wherein the word line hard mask layer 14 is partially polished during the first chemical mechanical polishing process, and the second chemical mechanical polishing is performed. Because the bit line hard mask layer 25 is partially polished during the process, these hard mask layers 14 and 25 must be formed thicker than the desired thickness in the device, thereby forming the word line 13 and the bit line 24. There is a burden on the patterning etching process.

Third, it is difficult to stably adjust the polishing target in the chemical mechanical polishing process, i.e., it is excessively polished so that the word line 13 and the bit line 24 are damaged or the polishing is insufficient and thus the bridge between the plug patterns is broken. Inducing defects are generated.

Fourthly, since the plug node has a higher resistance due to the double formation of the plug patterns, the operation characteristics of the device are deteriorated.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying and stabilizing a bit line contact plug and a storage node contact plug forming process of a semiconductor device.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of stabilizing the contact resistance of the bit line.

It is still another object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing a decrease in operating characteristics of a device by preventing a double formation of a contact plug to prevent an increase in resistance of a plug node.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of realizing high integration of the device and simplifying the process.

A method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention provides a semiconductor substrate including a word line surrounded by a word line hard mask layer and a word line spacer, and a drain and a source junction; Forming a bit line contact hole and a storage node contact hole by etching a portion of the first insulating layer over the entire first insulating layer; Forming a polysilicon layer over the whole, and then etching the polysilicon layer of the bit line contact hole portion to form a bit line contact plug and a storage node contact plug, respectively; Forming a second insulating layer on the entire structure, and then polishing and planarizing the second insulating layer, the storage node contact plug, and a portion of the first insulating layer; Etching a portion of the second insulating layer to form a bit line damascene pattern to which the bit line contact plug is exposed; And forming a bit line and a bit line hard mask layer inside the bit line damascene pattern.

1A to 1F are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 41: semiconductor substrate 12, 42: device isolation film

13, 43: word line 14, 44: word line hard mask layer

15a, 45a: drain junction 15b, 45b: source junction

16, 46: word line spacer 17, 47: first insulating layer

19a: first bit line contact hole 49a: bit line contact hole

19b: first storage node contact hole 49b: storage node contact hole

50: polysilicon layer 20a, 50a: bit line contact plug

20b: first storage node contact plug

50b: storage node contact plug 21, 51: second insulating layer

23: second bit line contact hole 53: bit line damascene pattern

24, 54: bit line 25, 55: bit line hard mask layer

26 and 56: bit line spacer 27: third insulating layer

29: second storage node contact hole 30: second storage node contact plug

18, 22, 28, 48, 52, 70: photoresist pattern

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an isolation region 42 is formed on a semiconductor substrate 41 to define an active region. The word line 43 is formed on the semiconductor substrate 41 on which the device isolation layer 42 is formed. The word line hard mask layer 44 is formed on the word line 43. Source and drain ion implantation forms drain and source junctions 45a and 45b in the semiconductor substrate 41. The word line spacers 46 are formed on sidewalls of the structure in which the word line 43 and the word line hard mask layer 44 are stacked. A first insulating layer 47 is formed on the entire structure including the word line spacer 46, and a first photoresist pattern 48 to be used in the self-aligned contact etching process is formed on the first insulating layer 47. . The first insulating layer 47 is etched by a self-aligned etching process using the first photoresist pattern 48 as an etch mask to expose the drain and source junctions 45a and 45b, thereby forming a bit in the drain junction 45a. The line contact hole 49a is formed, and the storage node contact hole 49b is formed in the source junction 45b.

In the above, the device isolation layer 42 is preferably formed by a shallow trench isolation (STI) process for high integration of the device. The word line hard mask layer 44 is preferably formed of a nitride-based material. Unlike the related art, the word line hard mask layer 44 is not directly related to the chemical mechanical polishing process and thus is not polished to a certain thickness, so that the minimum thickness, that is, self-alignment, is desired in the device. It is formed to an optimal thickness that can serve as an etching barrier layer during the contact etching process. The word line spacer 46 may be formed of a nitride-based material in order to prevent the word line 43 from being exposed during the self-aligned contact etching process. The first insulating layer 47 mainly deposits an oxide-based material in order to protect the cells while electrically insulating the surrounding cells, and performs a post-deposition planarization process to facilitate the self-aligned contact etching process.

Referring to FIG. 2B, the first photoresist pattern 48 is removed, and the polysilicon layer 50 is formed to sufficiently fill the contact holes 49a and 49b. The polysilicon layer 50 is preferably planarized to facilitate the subsequent etching process. Surface planarization of the polysilicon layer 50 is performed by a dry etch back process or a chemical mechanical polishing process.

Referring to FIG. 2C, a second photoresist pattern 70 having an open bit line node region is formed on the polysilicon layer 50. In the etching process using the second photoresist pattern 70 as an etching mask, the polysilicon layer 50 is etched until the word line hard mask layer 44 is exposed to thereby expose the bit line contact plug 50a and the storage node contact. Each plug 50b is formed. The bit line contact plug 50a is connected to the drain junction 45a, and the storage node contact plug 50b is connected to the source junction 45b.

In the above, since the bit line node region of the second photoresist pattern 70 is opened, the portion where the storage node contact plug 50b is formed is covered, so that the bit line contact plug 50a is a bit line contact. The polysilicon layer 50 is formed only in the hole 49a, and the storage node contact plug 50b is formed to protrude upward as well as inside the storage node contact hole 49b. Here, the protrusion of the storage node contact plug 50b corresponds to the second storage node contact plug 30 shown in FIG. 1F when compared with the conventional device. Meanwhile, an open portion of the second photoresist pattern 70 is defined as a bit line node region. When the meaning of the "bit line node region" is accurately expressed, the neighboring conductive layer, for example, the storage node contact plug 50b, is defined. And a space in which the insulator will be filled so that the bit lines can be sufficiently electrically insulated.

Referring to FIG. 2D, the second photoresist pattern 70 is removed and a second insulating layer 51 is formed on the entire structure. A chemical mechanical polishing process is performed to flatten the second insulating layer 51, the storage node contact plug 50b, and a portion of the first insulating layer 47. A third photoresist pattern 52 is formed on the planarized surface to open an area where the bit line including the bit line contact plug 50a is to be formed. In the etching process using the third photoresist pattern 52 as an etching mask, the second insulating layer 51 is etched until the bit line contact plug 50a is exposed to form the bit line damascene pattern 53.

In the above description, the sidewalls of the bit line damascene pattern 53 may be formed of the second insulating layer 51, and the second insulation layer 51 may also be formed on the sidewalls of the damascene pattern 53 of the bit line contact plug 50a. This thickness remains to allow electrical isolation between the storage node contact plug 50b and the bit lines to be formed later. The second insulating layer 51 is formed using an oxide-based material such as BPSG, TEOS, USG, or HDP.

2E and 2F, the third photoresist pattern 52 is removed, and the bit line spacers 56 are formed on sidewalls of the bit line damascene pattern 53. The bit line 54 is formed in the bit line damascene pattern 53 on which the bit line spacer 56 is formed. The bit line hard mask layer 55 is formed on the bit line 54.

In the above, the bit line 54 is formed by an etch back process after depositing a conductive layer material, for example, polyside, tungsten, aluminum, etc., by adjusting the etch back process target. 54. The top surface is positioned below the top surface of the bit line damascene pattern 53 so that a hole having a predetermined depth, for example, a depth of 100 to 1000 mm is formed, and the bit line hard mask layer 55 is formed in the hole. ) To form. The bit line hard mask layer 55 is formed on the bit line 54 by a dry etch back process or a chemical mechanical polishing process after depositing a nitride-based material to a thickness of 200 to 2000 microns. The bit line spacer 56 is formed by a spacer etching process after depositing a nitride-based material to a thickness of 100 ~ 1000Å.

Thereafter, the capacitor forming step, the wiring forming step, and the like are performed according to a general step to complete the semiconductor device.

As described above, the present invention reduces the risk that may occur during the self-aligned contact etching process because the self-aligned contact etching process is performed only once, and applies the patterning process instead of the chemical mechanical polishing process when forming the contact plug. Not only does not need to form a thick hard mask layer, but also makes it easy to process the word line patterning process, and also applies a damascene method to form a bit line, and the storage node contact plug has a double structure. Since it is not formed, it is possible to simplify the process and improve plug resistance characteristics.

Claims (12)

Providing a semiconductor substrate including a word line surrounded by a word line hard mask layer and a word line spacer, and a drain and a source junction; Forming a bit line contact hole and a storage node contact hole by etching a portion of the first insulating layer over the entire first insulating layer; Forming a polysilicon layer over the whole, and then etching the polysilicon layer of the bit line contact hole portion to form a bit line contact plug and a storage node contact plug, respectively; Forming a second insulating layer on the entire structure, and then polishing and planarizing the second insulating layer, the storage node contact plug, and a portion of the first insulating layer; Etching a portion of the second insulating layer to form a bit line damascene pattern to which the bit line contact plug is exposed; And And forming a bit line and a bit line hard mask layer inside the bit line damascene pattern. The method of claim 1, The bit line contact hole and the storage node contact hole are formed by etching the first insulating layer by a self-aligned contact etching process. The method of claim 1, The polysilicon layer is a method of manufacturing a semiconductor device, characterized in that the surface is planarized by a dry etch back process or a chemical mechanical polishing process after deposition. The method of claim 1, The bit line contact plug and the storage node contact plug may have the bit line node region open, and the portion where the storage node contact plug is formed may be etched using the photoresist pattern to cover the polysilicon layer. And etching until the hard mask layer is exposed. The method according to claim 1 or 4, The bit line contact plug is formed only in the bit line contact hole. The method according to claim 1 or 4, And the storage node contact plug is formed to protrude upward as well as inside the storage node contact hole. The method of claim 1, The second insulating layer is a method of manufacturing a semiconductor device, characterized in that formed using an oxide-based material such as BPSG, TEOS, USG, HDP. The method of claim 1, The bit line is a method of manufacturing a semiconductor device, characterized in that the conductive material such as polyside, tungsten, aluminum formed on the entire structure including the damascene pattern and then formed by an etch back process. The method of claim 8, The etch back process is a method of manufacturing a semiconductor device, characterized in that to form a hole having a depth of 100 ~ 1000Å in the bit line damascene pattern The method of claim 1, The bit line hard mask layer is formed on the bit line by depositing a nitride-based material to a thickness of 200 ~ 2000Å and a dry etch back process or a chemical mechanical polishing process. The method of claim 1, And forming a bit line spacer on sidewalls of the bit line damascene pattern. The method of claim 11, The bit line spacer is a method of manufacturing a semiconductor device, characterized in that the nitride-based material is deposited to a thickness of 100 ~ 1000Å by a spacer etching process.