KR100307968B1 - Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly - Google Patents
Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly Download PDFInfo
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- KR100307968B1 KR100307968B1 KR1019990026394A KR19990026394A KR100307968B1 KR 100307968 B1 KR100307968 B1 KR 100307968B1 KR 1019990026394 A KR1019990026394 A KR 1019990026394A KR 19990026394 A KR19990026394 A KR 19990026394A KR 100307968 B1 KR100307968 B1 KR 100307968B1
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 57
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- UZPZYFDULMKDMB-UHFFFAOYSA-N 1,2-dichloro-3,4-dimethylbenzene Chemical group CC1=CC=C(Cl)C(Cl)=C1C UZPZYFDULMKDMB-UHFFFAOYSA-N 0.000 claims 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 1
- 239000008096 xylene Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 15
- 230000008021 deposition Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
본 발명은 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법에 관한 것으로, 이 공정은 반도체기판에 게이트전극 및 소스/드레인 접합 영역을 갖는 트랜지스터를 형성하고, 게이트전극 상부 및 측벽에 형성된 절연막 사이에 드러난 소스/드레인 접합 영역에 연결되는 플러그폴리를 형성하고, 플러그폴리가 형성되지 않는 트랜지스터의 공간에 게이트전극 상부면이 드러나도록 절연막을 매립하고, 상기 결과물 상부면에 비트라인 식각 공정시 식각 손상을 줄이기 위하여 화학기상증착법으로 산화물질을 증착하여 제 1층간절연막을 형성한 후에 고밀도 플라즈마 공정으로 산화물질을 증착하여 플러그폴리가 형성되지 않는 부위의 표면을 평탄화하는 제 2층간절연막을 형성하고, 제 2층간절연막 및 제 1층간절연막을 식각해서 하부의 플러그폴리의 상부면이 개방되는 콘택홀을 형성한 후에 도전물질을 채워넣고 이를 패터닝하여 비트라인을 형성한다. 이에 따라, 본 발명은 플러그폴리가 형성된 하부 구조물의 토포로지에 의해 층간절연막 사이에 발생하는 홈이 사라지게 되어 비트라인의 브릿지 및 식각 손상을 막아준다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device having a plug poly. The process includes forming a transistor having a gate electrode and a source / drain junction region on a semiconductor substrate and exposing the insulating film formed on the gate electrode and the sidewalls. Form a plug poly connected to the source / drain junction region, embed an insulating film so that the gate electrode is exposed in the space of the transistor where the plug poly is not formed, and reduce the etching damage during the bit line etching process on the upper surface of the resultant. In order to form a first interlayer insulating film by depositing an oxide material by chemical vapor deposition, and then depositing an oxide material by a high density plasma process to form a second interlayer insulating film to planarize the surface of the portion where the plug poly is not formed, and to form a second interlayer insulating film. The insulating film and the first interlayer insulating film are etched to form a lower plug poly phase. After forming the contact hole opening the side surface is filled with a conductive material and patterned to form a bit line. Accordingly, in the present invention, the grooves generated between the interlayer insulating layers disappear by the topology of the lower structure in which the plug poly is formed, thereby preventing the bridge and the etching damage of the bit line.
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로서, 특히 플러그폴리를 형성한 후에 하부 토포로지에 의해 플러그폴리가 형성되지 않는 게이트전극 사이의 층간 절연막을 완만하게 하여 셀 사이의 비트라인의 브릿지를 방지할 수 있는 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, after forming the plug poly, the interlayer insulating film between the gate electrodes where the plug poly is not formed by the lower topologies is smoothed to prevent the bridge of the bit lines between the cells. It relates to a method for forming an interlayer insulating film of a semiconductor device having a plug poly.
최근의 반도체 장치는 디바이스가 고집적화됨에 따라 메모리 셀 크기가 점점 감소되면서 워드 라인과 커패시터 콘택, 비트라인과 커패시터 콘택의 마진이 점점 작아져 커패시터 콘택을 더욱 작게 형성해야만 한다.In recent semiconductor devices, as the device density increases, the memory cell size gradually decreases, so that the margins of the word line and capacitor contacts, the bit line and the capacitor contacts become smaller, and thus the capacitor contacts must be made smaller.
한편, 반도체 집적회로가 고집적화됨에 따라 다수의 배선층 또는 콘택홀 사이의 미스얼라인 마진(mis-align margin)이 점점 줄어들고 있다. 더욱이, 반도체 메모리셀과 같이 디자인 룰(design rule)에 여유가 없고 같은 형태의 패턴이 반복되는 경우, 콘택홀을 자기정렬(self-align) 방식으로 형성함으로써 메모리셀의 면적을 축소시키는 방법이 연구개발되었다. 이는 주변구조물의 단차를 이용하여 콘택홀을 형성하는 것으로, 주변구조물의 높이, 콘택홀이 형성될 절연물질의 두께 및 식각방법등에 의해 다양한 크기의 콘택홀을 마스크 사용없이 얻을 수 있기 때문에 고집적화에 의해 미소화되는 반도체장치의 실현에 적합한 방법으로 사용된다.Meanwhile, as semiconductor integrated circuits are highly integrated, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. Developed. The contact hole is formed by using the step of the surrounding structure. The contact hole of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material on which the contact hole is to be formed, and the etching method. It is used in a method suitable for realizing a semiconductor device to be micronized.
한편, 상기 기판의 접합 영역에 연결되는 수직 배선을 마스크 공정없이 형성할 수 있는 플러그폴리(plug poly) 공정 또한, 고직접 반도체장치에 주로 적용되고있는 기술이다. 이 플러그폴리 공정은 식각 배리어 물질을 이용한 셀프 얼라인 콘택 방식으로서, 셀프얼라인 콘택홀을 실시하고 난 뒤에 콘택홀을 매립할 도전체를 증착한다. 그리고, 플러그폴리를 위한 도전체를 증착하고 나서 콘택홀 부위만 이를 남겨놓기 위하여 상부의 도전체는 선택적으로 제거해야 하는데, 이 방법으로는 전면 식각 방법과 CMP(Chemical Mechanical Polishing) 방법이 있다.On the other hand, a plug poly process that can form a vertical wiring connected to the junction region of the substrate without a mask process is also a technique that is mainly applied to high direct semiconductor devices. The plug-poly process is a self-aligned contact method using an etch barrier material, which deposits a conductor to fill a contact hole after the self-aligned contact hole is performed. After depositing the conductor for the plug poly, the upper conductor must be selectively removed in order to leave only the contact hole area. The methods include a front etching method and a chemical mechanical polishing (CMP) method.
그런데, 글로벌 단차를 확보하기 위하여 0.18㎛ 이하의 기술에서 특히 CMP 기술을 주로 사용하고 있다. CMP를 이용할 경우 하부 게이트전극을 배리어로 사용하는 경우와 층간절연막인 산화막을 남겨 놓은 상태로 CMP 공정을 실시하는 경우 두가지가 있다. 후자의 경우는 후속 공정에서 비트라인이 될 도프트 폴리실리콘이 변형되기 때문에 사용상 문제점이 있다.However, in order to secure a global step, the CMP technology is mainly used in the technology of 0.18 μm or less. When using CMP, there are two cases in which the lower gate electrode is used as a barrier and the CMP process is performed with the oxide layer, which is an interlayer insulating film, left. In the latter case, there is a problem in use because the doped polysilicon to be a bit line is deformed in a subsequent process.
도 1a 내지 도 1c는 종래 기술에 의한 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법을 설명하기 위한 공정 순서도이다.1A to 1C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the prior art.
이를 참조하면, 종래 플러그폴리의 제조 방법은 도 1a에 도시된 바와 같이 필드산화막(12)이 형성된 반도체기판(10)에 게이트산화막(14)과, 게이트 전극 및 그 측벽에 질화막을 사용한 스페이서 절연막(24)을 형성하고, 불순물 이온 주입을 하여 소스/드레인 영역(26)을 형성한다. 여기서, 게이트 전극은 도프트 폴리실리콘(16)과, 텅스텐실리사이드(18), 버퍼 산화막(20) 및 마스크용 질화막(22)이 적층된 구조를 갖는다.Referring to this, a conventional method of manufacturing a plug poly is a spacer insulating film using a gate oxide film 14 on a semiconductor substrate 10 on which a field oxide film 12 is formed, a nitride film on a gate electrode, and sidewalls thereof, as shown in FIG. 1A. 24 and impurity ion implantation to form source / drain regions 26. Here, the gate electrode has a structure in which a doped polysilicon 16, a tungsten silicide 18, a buffer oxide film 20, and a mask nitride film 22 are stacked.
그 다음, 스페이서 형성시 기판 표면의 게이트산화막(14)이 함께 식각되어 게이트 전극의 스페이서에 의해 셀프 얼라인되면서 기판의 활성 영역이 노출되는개구부가 형성되는데, 이러한 개구부에 도프트 폴리실리콘을 증착하고 이를 평탄화하거나 전면식각 공정을 이용하여 게이트전극 상부 절연막(24)이 드러나도록 상기 도포트 폴리실리콘을 연마함으로써 플러그폴리(28)를 형성한다.Then, when the spacer is formed, the gate oxide layer 14 on the surface of the substrate is etched together to form an opening through which the active region of the substrate is exposed while self-aligning by the spacer of the gate electrode. The plug poly 28 is formed by polishing the doped polysilicon so that the gate insulating layer 24 is exposed by planarization or a front surface etching process.
그리고, 플러그폴리(28)가 형성되지 않은 게이트전극 사이의 공간을 매립하기 위하여 절연막(30)을 증착한다.Then, the insulating film 30 is deposited to fill the space between the gate electrodes where the plug poly 28 is not formed.
그 다음, 도 1b에 도시된 바와 같이, 상기 결과물 상부에 USG(Undoped Silicate Glass), BPSG(BoroPhospho Silicate Glass), TEOS(Tetra - Etly - Ortho - Silicate) 중에서 선택한 막질을 사용하여 층간절연막(32)을 형성하고, 이 막내에 플러그폴리(28)의 상부면이 노출되는 콘택홀(도시하지 않음)을 형성하고 다시 2차의 도프트 폴리실리콘(34)을 증착한다.Next, as shown in FIG. 1B, an interlayer insulating layer 32 is formed on the resultant layer using a film selected from USG (Undoped Silicate Glass), BPSG (BoroPhospho Silicate Glass), and TEOS (Tetra-Etly-Ortho-Silicate). And a contact hole (not shown) in which the top surface of the plug poly 28 is exposed is formed in this film, and the second doped polysilicon 34 is deposited again.
그 다음, 도 1c에 도시된 바와 같이 상기 도프트 폴리실리콘(34)을 패터닝하여 플러그폴리(28)와 연결되는 수직 배선인 비트라인(34')을 형성한다.Next, as shown in FIG. 1C, the doped polysilicon 34 is patterned to form a bit line 34 ′, which is a vertical line connected to the plug poly 28.
상기와 같은 종래 기술에 의한 반도체소자의 플러그폴리 제조 공정은 게이트전극을 식각 배리어로 사용할 경우 폴리실리콘 사이의 브릿지를 방지하기 위하여 산화 슬러리(slurry)를 사용하게 된다. 이 산화 슬러리는 마스크 질화막(22) 및 폴리실리콘층의 식각 비율이 절연막(30)보다 적기 때문에 플러그폴리(28)가 형성되지 않은 게이트전극 사이의 절연막(30) 상부의 층간절연막(32)이 약간 밑으로 쳐져 홈(a)이 발생하게 된다.In the plug poly fabrication process of the semiconductor device according to the related art, an oxide slurry is used to prevent a bridge between polysilicon when the gate electrode is used as an etching barrier. Since the etch rate of the mask nitride film 22 and the polysilicon layer is smaller than that of the insulating film 30, the oxide slurry has a slight interlayer insulating film 32 on the insulating film 30 between the gate electrodes on which the plug poly 28 is not formed. The groove (a) is caused to hit down.
이러한 층간절연막(32)의 홈(a)에는 이후 비트라인의 재료인 도프트 폴리실리콘의 잔여물이 남아 있게 된다. 이를 완전히 제거하기 위하여 과도한 식각을 진행하게 되면 폴리실리콘층 및 층간절연막의 손상을 수반하게 되고 이로 인해 비트라인 사이의 브릿지를 유발하여 반도체소자의 수율을 저하시키게 된다.Residues of doped polysilicon, which is a material of the bit line, remain in the groove a of the interlayer insulating layer 32. Excessive etching in order to completely remove this is accompanied by damage to the polysilicon layer and the interlayer insulating film, thereby causing the bridge between the bit line to reduce the yield of the semiconductor device.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여, 화학기상증착법으로 산화 물질을 얇게 증착하고 고밀도 플라즈마방식으로 산화막을 증착하여 층간절연막을 형성함으로써 플러그폴리가 형성된 하부 구조물의 토포로지에 의해 발생된 층간절연막의 홈을 제거하여 비트라인 형성시 식각 손상을 보상하면서 비트라인 사이의 브릿지를 방지할 수 있는 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법을 제공하는데 있다.An object of the present invention is to solve the problems of the prior art as described above, by depositing a thin oxide material by chemical vapor deposition and by depositing an oxide film by a high density plasma method to form an interlayer insulating film to the topology of the lower structure formed with plug poly The present invention provides a method for forming an interlayer insulating film of a semiconductor device having a plug poly that can prevent the bridge between the bit lines while compensating for the etching damage when the bit line is formed by removing the groove of the interlayer insulating film.
도 1a 내지 도 1c는 종래 기술에 의한 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법을 설명하기 위한 공정 순서도,1A to 1C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the prior art;
도 2a 내지 도 2c는 본 발명에 따른 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법을 설명하기 위한 공정 순서도.2A to 2C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the present invention;
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 실리콘 기판 12: 필드 산화막10 silicon substrate 12 field oxide film
14: 게이트산화막 16: 도프트 폴리실리콘층14: gate oxide film 16: doped polysilicon layer
18: 텅스텐 실리사이드막 20: 버퍼용 산화막18: tungsten silicide film 20: buffer oxide film
22: 마스크용 질화막 24: 스페이서 및 절연막22: nitride film for mask 24: spacer and insulating film
26: 소스/드레인 접합 영역 28: 플러그 폴리26: source / drain junction area 28: plug pulley
30: 게이트전극 사이의 절연막 40: 제 1층간절연막30: insulating film between gate electrodes 40: first interlayer insulating film
42: 제 2층간절연막42: second interlayer insulating film
상기 목적을 달성하기 위하여 본 발명은 하부 반도체소자와 상부 배선을 수직 연결하도록 게이트전극 사이에 기판의 접합 영역에 연결되는 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법에 있어서, 반도체 기판 상부에 게이트산화막, 게이트전극 및 소스/드레인 접합영역을 갖는 트랜지스터를 형성하는 단계와, 트랜지스터의 게이트전극 상부 및 측벽에 형성된 절연막 사이에 드러난 소스/드레인 접합 영역에 연결되는 플러그폴리를 형성하는 단계와, 플러그폴리가 형성되지 않는 트랜지스터의 공간에 게이트전극 상부면이 드러나도록 절연막을 매립하는 단계와, 결과물 상부면에 화학기상증착법으로 절연 물질을 증착하여 제 1층간절연막을 형성하는 단계와, 제 1층간절연막 상부에 고밀도 플라즈마 공정으로 산화물질을 증착하여 제 2층간절연막을 형성하는 단계와, 제 2층간절연막 및 제 1층간절연막을 식각해서 하부의 플러그폴리의 상부면이 개방되는 콘택홀을 형성한 후에 도전물질을 채워넣고 이를 패터닝하여 비트라인을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film of a semiconductor device having a plug poly connected to a junction region of a substrate between gate electrodes so as to vertically connect a lower semiconductor device and an upper wiring. Forming a transistor having a gate electrode and a source / drain junction region, forming a plug poly connected to the source / drain junction region exposed between the insulating film formed on the sidewall and the gate electrode of the transistor; Embedding an insulating film so that a gate electrode top surface is exposed in a space of a transistor which is not formed, and depositing an insulating material on the upper surface of the resultant by chemical vapor deposition to form a first interlayer insulating film; Deposition of oxide layer by high density plasma process Forming a film, and forming a contact line by etching the second interlayer insulating film and the first interlayer insulating film to form a contact hole in which the upper surface of the lower plug poly is opened, and then filling and patterning the conductive material to form a bit line. do.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 하며, 본 실시예에서는 종래 기술과 동일한 부분에 대해서는 동일 도면부호를 사용하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and in this embodiment, the same reference numerals will be used for the same parts as the prior art.
도 2a 내지 도 2c는 본 발명에 따른 플러그폴리를 갖는 반도체장치의 층간절연막 형성방법을 설명하기 위한 공정 순서도이다.2A to 2C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the present invention.
이를 참조하면, 본 발명의 제조 방법은 도 2a에 도시된 바와 같이, 반도체기판으로서 실리콘기판(10)에 소자 분리 공정을 실시하여 필드산화막(12)을 형성한 후에, 게이트산화막(14)을 형성한다. 그리고, 게이트산화막(14) 상부에 다층의 게이트 도전층으로서 도프트 폴리실리콘(16), 텅스텐 실리사이드(18), 버퍼 산화막(20) 및 마스크 절연막인 질화막(22)을 순차 적층하고 게이트 마스크를 사용한 사진 및 식각 공정을 실시하여 순차 적층된 막들(22,20,18,16)을 셀프 얼라인하게 패터닝하여 게이트 전극을 형성한다. 그리고, 게이트전극 측면에 절연막으로 이루어진 스페이서(24)를 형성하고, 불순물 주입 공정을 실시하여 게이트 전극 사이에 드러난 기판의 활성 영역에 소스/드레인 접합 영역(26)을 형성한다.Referring to this, as shown in FIG. 2A, the gate oxide film 14 is formed after the field oxide film 12 is formed by performing a device isolation process on the silicon substrate 10 as a semiconductor substrate. do. The doped polysilicon 16, the tungsten silicide 18, the buffer oxide film 20, and the nitride film 22 serving as the mask insulating film were sequentially stacked on the gate oxide film 14 as a multilayer gate conductive layer, and a gate mask was used. Photographs and etching processes are performed to pattern the stacked layers 22, 20, 18, and 16 in a self-aligned manner to form a gate electrode. A spacer 24 made of an insulating film is formed on the side of the gate electrode, and an impurity implantation process is performed to form the source / drain junction region 26 in the active region of the substrate exposed between the gate electrodes.
그 다음, 반도체소자의 게이트전극을 둘러싼 절연막(24) 사이에 도프트 폴리실리콘을 증착하고 이를 CMP로 연마하여 불순물 접합 영역인 소스/드레인 영역(26)과 연결된 플러그폴리(28)를 형성한다. 여기서, 플러그폴리(28)의 도프트 폴리실리콘은 500∼550℃에서 도펀트로서 인을 주입하되 그 농도를 0.1E20∼1.5E20atmos/㎤로 한다. 그리고, 플러그폴리(28)가 형성되지 않은 게이트전극 사이에 절연막(30)을 매립함으로써 기판 표면을 평탄화한다.Next, a doped polysilicon is deposited between the insulating layers 24 surrounding the gate electrode of the semiconductor device and polished with CMP to form a plug poly 28 connected to the source / drain region 26, which is an impurity junction region. Here, the doped polysilicon of the plug poly 28 is injected with phosphorus as a dopant at 500 to 550 캜, and its concentration is 0.1E20 to 1.5E20 atmos / cm 3. Then, the substrate surface is planarized by filling the insulating film 30 between the gate electrodes where the plug poly 28 is not formed.
이어서, 도 2b에 도시된 바와 같이, 상기 결과물에 고온의 화학기상증착법으로 산화계 물질을 150∼300Å의 두께로 증착하여 제 1층간절연막(40)을 형성한다. 여기서, 제 1층간절연막(40)의 물질은 저압 화학기상증착법으로 퍼니스(furnace)에서 650∼750℃의 온도 범위에서 증착된 TEOS막과, 퍼니스에서 750∼800℃의 온도 범위 조건하에 사일렌 가스(SiH4) 내지 디클로로 사일렌(SiH2Cl2) 가스를 이용해 증착된한 고온 산화막(high temperature oxide) 중에서 어느 하나를 선택해서 형성한다. 아니면, 제 1층간절연막(40)은 산화계 물질이 아닌 질화막으로 이루어질 수도 있는데, 이때 질화막의 증착은 저압 화학기상증착법으로 700∼800℃의 온도 범위에서 진행된다.Subsequently, as shown in FIG. 2B, an oxide-based material is deposited to the resultant at a thickness of 150 to 300 kPa by a high temperature chemical vapor deposition method to form a first interlayer insulating film 40. Here, the material of the first interlayer insulating film 40 is a TEOS film deposited at a temperature range of 650 to 750 ° C. in a furnace by low pressure chemical vapor deposition, and a silica gas under a temperature range of 750 to 800 ° C. in a furnace. It is formed by selecting any one of the high temperature oxide deposited by using (SiH 4 ) to dichlorosilane (SiH 2 Cl 2 ) gas. Alternatively, the first interlayer insulating film 40 may be formed of a nitride film instead of an oxidizing material. In this case, the deposition of the nitride film is performed in a temperature range of 700 to 800 ° C. by low pressure chemical vapor deposition.
상기 제 1층간절연막(40)의 역할은 이후 고밀도 플라즈마(high density plasma) 산화 공정시 실리콘 기판에 플라즈마 손상을 주게 되어 게이트 산화막 등에 전기적 손상을 주게 되는 것을 방지하기 위한 완충 기능을 한다.The first interlayer insulating film 40 plays a buffer function to prevent electrical damage to the gate oxide film by causing plasma damage to the silicon substrate during a high density plasma oxidation process.
이어서, 상기 제 1층간절연막(40) 상부에 하부 구조의 불균일한 토포토지로 인한 비트라인의 브릿지를 방지하기 위하여 고밀도 플라즈마 방식으로 산화막을 증착하여 제 2층간절연막(42)을 형성한다. 이때, 제 2층간절연막(42)의 증착 두께를 500∼1500Å로 한다. 또한, 제 2층간절연막(42)의 산화막 증착은 고밀도 플라즈마 공정의 바이어스 전력을 1∼3kW, 소스 전력을 3∼5kW로 하여 사일렌 가스를 50∼150sccm, O2를 100∼200sccm, Ar을 50∼150sccm으로 흘려주어 형성한다.Subsequently, the second interlayer insulating layer 42 is formed by depositing an oxide film on the first interlayer insulating layer 40 by a high density plasma method in order to prevent the bridge of the bit line due to the uneven topography of the lower structure. At this time, the deposition thickness of the second interlayer insulating film 42 is set to 500 to 1500 kPa. In the oxide film deposition of the second interlayer insulating film 42, the bias power of the high-density plasma process is 1 to 3 kW, the source power is 3 to 5 kW, and the silica gas is 50 to 150 sccm, the O 2 is 100 to 200 sccm, and the Ar is 50. It is formed by flowing at -150 sccm.
여기서, 플라즈마 방식으로 증착된 제 2층간절연막(42)은 게이트전극 부위에서 산 형태(b)로 나머지 부위에서 평평한 모양(c)을 갖는다. 이러한 제 2층간절연막(42)의 토포로지는 이후 비트라인의 패터닝 공정시 식각 잔여물을 남기지 않도록 하는 역할을 한다.Here, the second interlayer insulating film 42 deposited by the plasma method has a flat shape (c) at the remaining portion in the form of acid (b) at the gate electrode portion. The topology of the second interlayer insulating layer 42 serves to prevent etch residues in the subsequent bit line patterning process.
그 다음, 도 2c에 도시된 바와 같이 하부의 플러그폴리(28)를 개방하기 위한 마스크를 이용한 사진 및 식각 공정으로 상기 적층된 제 2 및 제 1층간절연막(42,40)을 식각하여 플러그폴리(28)의 상부면이 개방되는 콘택홀(도시하지 않음)을 형성한다. 그리고, 기판 전면에 도전물질로서 도프트 폴리실리콘을 증착하고 비트라인 마스크를 이용한 사진 및 식각 공정을 진행하여 폴리실리콘층을 패터닝해서 하부의 플러그폴리와 연결되는 비트라인(44)을 형성한다.Next, as illustrated in FIG. 2C, the stacked second and first interlayer insulating layers 42 and 40 are etched by a photo and etching process using a mask for opening the lower plug poly 28. A contact hole (not shown) is formed in which the upper surface of 28 is opened. Then, doped polysilicon is deposited on the entire surface of the substrate, and a photolithography and etching process using a bitline mask is performed to pattern the polysilicon layer to form a bitline 44 connected to the lower plug poly.
본 발명의 제조 공정에 있어서, 제 1층간절연막은 상술한 고온 산화막 대신에 저압 화학기상증착법으로 증착된 질화막을 사용할 수 있다.In the manufacturing process of the present invention, the first interlayer insulating film may be a nitride film deposited by a low pressure chemical vapor deposition method instead of the above-described high temperature oxide film.
상기한 바와 같이 본 발명은, 고밀도 플라즈마방식으로 산화막을 증착하여게이트전극이 형성된 지역에서는 산 형태를 가지며 그렇지 않은 부위에서는 평평한 증착 특성을 갖는 층간절연막을 형성함으로써 플러그폴리가 형성된 하부 구조물의 토포로지에 의해 발생된 층간절연막의 홈을 제거하여 비트라인 형성시 비트라인 사이의 브릿지를 방지할 수 있다.As described above, the present invention, by depositing the oxide film in a high-density plasma method to form an interlayer insulating film having an acid form in the region where the gate electrode is formed, and the flat deposition characteristics in the other region to the topology of the lower structure formed with plug poly By removing the groove of the interlayer insulating film generated by this, it is possible to prevent the bridge between the bit lines when forming the bit line.
또한, 본 발명은 고밀도 플라즈마 방식의 산화막 증착전에 화학기상증착법으로 산화 물질을 얇게 증착함으로써 플라즈마 산화 공정에 의해 기판 내지 게이트산화막이 손생되는 것을 하부 산화막이 막아주어 반도체소자의 수율을 높일 수 있다.In addition, the present invention can increase the yield of the semiconductor device by preventing the lower oxide film from damaging the substrate or the gate oxide film by the plasma oxidation process by thinly depositing the oxidized material by chemical vapor deposition before the deposition of the oxide film of the high density plasma method.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990026394A KR100307968B1 (en) | 1999-07-01 | 1999-07-01 | Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990026394A KR100307968B1 (en) | 1999-07-01 | 1999-07-01 | Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly |
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| KR20010008518A KR20010008518A (en) | 2001-02-05 |
| KR100307968B1 true KR100307968B1 (en) | 2001-11-01 |
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| KR100745054B1 (en) * | 2001-06-19 | 2007-08-01 | 주식회사 하이닉스반도체 | Method for forming contact plug in semiconductor Device |
| KR100484258B1 (en) * | 2001-12-27 | 2005-04-22 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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