KR20010008518A - Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly - Google Patents

Abstract

PURPOSE: A method for forming an interfacial insulating layer of a semiconductor device having a plug-poly is provided to prevent a bridge of bit line between cells by smoothing an interfacial insulating layer between the gate electrodes not including a plug-poly. CONSTITUTION: A gate oxide layer(14), a gate electrode and a source/drain junction area(26) are included in a transistor. The transistor is formed on a semiconductor substrate(10). A plug-poly(28) is formed to be connected to a source/drain junction area exposed between the insulation layers. The insulating layer is formed on an upper part of a gate electrode and a gate electrode sidewall. The insulating layer is buried in a transistor space not including the plug-poly so as to expose the upper part of the gate electrode. An insulation material is deposited on the resultant material by using CVD, thereby forming the first interfacial insulation layer(40). An oxide material is deposited on the first interfacial insulating layer by means of a high-density plasma process, thereby forming the second interfacial insulation layer(42). A contact hole for opening an upper part of a lower plug-poly is formed by etching the second and first interfacial insulation layers, a conductive material is inserted in the contact hole and patterned, thereby forming a bit line.

Description

Method of forming interlevel dielectric layers of semiconductor device provided with plug-poly}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, after forming the plug poly, the interlayer insulating film between the gate electrodes where the plug poly is not formed by the lower topologies is smoothed to prevent the bridge of the bit lines between the cells. It relates to a method for forming an interlayer insulating film of a semiconductor device having a plug poly.

In recent semiconductor devices, as the device density increases, the memory cell size gradually decreases, so that the margins of the word line and capacitor contacts, the bit line and the capacitor contacts become smaller, and thus the capacitor contacts must be made smaller.

Meanwhile, as semiconductor integrated circuits are highly integrated, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. Developed. The contact hole is formed by using the step of the surrounding structure. The contact hole of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material on which the contact hole is to be formed, and the etching method. It is used in a method suitable for realizing a semiconductor device to be micronized.

On the other hand, a plug poly process capable of forming a vertical wiring connected to the junction region of the substrate without a mask process is also a technique mainly applied to a high direct semiconductor device. The plug-poly process is a self-aligned contact method using an etch barrier material, which deposits a conductor to fill a contact hole after the self-aligned contact hole is performed. After depositing the conductor for the plug poly, the upper conductor must be selectively removed in order to leave only the contact hole area. The methods include a front etching method and a chemical mechanical polishing (CMP) method.

However, in order to secure a global step, the CMP technology is mainly used in the technology of 0.18 μm or less. When using CMP, there are two cases in which the lower gate electrode is used as a barrier and the CMP process is performed with the oxide layer, which is an interlayer insulating film, left. In the latter case, there is a problem in use because the doped polysilicon to be a bit line is deformed in a subsequent process.

1A to 1C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the prior art.

Referring to this, a conventional method of manufacturing a plug poly is a spacer insulating film using a gate oxide film 14 on a semiconductor substrate 10 on which a field oxide film 12 is formed, a nitride film on a gate electrode, and sidewalls thereof, as shown in FIG. 1A. 24 and impurity ion implantation to form source / drain regions 26. Here, the gate electrode has a structure in which a doped polysilicon 16, a tungsten silicide 18, a buffer oxide film 20, and a mask nitride film 22 are stacked.

Then, when the spacer is formed, the gate oxide film 14 on the surface of the substrate is etched together to form an opening through which the active region of the substrate is exposed while self-aligning by the spacer of the gate electrode. The doped polysilicon is deposited on the opening. The plug poly 28 is formed by polishing the doped polysilicon so that the gate insulating layer 24 is exposed by planarization or a front surface etching process.

Then, the insulating film 30 is deposited to fill the space between the gate electrodes where the plug poly 28 is not formed.

Next, as shown in FIG. 1B, an interlayer insulating layer 32 is formed on the resultant layer using a film selected from USG (Undoped Silicate Glass), BPSG (BoroPhospho Silicate Glass), and TEOS (Tetra-Etly-Ortho-Silicate). And a contact hole (not shown) in which the top surface of the plug poly 28 is exposed is formed in this film, and the second doped polysilicon 34 is deposited again.

Next, as shown in FIG. 1C, the doped polysilicon 34 is patterned to form a bit line 34 ′, which is a vertical line connected to the plug poly 28.

In the plug poly fabrication process of the semiconductor device according to the related art, an oxide slurry is used to prevent a bridge between polysilicon when the gate electrode is used as an etching barrier. Since the etch rate of the mask nitride film 22 and the polysilicon layer is smaller than that of the insulating film 30, the oxide slurry has a slight interlayer insulating film 32 on the insulating film 30 between the gate electrodes on which the plug poly 28 is not formed. The groove (a) is caused to hit down.

Residues of doped polysilicon, which is a material of the bit line, remain in the groove a of the interlayer insulating layer 32. Excessive etching in order to completely remove this is accompanied by damage to the polysilicon layer and the interlayer insulating film, thereby causing the bridge between the bit line to reduce the yield of the semiconductor device.

An object of the present invention is to solve the problems of the prior art as described above, by depositing a thin oxide material by chemical vapor deposition and by depositing an oxide film by a high density plasma method to form an interlayer insulating film to the topology of the lower structure formed with plug poly The present invention provides a method for forming an interlayer insulating film of a semiconductor device having a plug poly that can prevent the bridge between the bit lines while compensating for the etching damage when the bit line is formed by removing the groove of the interlayer insulating film.

1A to 1C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the prior art;

2A to 2C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the present invention;

* Description of the symbols for the main parts of the drawings *

10 silicon substrate 12 field oxide film

14: gate oxide film 16: doped polysilicon layer

18: tungsten silicide film 20: buffer oxide film

22: nitride film for mask 24: spacer and insulating film

26: source / drain junction area 28: plug pulley

30: insulating film between gate electrodes 40: first interlayer insulating film

42: second interlayer insulating film

In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film of a semiconductor device having a plug poly connected to a junction region of a substrate between gate electrodes so as to vertically connect a lower semiconductor device and an upper wiring. Forming a transistor having a gate electrode and a source / drain junction region, forming a plug poly connected to the source / drain junction region exposed between the insulating film formed on the sidewall and the gate electrode of the transistor; Embedding an insulating film so that a gate electrode top surface is exposed in a space of a transistor which is not formed, and depositing an insulating material on the upper surface of the resultant by chemical vapor deposition to form a first interlayer insulating film; Deposition of oxide layer by high density plasma process Forming a film, and forming a contact line by etching the second interlayer insulating film and the first interlayer insulating film to form a contact hole in which the upper surface of the lower plug poly is opened, and then filling and patterning the conductive material to form a bit line. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and in this embodiment, the same reference numerals will be used for the same parts as the prior art.

2A to 2C are process flowcharts for explaining a method for forming an interlayer insulating film of a semiconductor device having a plug poly according to the present invention.

Referring to this, as shown in FIG. 2A, the gate oxide film 14 is formed after the field oxide film 12 is formed by performing a device isolation process on the silicon substrate 10 as a semiconductor substrate. do. The doped polysilicon 16, the tungsten silicide 18, the buffer oxide film 20, and the nitride film 22 serving as the mask insulating film were sequentially stacked on the gate oxide film 14 as a multilayer gate conductive layer, and a gate mask was used. Photographs and etching processes are performed to pattern the stacked layers 22, 20, 18, and 16 in a self-aligned manner to form a gate electrode. A spacer 24 made of an insulating film is formed on the side of the gate electrode, and an impurity implantation process is performed to form the source / drain junction region 26 in the active region of the substrate exposed between the gate electrodes.

Next, a doped polysilicon is deposited between the insulating layers 24 surrounding the gate electrode of the semiconductor device and polished with CMP to form a plug poly 28 connected to the source / drain region 26, which is an impurity junction region. Here, the doped polysilicon of the plug poly 28 is injected with phosphorus as a dopant at 500 to 550 캜, and its concentration is 0.1E20 to 1.5E20 atmos / cm 3. Then, the substrate surface is planarized by filling the insulating film 30 between the gate electrodes where the plug poly 28 is not formed.

Subsequently, as shown in FIG. 2B, an oxide-based material is deposited to the resultant at a thickness of 150 to 300 kPa by a high temperature chemical vapor deposition method to form a first interlayer insulating film 40. Here, the material of the first interlayer insulating film 40 is a TEOS film deposited at a temperature range of 650 to 750 ° C. in a furnace by low pressure chemical vapor deposition, and a silica gas under a temperature range of 750 to 800 ° C. in a furnace. It is formed by selecting any one of the high temperature oxide deposited by using (SiH ₄ ) to dichlorosilane (SiH ₂ Cl ₂ ) gas. Alternatively, the first interlayer insulating film 40 may be formed of a nitride film instead of an oxidizing material. In this case, the deposition of the nitride film is performed in a temperature range of 700 to 800 ° C. by low pressure chemical vapor deposition.

The first interlayer insulating film 40 plays a buffer function to prevent electrical damage to the gate oxide film by causing plasma damage to the silicon substrate during a high density plasma oxidation process.

Subsequently, the second interlayer insulating layer 42 is formed by depositing an oxide film on the first interlayer insulating layer 40 by a high density plasma method in order to prevent the bridge of the bit line due to the uneven topography of the lower structure. At this time, the deposition thickness of the second interlayer insulating film 42 is set to 500 to 1500 kPa. In the oxide film deposition of the second interlayer insulating film 42, the bias power of the high-density plasma process is 1 to 3 kW, the source power is 3 to 5 kW, and the silica gas is 50 to 150 sccm, the O ₂ is 100 to 200 sccm, and the Ar is 50. It is formed by flowing at -150 sccm.

Here, the second interlayer insulating film 42 deposited by the plasma method has a flat shape (c) at the remaining portion in the form of acid (b) at the gate electrode portion. The topology of the second interlayer insulating layer 42 serves to prevent etch residues in the subsequent bit line patterning process.

Next, as illustrated in FIG. 2C, the stacked second and first interlayer insulating layers 42 and 40 are etched by a photo and etching process using a mask for opening the lower plug poly 28. A contact hole (not shown) is formed in which the upper surface of 28 is opened. Then, doped polysilicon is deposited on the entire surface of the substrate, and a photolithography and etching process using a bitline mask is performed to pattern the polysilicon layer to form a bitline 44 connected to the lower plug poly.

In the manufacturing process of the present invention, the first interlayer insulating film may be a nitride film deposited by a low pressure chemical vapor deposition method instead of the above-described high temperature oxide film.

As described above, the present invention forms an interlayer insulating film having an acid form in a region where a gate electrode is formed by depositing an oxide film by a high density plasma method and a flat deposition characteristic in a region where the gate electrode is formed, thereby forming a top layer of the plug structure formed on the topology. By removing the groove of the interlayer insulating film generated by this, it is possible to prevent the bridge between the bit lines when forming the bit line.

In addition, the present invention can increase the yield of the semiconductor device by preventing the lower oxide film from damaging the substrate or the gate oxide film by the plasma oxidation process by thinly depositing the oxidized material by chemical vapor deposition before the deposition of the oxide film of the high density plasma method.

Claims (6)

A method for forming an interlayer insulating film of a semiconductor device having a plug poly connected to a junction region of a substrate between gate electrodes so as to vertically connect a lower semiconductor element and an upper wiring, Forming a transistor having a gate oxide film, a gate electrode, and a source / drain junction region on the semiconductor substrate; Forming a plug poly connected to a source / drain junction region exposed between an insulating film formed on an upper side of the gate electrode and a sidewall of the transistor; Filling an insulating film so that the upper surface of the gate electrode is exposed in a space of the transistor in which the plug poly is not formed; Depositing an insulating material on the upper surface of the resultant by chemical vapor deposition to form a first interlayer insulating film; Depositing an oxide material on the first interlayer insulating film by a high density plasma process to form a second interlayer insulating film; Etching the second interlayer insulating film and the first interlayer insulating film to form a contact hole in which the upper surface of the lower plug poly is opened, and then filling the conductive material and patterning the bit interlayer insulating film to form a bit line. An interlayer insulating film forming method of a semiconductor device having a plug poly. 2. The method for forming an interlayer insulating film of a semiconductor device having a plug poly according to claim 1, wherein said first interlayer insulating film has a thickness of 150 to 300 kPa. The method of claim 1, wherein the first interlayer insulating film is a high temperature using a TEOS film deposited in a temperature range of 650 ~ 750 ℃ by a low pressure chemical vapor deposition method, and using a xylene gas to dichloro xylene gas at a temperature range of 750 ~ 800 ℃ A method for forming an interlayer insulating film of a semiconductor device having a plug poly, characterized in that any one of an oxide film. The method of claim 1, wherein the first interlayer dielectric film is a nitride film deposited at a temperature in the range of 700 to 800 ° C. by low pressure chemical vapor deposition. 2. The method for forming an interlayer insulating film of a semiconductor device having a plug poly according to claim 1, wherein said second interlayer insulating film has a thickness of 500-1500 GPa. 2. The method of claim 1, wherein the second interlayer dielectric film is formed with a bias power of 1 to 3 kW, a source power of 3 to 5 kW in a high density plasma process, 50 to 150 sccm of silylene gas, 100 to 200 sccm of O ₂ , and Ar. A method of forming an interlayer insulating film of a semiconductor device having a plug poly, characterized in that it is formed by flowing at 50 to 150 sccm.