KR19990030836A - Self-aligning contact hole formation method - Google Patents

Abstract

A method of forming a self-aligned contact hole is disclosed. This method forms a gate oxide film on a semiconductor substrate, and forms a conductive film pattern surrounded by a capping insulating film pattern and a spacer on a predetermined region of the gate oxide film. The nitride layer may be formed using a plasma treatment process using a gas containing nitrogen or a heat treatment process performed in an ammonia gas atmosphere between the gate patterns. Accordingly, an etch stop film having a uniform thickness can be formed on the entire surface of the resultant nitride film, and a phenomenon in which the etch stop film is lifted up when the high density plasma CVD oxide film is formed on the etch stop film can be suppressed.

Description

Self-aligning contact hole formation method

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact hole.

As the degree of integration of semiconductor devices increases, the width and spacing of the wirings become smaller. Accordingly, when contact holes are formed between the wires formed in parallel with each other, a process margin, for example, an alignment margin in a photographic process, is reduced, and contact defects are likely to occur. Recently, a method of forming a self-aligning contact hole capable of improving alignment margin as a method of forming a contact hole of a highly integrated semiconductor device has been proposed.

1 to 3 are cross-sectional views illustrating a method of forming a conventional self-aligned contact hole.

1 is a cross-sectional view for explaining a step of forming the gate pattern 9. First, a gate oxide film 3 is formed on a semiconductor substrate 1, for example, a silicon substrate. Next, a conductive film and a capping insulation layer are sequentially formed on the gate oxide film 3. The conductive layer is formed of a doped polysilicon layer or a polycide layer, and the capping insulating layer is formed of a silicon nitride layer. Subsequently, the capping insulating layer and the conductive layer are successively patterned to form parallel gate patterns 9 that maintain a predetermined distance from each other on the predetermined region of the gate oxide layer 3. Each gate pattern 9 has a structure in which a conductive film pattern 5 and a capping insulating film pattern 7 are sequentially stacked. The conductive layer pattern 5 serves as a gate electrode.

2 is a cross-sectional view for describing a step of forming the spacer 11 and the etch stop layer 13. Specifically, a silicon nitride film is formed on the entire surface of the resultant product on which the gate pattern 9 is formed, and then the silicon nitride film is anisotropically etched to form spacers 11 on sidewalls of the gate pattern 9. In this case, the gate oxide layer 3 between the gate patterns 9 may also be etched to expose the semiconductor substrate 1. Subsequently, an etch stop layer 13, for example, a silicon nitride layer by a CVD process, is formed on the entire surface of the resultant on which the spacer 11 is formed. The etch stop layer 13 is preferably formed to a thin thickness of about 70 ~ 150Å. The silicon nitride film has a different thickness depending on the type of under-layer. In other words, the silicon nitride film formed on the capping insulation layer pattern 7 and the spacer 11 formed of the silicon nitride film has a normal thickness T2, while the silicon nitride film formed on the oxide film or the silicon substrate has the thickness T2. Thinner than the thickness T1. Therefore, when the etch stop layer 13 is formed of a silicon nitride film, a thin silicon nitride film of several tens of micrometers is formed on the semiconductor substrate 1 between the gate patterns 9.

3 is a cross-sectional view for explaining a step of forming the interlayer insulating film 15. In detail, an interlayer insulating layer 15 having excellent characteristic filling a gap on the etch stop layer 13, for example, a high density plasma CVD oxide layer, is formed. In this case, since the high density plasma CVD oxide film is formed in a state where a bias is applied to the semiconductor substrate 1, plasma ions and electrons are trapped at an interface between the etch stop layer 13 and the semiconductor substrate 1. The phenomenon that the etch stop film 13 having a thin thickness T1, particularly the etch stop film 13 formed with a thin thickness T1 over a large area A occurs.

Subsequently, although not illustrated, the interlayer insulating layer 15 is planarized, and then the planarized interlayer insulating layer is patterned to expose the etch stop layer 13 between the gate patterns 9. The exposed etch stop layer 13 is etched to form a self-aligned contact hole exposing the semiconductor substrate 1 between the gate patterns 9.

As described above, according to the related art, a phenomenon in which the etch stop film is lifted up when the interlayer insulating film is formed is generated. As a result, when forming a self-aligned contact hole or a subsequent metal contact hole, particles and abnormal patterns due to the excited etch stop layer are caused.

An object of the present invention is to provide a method for forming a self-aligned contact hole that can eliminate the phenomenon that the etch stop film is lifted.

1 to 3 are cross-sectional views illustrating a method for forming a self-aligned contact hole according to the prior art.

4 to 7 are cross-sectional views illustrating a method of forming a self-aligned contact hole according to the present invention.

In order to achieve the above object, the present invention forms a gate oxide film on a semiconductor substrate. Next, a plurality of gate patterns parallel to each other are formed on a predetermined region of the gate oxide film. Each gate pattern includes a conductive film pattern and a capping insulating film pattern that are sequentially stacked. The conductive layer pattern may be formed of a doped polysilicon layer or a polycide layer, and the capping layer pattern may be formed of a silicon nitride layer. Here, the conductive film pattern serves as a gate electrode. A silicon nitride film is formed on the entire surface of the resultant product on which the plurality of gate patterns are formed, and then anisotropically etched to form a spacer on the sidewall of the gate pattern. When the spacer is formed in this manner, the conductive film pattern corresponding to the gate electrode is completely surrounded by the capping insulating film pattern and the spacer. In addition, when the anisotropic etching process for forming the spacer is performed, the gate oxide layer between the gate patterns may be additionally etched by the overetch, so that an oxide layer thinner than the initial gate oxide layer may remain or the semiconductor substrate may be exposed. have. When the spacer is formed, etch damage is applied to the surface of the semiconductor substrate. Therefore, the resultant spacer is thermally oxidized at a predetermined temperature to remove the etch damage and to form a thin thermal oxide layer on the surface of the semiconductor substrate between the gate patterns. A source / drain region is formed by injecting impurities into the semiconductor substrate between the gate patterns by using the thin thermal oxide film as a screen oxide layer. Then, the surface of the resultant formed source / drain region is cleaned. In this case, the thin thermal oxide film formed between the gate patterns is also etched. Therefore, a semiconductor substrate between the gate patterns may be exposed or a part of the thin thermal oxide film may remain. Next, the surface cleaning result is exposed to a plasma using nitrogen gas and ammonia gas to form a nitride layer on the surface of the thermal oxide film or the exposed semiconductor substrate remaining between the gate patterns. do. The nitride film may be formed by a heat treatment process performed at a temperature of 700 ° C. to 1000 ° C. and an ammonia gas atmosphere instead of the plasma process. An etch stop layer is formed on the entire surface of the resultant nitride film. The etch stop layer may be formed of a material layer having a high etch selectivity, for example, a silicon nitride layer, with respect to an interlayer insulating layer formed in a subsequent process, that is, an oxide layer. At this time, the etch stop layer is preferably formed in a thin thickness of 70 ~ 150Å. When the etch stop layer is formed after the nitride layer is formed between the gate patterns as described above, the etch stop layer deposited on the nitride layer is formed to have the same thickness as the etch stop layer deposited on the gate pattern surface and the spacer surface. Therefore, it is not necessary to form an etch stop film thicker than necessary on the spacer and the gate pattern to form an etch stop film having a predetermined thickness between the gate patterns. Subsequently, a high density plasma CVD oxide film having a high etching selectivity with respect to the interlayer insulating layer, for example, the etch stop layer, is formed on the entire surface of the resultant on which the etch stop layer is formed. In this case, since the etch stop layer formed on the semiconductor substrate between the gate patterns maintains a certain thickness, the nitride film and the etch stop layer maintain a stable adhesive state. In addition, the high density plasma CVD oxide film is excellent in filling a gap having a high aspect ratio. Thus, an interlayer insulating film is formed to completely fill the regions between the gate patterns. Subsequently, the interlayer insulating layer is patterned to expose the etch stop layer between the gate patterns, and the exposed etch stop layer and the underlying nitride layer are continuously etched to expose the semiconductor substrate between the gate patterns. To form.

According to the present invention, the phenomenon that the etch stop film is lifted up when the interlayer insulating film is formed of the high-density plasma CVD oxide film excellent in filling the recesses having a high aspect ratio can be suppressed. Accordingly, self-aligned contact holes suitable for highly integrated semiconductor devices can be realized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view for describing a step of forming the gate pattern 29, the spacer 31, and the nitride film 33. First, a gate oxide film 23 is formed on the semiconductor substrate 21. Next, a conductive film and a capping insulating film are sequentially formed on the gate oxide film 23. Here, the conductive film is formed of a doped polysilicon film or a polyside film. The polyside film is composed of a doped polysilicon film and a refractory metal silicide layer. As the refractory metal silicide film, a tungsten silicide film, a titanium silicide film, a cobalt silicide film, and the like are widely used. The capping insulating layer is preferably formed of a silicon nitride film having a high etching selectivity with respect to the oxide film. Subsequently, the capping insulating layer and the conductive layer are successively patterned to form a plurality of gate patterns 29 parallel to each other on a predetermined region of the gate oxide layer 23. Each of the gate patterns 29 has a structure in which a conductive layer pattern 25 and a capping insulation layer pattern 27 are sequentially stacked. The conductive layer pattern 25 serves as a gate electrode of the MOS transistor. A silicon nitride film is formed on the entire surface of the resultant product on which the gate pattern 29 is formed, and then anisotropically etched to form the spacer 31 on the sidewall of the gate pattern 29. In this case, the gate oxide layer exposed between the gate patterns 29 may be further over-etched to expose the semiconductor substrate 21, or an oxide layer thinner than the initial gate oxide layer may remain. When the spacer 31 is formed, the conductive film pattern 25, that is, the gate electrode, is completely surrounded by the capac insulating film pattern 27 and the spacer 31 as shown in FIG. 4. When the anisotropic etching process for forming the spacer 31 is performed, etch damage is applied to the surface of the semiconductor substrate. Accordingly, the resultant spacer 31 is thermally oxidized at a predetermined temperature to remove the etching damage. At this time, a thin thermal oxide film is grown on the surface of the semiconductor substrate 21 between the gate patterns 29. An ion implantation process is performed to form a source / drain region (not shown) in the semiconductor substrate 21 between the gate patterns 29 by using the thin thermal oxide film as a screen oxide film. Subsequently, the surface of the resultant is cleaned by a conventional method. In this case, the thin thermal oxide film may be cooled to expose the semiconductor substrate 21 under the thin thermal oxide film, or a part of the thin thermal oxide film may remain. Next, the surface-finished product is exposed to a plasma using nitrogen gas and ammonia gas to form a nitride film 33 on the surface of the remaining thermal oxide film or on the exposed semiconductor substrate 21. At this time, the plasma treatment process is preferably carried out for 20 seconds to 2 minutes at a temperature of 200 ℃ to 500 ℃. When a thermal oxide film remains between the gate patterns 29, the nitride film 33 formed on the remaining thermal oxide film is an oxynitride film. When the semiconductor substrate 21 is exposed between the gate patterns 29, the nitride film 29 formed on the exposed semiconductor substrate 21 is a silicon nitride film.

The nitride film 33 may be formed by a heat treatment process instead of a plasma treatment process. At this time, the heat treatment step is carried out in a temperature of 700 ℃ to 1000 ℃ and ammonia gas atmosphere.

FIG. 5 is a cross-sectional view for describing a step of forming the etch stop layer 35 and the interlayer insulating layer 41. In detail, the etch stop layer 35 is formed on the entire surface of the resultant product on which the nitride layer 33 is formed. The etch stop layer 35 is preferably formed of an insulating film having a high etching selectivity relative to the oxide film, for example, a thin silicon nitride film having a thickness of 70 to 150 Å. In this case, the etch stop layer 35, that is, the silicon nitride layer is formed on the capping insulating layer pattern 27, the spacer 31, and the nitride layer 33 to have a uniform thickness. Therefore, in order to form an etch stop layer 35 having a predetermined thickness, that is, a silicon nitride film having a thickness of 70 to 150 에 on the semiconductor substrate 21 between the gate patterns 29, on the gate pattern 29 and the spacer 31. It is not necessary to form a thick silicon nitride film more than necessary. As the silicon nitride film formed on the gate pattern 29 and the spacer 31 is thicker, the area of the semiconductor substrate 21 exposed by the self-aligned contact hole formed in a subsequent process decreases. This is because the etch stop layer 35 formed on the spacer 31 is completely removed while the etch stop layer 35 and the nitride layer 33 formed on the semiconductor substrate 21 between the gate patterns 29 are completely etched. Because it is not. Therefore, in order to completely remove the etch stop layer 35 formed on the spacer 31, the etch stop layer 35 needs to be excessively etched. At this time, the semiconductor substrate 21 already exposed between the gate patterns 29 is further overetched. When the semiconductor substrate 21 is further etched in this way, the depth of the source / drain regions becomes very shallow, and severe etch damage is applied to the semiconductor substrate 21. As a result, the leakage current characteristics of the source / drain regions are reduced, and the driving current of the transistor is reduced. In addition, when the etch stop layer 35 is excessively etched, an edge portion of the capping insulation layer pattern 27 formed of the same material layer as that of the etch stop layer 35, that is, silicon nitride layer is excessively etched, thereby forming a conductive layer pattern 25. ), That is, the gate electrode may be exposed. In conclusion, the etch stop layer 35 formed on the spacer 31 and the gate pattern 29 should be formed as thin as possible in order to increase the margin of the etching process for forming the self-aligned contact hole. The etch stop layer 35 formed on the semiconductor substrate 21 between the patterns 29 should be formed thicker than a predetermined thickness in order to suppress the floating phenomenon in the subsequent process. The nitride film 33 according to the present invention improves the thickness uniformity of the etch stop film 35 and thus satisfies the above requirements. Therefore, excessive etching is not required in a subsequent process of etching the etch stop layer to form a self-aligned contact hole.

Subsequently, an interlayer insulating layer 41 is formed on the entire surface of the resultant product in which the etch stop layer 35 is formed. The interlayer insulating film 41 is preferably formed of a high density plasma CVD oxide film 37 having excellent characteristics for filling a gap. However, as shown in FIG. 5, the interlayer insulating film 41 may be formed by sequentially stacking a high density plasma CVD oxide film 37 and a low pressure CVD oxide film 39. At this time, since the etch stop layer 35 formed on the nitride layer 33 maintains a constant thickness, the etch stop layer 35 is suppressed when the high density plasma CVD oxide layer 37 is formed. Here, the process of forming the high-density plasma CVD oxide film 37 has a superior characteristic than the low pressure CVD oxide film 39 because the deposition process and the etching process are alternately performed to completely fill the recesses without voids. However, the high-density plasma CVD oxide film 37 has a very slow deposition rate compared to the low pressure CVD oxide film 39, thereby reducing the throughput. Therefore, in order to form the void-free interlayer insulating film 41 on the surface having a severe topology, a high density plasma CVD oxide film 37 is initially formed to a predetermined thickness, and on the high density plasma CVD oxide film 37. It is preferable to form the low pressure CVD oxide film 39 in the. The high density plasma CVD oxide film 41 may be an undoped silicate glass (USG), a borophosphosilicate glass (BPSG) film, a phosphosilicate glass (PSG) film, or a borosilicate glass (BSG) film. In the case of forming the undoped oxide film by high density plasma CVD, argon gas, silane (SiH ₄ ) gas, and oxygen gas are used as the reaction gas. When an oxide film doped with impurities, that is, a BPSG film, a PSG film, or a BSG film is formed by a high density plasma CVD method, an appropriate impurity gas is additionally injected in addition to the reaction gas. Examples of the high density plasma CVD process include electron cyclotron resonance (ECR), helicon CVD, and inductive coupled type CVD.

6 is a cross-sectional view for explaining a step of forming a planarized interlayer insulating film 41a and a photoresist pattern 43 for defining a self-aligned contact hole. In detail, the planarized interlayer insulating film 41a is formed by planarizing the interlayer insulating film 41 using a chemical mechanical polishing (CMP) process. In this case, the chemical mechanical polishing process is performed until the planarized interlayer insulating film 41a remaining on the gate pattern 29 has a predetermined thickness. In this case, a blanket etch-back process may be used instead of the chemical mechanical polishing process as a method of planarizing the interlayer insulating layer 41. Next, a photoresist pattern 43 for defining a self-aligned contact hole region is formed on the planarized interlayer insulating film 41a. The photoresist pattern 43 exposes a predetermined region of the planarized interlayer insulating film 41a between the gate patterns 29 adjacent to each other. In this case, in order to increase the alignment margin during the photolithography process for forming the photoresist pattern 43, the width W2 of the area opened by the photoresist pattern 43 may be changed into the gate patterns ( 29) wider than the gap W1 therebetween.

7 is a cross-sectional view for explaining a step of forming a self-aligning contact hole H. FIG. In more detail, the exposed planarization interlayer insulating layer 41a is etched using the photoresist pattern 43 as an etch mask, thereby exposing the etch stop layer 35 between the gate patterns 29. In this case, the etch stop layer 35 formed on the edge region of the gate pattern 29 may also be exposed. Next, the exposed etch stop layer 35 is etched to expose the spacers 31 between the gate patterns 29 adjacent to each other. The nitride substrate 33 interposed between the exposed etch stop layer 35 and the semiconductor substrate 21 is etched and removed to expose the semiconductor substrate 21 between the gate patterns 29. The self-aligning contact hole H is formed. In this case, even if the exposed etch stop layer 35 is not excessively etched as described in FIG. 5, the area of the semiconductor substrate 21 exposed by the self-aligned contact hole H may be maximized. . Subsequently, the photoresist pattern 43 is removed by a conventional method.

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

According to the present invention as described above, by forming a nitride film on the semiconductor substrate between the gate pattern, it is possible to form an etch stop film having a uniform thickness on the entire surface of the resultant nitride film. Accordingly, when the interlayer insulating film is formed of the high density plasma CVD oxide film, the etch stop film formed on the surface of the active region between the gate patterns may be suppressed.

Claims (15)

Forming a gate oxide film on the semiconductor substrate; Forming a plurality of gate patterns parallel to each other on a predetermined region of the gate oxide film; Forming a spacer on sidewalls of the gate pattern; Forming a nitride film on an oxide film surface or an exposed semiconductor substrate surface remaining between the gate patterns; And And forming an etch stop layer on the entire surface of the resultant product in which the nitride layer is formed. The method of claim 1, wherein after forming the etch stop layer Forming a planarized interlayer insulating layer on the etch stop layer; Etching a predetermined region of the planarized interlayer insulating layer to expose an etch stop layer between the gate patterns; And And removing the exposed etch stop layer and the nitride layer under the exposed etch stop layer, thereby exposing a semiconductor substrate between the gate patterns. The method of claim 1, wherein the forming of the plurality of gate patterns is performed. Sequentially forming a conductive film and a capping insulating film on the gate oxide film; And And sequentially patterning the capping insulating layer and the conductive layer to form a plurality of gate patterns each consisting of a conductive layer pattern and a capping insulating layer pattern sequentially stacked on a predetermined region of the gate oxide layer and parallel to each other. Self-aligning contact hole forming method. 4. The method of claim 3, wherein the conductive layer is formed of a doped polysilicon layer or a polyside layer. The method of claim 3, wherein the capping insulating layer is formed of a silicon nitride layer. The method of claim 1, wherein the spacer is formed of a silicon nitride film. The method of claim 1, wherein the nitride film is formed by exposing the resultant product having the spacer to a plasma using nitrogen gas and ammonia gas. The method of claim 7, wherein the plasma treatment process is performed for 20 seconds to 2 minutes at a temperature of 200 ℃ to 500 ℃. The method of claim 1, wherein the nitride layer is formed by heat-treating the resultant product on which the spacer is formed at a temperature of 700 ° C. to 1000 ° C. and an ammonia gas atmosphere. The method of claim 1, wherein the etch stop layer is formed of a silicon nitride layer. The method of claim 10, wherein the silicon nitride layer has a thickness of about 70 kPa to about 150 kPa. 3. The method of claim 2, wherein the planarized interlayer insulating film is formed of a high density plasma CVD oxide film. The method of claim 12, wherein the high density plasma CVD oxide film is formed using argon gas, silane gas (SiH ₄ ), and oxygen gas. The method of claim 12, wherein the high-density plasma CVD oxide is any one selected from the group consisting of borophosphosilicate glass, PSG film (phosphosilicate glass), BSG film (borosilicate glass), and undoped silicate glass Self-aligning contact hole forming method, characterized in that. The method of claim 2, wherein the forming of the planarized interlayer insulating film is performed. Forming a high density plasma CVD oxide film on the entire surface of the resultant material on which the etch stop film is formed; Forming an interlayer insulating film composed of the high density plasma CVD oxide film and the low pressure CVD oxide film by forming a low pressure CVD oxide film on the high density plasma CVD oxide film; And Forming a planarized interlayer dielectric layer by etching the interlayer dielectric layer by a chemical mechanical polishing (CMP) process until an interlayer dielectric layer having a predetermined thickness remains on the gate pattern. Way.