KR100528765B1 - Method of manufacturing a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein the bit line is reduced by the damascene method using a metal, that is, copper, thereby reducing coupling noise between adjacent bit lines and forming a bit line in a cell region. The bottom electrode of the MIM capacitor in the time logic region is also formed, thereby providing a method of manufacturing a semiconductor device capable of improving the manufacturing efficiency of the SoC device without an additional process.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a process scheme for simultaneously forming a merged planner DRAM and a logic device, a bit line is formed of copper using a damascene method, and a MIM of a logic region is formed when the bit line is formed. (Metal Insulator Metal) The present invention relates to a method of simultaneously forming a capacitor lower electrode.

As semiconductor memory devices become more integrated, so-called System On Chip (SoC), which implements devices having different functions on one chip so that two or more devices operate organically on one chip. ) And so on. So the manufacturing process of SoC is more complicated and difficult. The manufacturing process for implementing devices having different functions on each chip may be applied to a process that satisfies the characteristics of only one device, but each device requires two or more devices having different functions on one chip. The process that satisfies all the properties becomes very complicated and in some cases additional processes are added. An embedded memory device, which is one of SoC devices, implements a memory device and a logic device on a single chip, and computes a cell area in which a plurality of memory cells are located and information stored in the cell area. It is composed of logic areas that generate information.

As one of such SoC devices, in a merged planar DRAM and logic (MPDL) using a MOS capacitor as a cell capacitor, there is a problem of reduced yield due to coupling noise between bit lines of a cell. In addition, in the device formation of the cell region and the logic region, there is a problem that the manufacturing efficiency of the SoC device deteriorates due to a different type of process for each region.

Therefore, in order to solve the above problems, the present invention reduces the coupling noise between adjacent bit lines by reducing the height of the bit lines by forming the bit lines using metal, that is, copper using the damascene method, and reducing the cell. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of increasing the manufacturing efficiency of a SoC device without additional processing by forming a bottom electrode of a MIM capacitor in a logic area when forming a bit line.

In the cell region according to the present invention, a semiconductor substrate having a plurality of elements (a memory cell) including a MOS capacitor and a MOS transistor is formed, and a semiconductor substrate having a plurality of elements including a logic transistor is provided in a logic region, Forming a first insulating film, patterning a portion of the first insulating film, forming a bit line contact and a bit line in the cell region, and forming a lower electrode of a capacitor in the logic region; Forming a second insulating film to be used as a dielectric film of the capacitor to be formed in the logic region, forming a third insulating film on the second insulating film, and then patterning the third insulating film of the logic region to form an upper electrode of the capacitor; Providing a method for manufacturing a semiconductor device comprising the step of forming a metal wiring .

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

Since the stacked DRAM uses polylines as bit lines, the thickness of the bit lines is three times lower than that of metal-based bit lines. However, in the MPDL to be used as an embodiment of the present invention, since the bit lines are formed of metal, they are vulnerable to coupling noise. This is because the planar DRAM has a smaller sensing capacitor margin because the cell capacitor capacity is smaller than that of the stack DRAM cell. Using a thick metal bitline, the sensing margin is further reduced by crosstalk with adjacent bitlines. In addition, the present invention uses a MOS capacitor as a capacitor of the memory cell. That is, the polysilicon in the upper layer becomes the power electrode, and the active region of the lower silicon becomes the storage node. An oxide film may be used as the dielectric material between the two electrodes.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a device isolation layer 12 is formed on a semiconductor substrate 10 in which a cell region A and a logic region B are defined.

Specifically, the pad oxide film (not shown) and the pad nitride film (not shown) are sequentially deposited. After the photoresist is coated over the entire structure, a photolithography process is performed to form a first photoresist pattern (not shown) for device isolation having a shallow trench isolation (STI) structure. An etching process using the first photoresist pattern as an etching mask is performed to etch the pad nitride layer, the pad oxide layer, and the semiconductor substrate 10 to form trenches (not shown) having an STI structure. The inside of the trench of the STI structure is oxidized and buried using an oxide-based material film, and then the STI planarization process is performed. The heat treatment process and the nitride film removal process are performed to remove the material film, the pad nitride film, and the pad oxide film remaining on the semiconductor substrate 10 to form the device isolation film 12 having the STI structure. The present invention is not limited thereto, and various processes and material films may be used to form the device isolation layer 12 having the STI structure.

Referring to FIG. 1B, the MOS capacitor used as the unit cell and the gate electrode of the MOS transistor are formed in the cell region A, and the gate electrode of the logic transistor is formed in the logic region.

Specifically, an ion implantation process is performed to form wells (not shown) for each region, and then an oxidation process is performed to form the gate oxide film 14. Of course, various types of processes such as a heat treatment process, a screen oxide film formation process, and a cleaning process may be applied to form the wells. The gate electrode conductive film 16 is formed on the gate oxide film 14. Polysilicon is deposited as the conductive film 16. A patterning process is performed to form a gate electrode for logic circuit in the logic region B, and a gate electrode for a MOS capacitor for the cell and a gate electrode for the MOS transistor in the cell region A. The patterning process may be performed by a photolithography process using a photosensitive film and an etching process of various forms.

Referring to FIG. 1C, a spacer 18 is formed on a gate sidewall, and then a source and a drain 20 are formed.

Specifically, after performing a gate light oxidation process for gate protection, a low concentration ion implantation is performed to form a lightly doped drain (LDD) cushion (not shown). The first insulating layer (not shown) is deposited on the entire structure, and then the entire surface is etched to remove the insulating layer except for the gate electrode sidewall, thereby forming a spacer 18 on the sidewall of the gate electrode. An oxide film or a nitride film can be formed as the first insulating film. High concentration ion implantation is performed to form the source and drain (junction) 20. The MOS capacitor 22 and the MOS transistor 24 are formed in the cell region A, and the logic transistor 26 is formed in the logic region B.

Referring to FIG. 1D, an insulating layer is formed over the gate electrodes of the cell region A and the logic region B, and a silicide film (not shown) is formed on the junction, and then the gate is insulated from the bit line contacts to be formed by a subsequent process. The second insulating film 28 is deposited and planarized. An etch stop layer 30 and a dielectric layer 32 are formed on the second insulating layer 28 to form the bit line contact and the MIM lower electrode region.

 Specifically, a metal film (not shown) is formed on the entire structure where the gate electrode is formed, and then a heat treatment process is performed to react the polysilicon and the metal film to form the silicide film. The metal film is formed by depositing Ti, Co, or Ni by monoatomic CVD or electroplating.

The MOS capacitor 22, the MOS transistor 24, or the logic transistor 26 perform a gate light oxidization process for gate protection after gate formation, and then perform low concentration ion implantation to form a lightly doped drain (LDD) cushion (not shown). And a spacer are formed on the sidewalls of the gate electrode, followed by high ion implantation to form a source and a drain.

An oxide film or a nitride film-based second insulating film 28 is deposited on the entire structure including the cell region A in which the MOS capacitor 22 and the MOS transistor 24 are formed, and the logic region B in which the logic transistor 26 is formed. , Flatten. An etch stop layer 30 having a high etch selectivity with respect to the second insulating layer 28 is formed on the second insulating layer 28, and then a dielectric layer 32 is formed on the etch stop layer 30. The etch stop layer 30 may be formed to have a nitride film having a thickness of 300 to 1000 Å, and the dielectric film 32 may have a thickness of 1000 to 3,000 Å.

Referring to FIG. 1E, a bit line 34 is formed in the cell region A and a lower electrode 36 of the MIM capacitor is formed in the logic region B through a patterning process.

In this embodiment, a damascene process is introduced to pattern the dielectric layer 32 and the etch stop layer 30 of the cell region A to first form a bit line contact hole (not shown), and then etch the dielectric layer 32 with the dielectric layer 32. The stop layer 30 is patterned to form trenches for the bit line of the cell region A and the lower electrode of the logic region, and the bit line contact hole and the trench are filled with metal to fill the bit line 34 and the lower electrode. Form 36.

Specifically, a second photoresist pattern (not shown) is formed by applying a photoresist on the entire structure and then performing a photolithography process using a mask for a bit line contact hole. An etching process using the second photoresist layer pattern as an etch mask may be performed to etch the entire second insulating layer or to form a bit line contact hole exposing the junction part. The second photoresist pattern is removed.

A photolithography process using a photosensitive film, a bit line mask, and a mask for the lower electrode of the MIM capacitor is performed to form a third photoresist pattern (not shown) for forming a bit line in the cell region A, and to form a logic region B. ) Forms a fourth photoresist pattern (not shown) for forming the lower electrode of the MIM capacitor. Cell regions in which bit line contact holes are formed by removing the etch stop layer 30 and the dielectric layer 32 on the second insulating layer 28 by performing various etching processes using the third and fourth photoresist layer patterns as etch masks, respectively. In (A), a bit line trench (not shown) and a logic region (B) form a bit line contact hole region previously patterned in forming a trench for a lower electrode of a capacitor (not shown). The second insulating film in the contact hole region is exposed to the junction to form a bit line contact hole by using an etching selectivity for the dielectric film and the etch stop layer in the region where the lower electrode is formed. In this case, the bit line trench may be formed first in the cell region A, and then the capacitor lower electrode trench of the logic region B may be formed, or the capacitor lower electrode trench of the logic region B may be formed, and then the cell region A may be formed. The bit line trench may be formed as shown in FIG. 2, and the bit line trench and the lower electrode trench of the capacitor may be simultaneously formed in the cell region A and the logic region B as in the present embodiment. A portion of the etch stop layer 30 and the dielectric layer 32 are removed to form the bit line trench and the lower electrode trench of the capacitor, and then the third and fourth photoresist patterns are removed. The material film in which the bit line contact hole of the cell region A is buried is removed.

The bit line plug 38 and the bit line 34 are formed in the cell region A through various methods and processes, and the lower electrode 36 of the MIM capacitor is formed in the logic region B. Can be formed. For example, a bit line trench may be first formed in the cell region A, and then a bit line contact hole may be formed through a patterning process.

A first barrier film (not shown) is formed on the entire structure to prevent diffusion of the metal along the step. A first metal layer (not shown) is formed on the entire structure where the first barrier layer is formed, and then planarized to form a bit line plug 38 and a bit line 34 in the cell region A, and a logic region B. The lower electrode 36 of the MIM capacitor is formed. The first barrier film is formed using one of Ti, Tin, and WN. By using copper as the first metal film, the height of the bit line, in which Al is used as the first metal film, may be lowered. The characteristics of copper are superior to that of aluminum and the bit line height can be controlled because the damascene method forms the bit line and the lower electrode. In addition, Al, which is used as the first metal film, has a limitation in lowering the bit line height because of the problem of lowering conductivity by forming a third material by reacting with the barrier metal when the height is low when forming the bit line. That is, when Al is 3000 Pa or less, many problems will arise.

To this end, a bit line 34 and a lower electrode 36 having a thickness of about 1000 to 2500 microseconds, which is about half the deposition thickness of aluminum, which is a first metal film that has been conventionally used, is planarized using chemical mechanical polishing (CMP). To form. This lowers the thickness of the bit line 34 described above to reduce noise of the coupling cap between adjacent bit lines. By simultaneously forming the bit line 34 of the cell region A and the lower electrode 36 of the capacitor of the logic region B without additional processing, the production period and production cost in the manufacture of the SOC can be reduced.

Referring to FIG. 1F, a third insulating layer 40 is formed on the cell region A and the logic region B on which the bit line 34 and the lower electrode 36 of the MIM capacitor are formed. The patterning process is performed to form the metal plug 42 for electrical contact with the lower metal wiring to be formed in the logic region B.

Specifically, the third insulating film 40 is formed using a dielectric material and used as the dielectric film of the MIM capacitor. The thickness of the third insulating film 40 may be adjusted by depositing the third insulating film 40 and then performing a planarization process. The dielectric material uses dielectric materials used in the manufacture of conventional MIM capacitors.

After the photosensitive film is coated on the third insulating film 40, a photolithography process using a mask for metal plugs is performed to form a fifth photoresist film pattern (not shown). An etching process using the fifth photoresist pattern as an etching mask is performed to form a metal plug hole (not shown) exposing a junction of the logic transistor 26 in the logic region B. The fifth photosensitive film pattern is removed.

A second barrier film (not shown) and a second metal film (not shown) are deposited on the entire structure on which the metal plug hole is formed, and then a planarization process is performed to form the metal plug 42. . The second barrier film is formed using one of Ti, Tin, and WN. It forms using copper as said 2nd metal film. The metal plug 42 is formed by removing the second barrier film and the second metal film formed on the third insulating film 40 through a planarization process using CMP.

Referring to FIG. 1G, a fourth insulating film 44 for forming the upper electrode 48 of the MIM capacitor is formed on the entire structure. The fourth insulating layer 44 is patterned to form the upper electrode 48 and the lower metal wiring 50 of the MIM capacitor. After forming the fifth insulating layer 46, the fifth insulating layer 46 is patterned to form the via plug 52.

Specifically, a fourth insulating film 44 for forming the upper electrode 48 of the capacitor is formed on the third insulating film 40 on which the metal plug 42 of the logic region B is formed using a dielectric material. After the photoresist is coated on the fourth insulating layer 44, a photolithography process is performed using a mask for the upper electrode of the MIM capacitor to form a sixth photoresist pattern (not shown). By removing the fourth insulating layer 44 through an etching process using the sixth photoresist pattern as an etching mask, a region (upper electrode trench) in which the upper electrode of the MIM capacitor is to be formed is defined. A third barrier film (not shown) is deposited on the entire structure, a third metal film (not shown) is deposited, and then planarized to form an upper electrode 48 of the MIM capacitor. The third barrier film is formed using at least one of Ti, Tin, and WN. An upper electrode is formed using copper as said 3rd metal film. The upper electrode 48 is formed by removing the third barrier layer and the third metal layer formed on the fourth insulating layer 44 through a planarization process using CMP.

The upper electrode 48 or the lower metal interconnection 50 of the MIM capacitor in the logic region B is designed so that the upper electrode 48 or the lower metal interconnection 50 and the cell do not pass over the block of the cell region A. Coupling noise between the bit lines 34 in the area A is prevented from occurring.

The fifth insulating layer 46 is formed on the entire structure where the upper electrode 48 or the lower metal wiring 50 is formed. After the photosensitive film is coated on the fifth insulating film 46, a photolithography process using a mask for a via plug is performed to form a seventh photoresist film pattern (not shown). Through the etching process using the seventh photoresist pattern as an etching mask, the fifth insulating layer 46 is removed to form a via plug hole (not shown) that is exposed to the lower metal wiring 50 or the third insulating layer. After removing the seventh photoresist layer pattern, a fourth barrier layer (not shown) and a fourth metal layer (not shown) are deposited on the entire structure and planarized to provide electrical connection between the lower metal interconnection 50 and the upper metal interconnection. Via plug 52 is formed.

Referring to FIG. 1H, the sixth insulating layer 54 is formed on the fifth insulating layer 46 on which the via plug 52 is formed, and then the sixth insulating layer 54 is patterned to form the upper metal wiring 56. .

Specifically, the sixth insulating film 54 is formed on the fifth insulating film 46, and then a photosensitive film is coated. An eighth photoresist pattern (not shown) is formed by performing a photolithography process using an upper metallization mask. An etching process using the eighth photoresist pattern as an etching mask is performed to remove the sixth insulating layer 54, and then the eighth photoresist pattern is removed. The barrier film and the metal film are deposited on the entire structure along the step, and then the planarization process is performed to form the upper metal wiring 56 connected to the via plug 52.

Not limited to this, the connection between the upper metal and the lower metal may be formed by performing a dual damascene process.

The formation of the aforementioned metal film specifies that various types of processes for the manufacture of semiconductor devices can be applied. For example, it can be formed using a deposition method such as CVD and a metal plating method.

In addition, the upper electrode, the lower metal wiring, and the upper metal wiring in this embodiment may be implemented by various types of process methods and conditions, but the metal bit line of the cell region and the MIM capacitor lower electrode of the logic region are the same metal film. It is formed simultaneously through the deposition process and the planarization process.

In addition, after forming various types of elements constituting the semiconductor device not described above, a passivation process is performed to form a memory cell composed of a MOS capacitor and a MOS transistor in a cell region, and a logic composed of a logic transistor in a logic region. Form a circuit.

As described above, according to the present invention, by forming the bit line of the MPDL element using metal, that is, copper, the height of the bit line can be reduced to reduce coupling noise between adjacent bit lines.

In addition, by forming the bottom electrode of the MIM capacitor in the logic region when forming the bit line of the cell region, the manufacturing efficiency of the SoC device may be improved without additional processes.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 12 device isolation film

14 gate insulating film 16 conductive film

18: spacer 20: source and drain

22: MOS capacitor 24: MOS transistor

26: logic transistor 30: etching stop film

28, 40, 44, 46, 54: insulating film

32: dielectric film 34: bit line

36: lower electrode 38: bit line plug

42 metal plug 48 upper electrode

50: lower metal wiring 52: contact plug

56: upper metal wiring

Claims (3)

(a) providing a semiconductor substrate having a plurality of elements (a memory cell) including a MOS capacitor and a MOS transistor in a cell region, and a plurality of elements including a logic transistor formed in a logic region; (b) forming a first insulating film on the entire structure; (c) patterning the first insulating film in the cell region to form a bit line contact hole and a bit line trench; (d) patterning the first insulating film in the logic region to form a lower electrode trench; (e) a metal film is deposited only in the bit line contact hole, the bit line trench and the lower electrode trench on the entire structure to form the bit line contact and the bit line in the cell region, and in the logic region Forming a lower electrode; (f) forming a second insulating film on the entire structure to be used as a dielectric film of a capacitor to be formed in the logic region; And (g) forming a third insulating film on the second insulating film, and then patterning the third insulating film of the logic region to form a metal wiring and an upper electrode of the capacitor. Manufacturing method. The method of claim 1, wherein step (e) Depositing a metal film on the entire structure where the bit line contact hole, the bit line trench and the lower electrode trench are formed; And And performing a planarization process on the metal film remaining on the first insulating film and a part of the first insulating film. The method of claim 2, The metal film is a copper film, the method of manufacturing a semiconductor device characterized in that 40 to 60% of the layer thickness of the metal film remaining through the planarization process.