KR101699443B1 - Method for manufacturing semiconductor device having vertical channel transistor - Google Patents

Abstract

A method of manufacturing a semiconductor device having a vertical channel transistor is provided. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a plurality of line-shaped first isolation films extending from a top surface of a substrate at a first depth in a first direction on the substrate, Defining a plurality of active areas in a line shape extending to the active area; Forming a plurality of trenches extending in a second direction perpendicular to the first direction and having a second depth less than the first depth and having a first width; Forming a plurality of device isolation trenches having a third depth greater than the second depth by etching the substrate on the bottom surface of the plurality of trenches selected at regular intervals among the plurality of trenches; Forming a second device isolation layer including an insulating material below the plurality of device isolation trenches; And forming a buried bit line on the bottom surface of the plurality of trenches and the plurality of device isolation trenches.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a vertical channel transistor,

The technical idea of the present invention relates to a method of manufacturing a semiconductor memory device and more particularly to a method of manufacturing a semiconductor memory device having a vertical channel transistor having a structure in which a vertical channel is formed in an active region facing a side wall of a contact gate And a method of manufacturing a semiconductor device.

As the degree of integration of semiconductor devices increases, the design rules for components of semiconductor devices are decreasing. Particularly, in a semiconductor device requiring a large number of transistors, the gate length, which is a standard of a design rule, is reduced, and the channel length is also reduced. A vertical channel transistor has been proposed in order to increase the effective channel length by lengthening the distance between the source and the drain in a transistor of a highly scaled semiconductor device.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device in which a channel width of a contact gate is uniformly formed in manufacturing a semiconductor device having a vertical channel transistor structure having a miniaturized unit cell size will be.

It is another object of the present invention to provide a method of manufacturing a semiconductor device in which bit lines are effectively insulated from adjacent active regions.

A method of manufacturing a semiconductor device having a vertical channel transistor according to an embodiment of the present invention is provided. A plurality of line-shaped first isolation films extending in a first direction from a top surface of the substrate at a first depth are formed on the substrate, and a plurality of line-shaped Defining an active region of the substrate;

Forming a plurality of trenches extending in a second direction perpendicular to the first direction and having a second depth less than the first depth and having a first width; Forming a plurality of device isolation trenches having a third depth greater than the second depth by etching the substrate on the bottom surface of the plurality of trenches selected at regular intervals among the plurality of trenches; Forming a second device isolation layer including an insulating material below the plurality of device isolation trenches; And forming a buried bit line on the bottom surface of the plurality of trenches and the plurality of device isolation trenches.

In some embodiments of the present invention, in the step of forming the second device isolation film, the second device isolation film may be formed by oxidizing the substrate exposed on the bottom and side surfaces of the plurality of device isolation trenches.

In some embodiments of the present invention, after forming the plurality of trenches, forming an insulating film liner in the plurality of trenches may be further included.

In some embodiments of the present invention, the step of forming the plurality of device isolation trenches includes a step of forming a plurality of trenches in the device isolation trenches, Forming a pattern; Removing the insulating film liner on the bottom surface of the plurality of trenches exposed by the opening; And etching the substrate on the bottom surface of the plurality of trenches exposed by the removed insulating film liner.

In some embodiments of the present invention, in the step of forming the second isolation film, the second isolation film may be formed by using the insulation film liner formed on the sidewall of the plurality of isolation trenches as an oxidation- The LOCOS method for selectively oxidizing the bottoms of the element isolation trenches can be adopted.

In some embodiments of the present invention, in the step of forming the plurality of element isolation trenches, the plurality of element isolation trenches are formed such that the plurality of trenches, which are alternately selected along the first direction, And may be formed in an area alternately selected along the second direction among the areas intersecting the active area.

In some embodiments of the present invention, the second isolation film may have a second width larger than the first width.

In some embodiments of the present invention, after forming the second isolation film, the substrate and the first isolation film on the bottom surface of the plurality of trenches and the second isolation film on the bottom surface of the plurality of isolation trenches And partially etching the device isolation film.

In some embodiments of the present invention, in the partially etched step, the etched plurality of trenches and the plurality of device isolation trenches may have a depth less than the first depth.

In some embodiments of the present invention, after the partially etching step, an ion implantation step of a low concentration dopant to form a first source region and a drain region may be further included.

In some embodiments of the present invention, the etching step is performed in a first step of etching to a predetermined depth and a second step of further etching to a desired depth, and the first step and the second step And an ion implanting step for forming a first source region and a drain region between the first electrode and the second electrode.

In some embodiments of the present invention, after forming the plurality of trenches, forming an oxide film on the inner wall of the plurality of trenches may be further included.

In some embodiments of the present invention, after the step of forming the second isolation film, an ion implantation step for forming the first source region and the drain region may be further included.

In some embodiments of the present invention, in the ion implantation step, impurities may be implanted into the active region in contact with the buried bit line at the bottom and sides of the buried bit line formed in the plurality of trenches.

In some embodiments of the present invention, the bottom surface of the buried bit line may be located at a depth less than the second depth.

In some embodiments of the present invention, the buried bit line may be formed lower than the top surface of the substrate.

In some embodiments of the present invention, the active region may include two active pillars between the plurality of device isolation trenches, which are bisected about the plurality of trenches.

In some embodiments of the present invention, the method includes forming a buried insulating film filling the plurality of trenches and the plurality of element isolation trenches on the buried bit line; Forming a second source region and a drain region in an upper region of the active regions; Forming a gate insulating film on one vertical side of each of the active pillars; And a contact gate having a bottom surface lower than the top surface of the substrate and facing the vertical side surface with the gate insulating film therebetween; and forming a word line connected to the contact gate and located on the top surface of the substrate .

A method of manufacturing a semiconductor device having a vertical channel transistor according to another aspect of the present invention is provided. The method includes the steps of defining a plurality of line-shaped active regions on a substrate; Forming a plurality of trenches perpendicular to the plurality of active regions; Forming a plurality of device isolation trenches by etching the substrate on the bottom surface of the plurality of trenches, the plurality of trenches being selected at regular intervals among the plurality of trenches; Forming an insulating layer on the bottom surfaces of the plurality of element isolation trenches; And forming a buried bit line on the bottom surface of the plurality of trenches and the plurality of device isolation trenches.

A method of manufacturing a semiconductor device having a vertical channel transistor according to another aspect of the present invention is provided. The method of manufacturing a semiconductor device includes: defining a plurality of first active areas in a line shape on a substrate; Forming a plurality of trenches perpendicular to the plurality of first active regions on the substrate; Extending a depth of a portion of the plurality of trenches to form a plurality of device isolation trenches; And forming an insulating layer in the plurality of element isolation trenches to form a plurality of island-shaped second active regions.

A method of manufacturing a semiconductor device according to the technical idea of the present invention includes a plurality of buried bit lines formed in a substrate in a memory cell array having a unit memory cell size of 4F ² in which a vertical channel is formed in an active region. The channel of the contact gate can be formed to have a constant width by forming an additional device isolation film after forming the active region in the form of a line in the semiconductor device of the vertical channel transistor structure having the unit cell size refined by high integration.

Further, by forming the buried bit lines by self-aligning with the device isolation films, the insulating distance from the adjacent active regions in the extending direction of the buried bit lines can be ensured. Therefore, even if the unit memory cell area is very small, the possibility of short circuit and leakage current can be minimized and the reliability of the device can be maintained.

1 is a schematic layout of a semiconductor device according to embodiments of the present invention.
2A is a partial perspective view showing a three-dimensional arrangement relationship of components constituting a cell array region in a semiconductor device according to an embodiment of the present invention.
2B is a partial perspective view schematically showing the arrangement of bit lines in a semiconductor device according to an embodiment of the present invention.
FIGS. 3A to 13B are views illustrating a method of manufacturing the semiconductor device of FIG.
FIG. 14 is a partial perspective view showing a three-dimensional arrangement relationship of components constituting a cell array region in a semiconductor device according to another embodiment of the present invention. FIG.
FIGS. 15A and 15B are views for explaining the method of manufacturing the semiconductor device of FIG.
16 is a plan view of a memory module 1000 including a semiconductor device according to the technical idea of the present invention.
17 is a schematic view of a memory card 2000 including a semiconductor device according to the technical idea of the present invention.
18 is a schematic diagram of a system 3000 including a semiconductor device according to the technical idea of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, The present invention is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the invention is not limited by the relative size or spacing depicted in the accompanying drawings.

1 is a schematic layout of a semiconductor device according to embodiments of the present invention.

2A is a partial perspective view showing a three-dimensional arrangement relationship of components constituting a cell array region in a semiconductor device according to an embodiment of the present invention.

The layout illustrated in FIG. 1 is applicable, for example, to a DRAM memory cell having a unit cell size of DRAM (Dynamic Random Access Memory), particularly 4F ² . Here, 1F means minimum feature size.

1 and 2A, a semiconductor device 100 according to the present invention includes a substrate 102 having a plurality of island-shaped active portions 106 defined by a first device isolation film 106 and a second device isolation film 136, Area 10, as shown in FIG. The plurality of active regions 10 can be divided into two active pillars 10A and 10B on the upper surface side of the substrate 102 by the trenches 10T each recessed to a predetermined depth from the central portion of the upper surface thereof . A first source / drain region 42 is formed at a portion where the two active pillars 10A and 10B branch off from the plurality of active regions 10. The two active pillars 10A and 10B have top surfaces 12A and 12B, respectively, which are spaced apart from each other. The upper surfaces 12A and 12B of the active pillars 10A and 10B may correspond to the upper surface of the substrate 102, respectively. A second source / drain region 44 may be formed on the top surfaces 12A and 12B of the two active pillars 10A and 10B, respectively.

The plurality of active regions 10 have a length of 3F in a first direction (x direction in FIG. 1 and FIG. 2A) which is a long axis direction X and a second direction In the y direction).

In the substrate 102, a plurality of buried bit lines 20 extend parallel to each other in the short axis (Y) direction of the active region 10. The plurality of buried bit lines 20 may be located at the bottom of the trenches 10T that bisect the active pillars 10A, 10B in one active region 10. The plurality of buried bit lines 20 extend in the direction of the short axis Y of the plurality of active regions 10 in the substrate 102 while the active region 10, the first isolation film 106, Lt; RTI ID = 0.0 > 136 < / RTI >

The active pillars 10A and 10B in the active region 10 include a vertical side 10CH for providing a channel surface on which a vertical channel is formed. The vertical side 10CH may face the contact gate 30CG. The vertical sides 10CH, which provide the respective channel surfaces in the two active pillars 10A and 10B included in one active region 10, may face opposite directions. A first source / drain region 42 formed around the buried bit line 10 on the channel surface 10CH and a second source / drain region 42 formed on the top surfaces 12A and 12B of the active pillars 10A and 10B, And the source / drain regions 44, respectively.

The two active pillars 10A and 10B included in one active region 10 may constitute independent unit memory cells. Two unit memory cells, each of which is implemented in two active pillars 10A and 10B included in one active region 10, are connected to one first source / drain region 10 formed around the bottom of the buried bit line 10, (42).

The bottom surface of the contact gate 30CG in the substrate 102 may be formed at a higher position than the top surface of the buried bit line 10. [ The distance from the top surfaces 12A and 12B of the active pillars 10A and 10B on the top surface of the substrate 102 to the bottom surface of the contact gate 30CG is larger than the distance from the top surfaces 12A and 12B of the active pillars 10A and 10B May be less than the distance to the top surface of the buried bit line 20.

A plurality of word lines 30WL extend parallel to each other in a direction orthogonal to the extending direction of the plurality of buried bit lines 20 (x direction in FIGS. 1 and 2A). The plurality of word lines 30WL may be electrically connected to a plurality of contact gates 30CG arranged in a line along the extension direction thereof. The plurality of word lines 30WL may be formed integrally with a plurality of contact gates 30CG arranged in a line along the extending direction. Alternatively, the plurality of word lines (30WL) and the plurality of contact gates (30CG) arranged in a line along the extending direction thereof are formed of different layers by separate deposition processes, and they can directly contact each other have.

As shown in Fig. 1, one contact gate (not shown) is formed between two active regions 10 neighboring each other along the direction between the x direction and the y direction, for example, the oblique (DL) direction in Fig. 30CG) may be located. In addition, a unit memory cell constituted by one active pillar 10A included in one active region 10 of two active regions 10 neighboring in the y-direction and one active memory cell 10A included in another active region 10 A unit memory cell composed of one active pillar 10B can share one contact gate 30CG.

A buried contact plug 50 may be formed in the second source / drain region 44 formed on the upper surface of each of the plurality of active pillars 10A and 10B. The buried contact plug 50 may be implemented as being in direct contact with the second source / drain region 40 above the second source / drain region 40, as illustrated in FIG. 2A. The lower electrodes (not shown) of the capacitors may be formed on the plurality of the buried contact plugs 50, respectively.

In forming the memory cell array having the unit memory cell size of 4F ² illustrated in FIGS. 1 and 2A, by including the plurality of buried bit lines 20 formed in the substrate 102, Even if a bias of high voltage is applied to the buried bit line 20 in a semiconductor device of a vertical channel transistor structure having a cell size, there is no adverse effect due to bias in the vertical channel region. In addition, the insulation distance ID1 can be ensured between two adjacent buried contact plugs 50 viewed from the extension direction of the word line 30WL (x direction in Figs. 1 and 2A). Further, as viewed in the extending direction of the buried bit line 20 (the y direction in Figs. 1 and 2A), the insulation distance ID2 can be ensured between two neighboring word lines 30WL.

In the semiconductor device 100 according to the technical idea of the present invention illustrated in FIGS. 1 and 2A, a plurality of buried bit lines 20 formed in one cell array region are connected to peripheral circuit regions or core regions Perry bit line CP_20 formed in a "core / ferry area" hereinafter). At this time, the core / ferrite bit line CP_20 may be formed on the substrate 102. Therefore, in order to electrically connect the core / ferrite bit line CP_20 and the buried bit line 20, the edge portion of the cell array region is electrically connected to the core / ferrite bit line CP_20 and the buried bit line 20 A direct contact plug DC extending in a vertical direction (z direction in FIG.

2B is a partial perspective view schematically showing the arrangement of bit lines in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2B, a plurality of buried bit lines 20 formed in a cell region (cell array region) are connected to a core / ferrite bit line CP_20 formed in a core / ferry region at an edge portion of the cell region, DC).

A plurality of buried bit lines 20 are formed at positions lower than the upper surface of the substrate 102 in the substrate 102 and a plurality of core / . The direct contact plug DC may have a shape extending from the inside of the substrate 102 to the top of the substrate 102 in a direction perpendicular to the extending direction of the main surface of the substrate 102. [ The word line 30WL shown in FIGS. 1 and 2A is disposed between a first depth where a plurality of buried bit lines 20 are located and a second depth where a plurality of core / ferrite bit lines CP_20 are located .

FIGS. 3A to 13B are views illustrating a method of manufacturing the semiconductor device of FIG.

3A, 3B, and 3C, FIG. 3A is a plan view of a region corresponding to a rectangular portion indicated by "P" in the layout illustrated in FIG. 1, FIG. 3B is a cross-sectional view taken along a line BX1- BX2 - BX2 '. 3C is a cross-sectional view corresponding to the cut lines CY1-CY1 'and CY2-CY2' in Fig. 3A.

3A, a plurality of line-shaped first isolation films 106 extending parallel to each other in a first direction (x direction in FIG. 3A) are formed on the substrate 102, Shaped first active regions 108 extending in a plurality of lines. The first isolation layer 106 and the first active region 108 may have the same width in the second direction (y direction in FIG. 3A) and may have a length of 1F.

The substrate 102 may be a silicon substrate. In order to form the first isolation film 106, a mask pattern (not shown) may be formed on the substrate 102 and a trench 104 may be formed. An insulating material is deposited on the substrate 102 to completely fill the trench 104 and then the first isolation layer 106 is formed to planarize the deposited insulating material to fill the trench 104 . For example, a chemical mechanical polishing (CMP) process may be used to planarize the insulating material. Although not shown in the drawing, the first isolation layer 106 may have a structure in which a sidewall oxide layer, a nitride layer liner, and a gap fill oxide layer are sequentially formed.

3B, and the position of the bottom surface of the first element isolation film 106 is shown in Fig. 3C. The first isolation layer 106 may have a bottom surface of the first depth P 1 from the top surface of the substrate 102.

An ion implantation process for forming wells in the substrate 102 can be performed before forming the trenches 104 on the substrate 102 as required. The ion implantation process for forming the well may be performed after formation of the first isolation film 106. [

4A, 4B and 4C, FIG. 4A is a plan view of a region corresponding to a rectangular portion indicated by "P" in the layout illustrated in FIG. 1, FIG. 4B is a cross-sectional view taken along line BX1- BX2 - BX2 '. 4C is a cross-sectional view corresponding to the cut lines CY1-CY1 'and CY2-CY2' in Fig. 4A.

A plurality of line-shaped pad oxide film patterns 112 and a first mask pattern 114 extending parallel to each other in a second direction (y direction in FIG. 4A) perpendicular to the first direction are formed. The first mask pattern 114 may be a silicon nitride film. In addition, the first mask pattern 114 may have a multi-layer structure including, for example, a silicon nitride film or a carbon-containing film.

Next, the exposed first isolation film 106 and the first active region 108 are anisotropically etched to a predetermined depth by using the pad oxide film pattern 112 and the first mask pattern 114 as an etching mask. The etch provides a plurality of bit line trenches (not shown) that provide space for forming the buried bit lines 150 (see FIGS. 12A and 12B) in the first isolation layer 106 and the first active region 108, respectively 124 are formed. The first active region 108 and the device isolation film 106 of the substrate 102 are exposed at the bottom and both sides of the bit line trench 124

The plurality of bit line trenches 124 may be formed to have a second depth P2 smaller than the first depth P1 from the upper surface of the substrate 102. [

By forming the plurality of bit line trenches 124, the first active region 108 is divided into a plurality of active pillars. Each of the active pillars may have one unit memory cell, and each active pillars may provide a vertical channel region necessary for forming each unit memory cell.

The plurality of bit line trenches 124 may be formed at equal intervals along the extending direction of the first active region 108 in the substrate 102. The width W1 of the plurality of bit line trenches 124 in the extending direction of the first active region 108 may be formed to be equal to the width W2 of the plurality of active pillars 108A and 108B. Alternatively, the width W1 of the plurality of bit line trenches 124 may be formed to be larger than the width W2 of the plurality of active pillars 108A and 108B. The sum of the width W1 of the plurality of bit line trenches 124 and the width W2 of the plurality of active pillars 108A and 108B may have a length of 2F.

5A, 5B and 5C, FIG. 5A is a plan view of a region corresponding to a rectangular portion indicated by "P" in the layout illustrated in FIG. 1, FIG. 5B is a cross-sectional view taken along line BX1- BX2 - BX2 '. FIG. 5C is a cross-sectional view corresponding to the cut lines CY1-CY1 'and CY2-CY2' of FIG. 5A.

An insulating material is formed on the entire surface of the substrate 102 so that the insulating film liner 126 is formed on the inner walls of the plurality of bit line trenches 124. The insulating film liner 126 may include silicon nitride. The insulating film liner 126 may be formed to a thickness of several nanometers, for example, a thickness of 30 to 90 angstroms. As the insulating film liner 126 is formed, the plurality of bit line trenches 124 have a width W3 smaller than the original width W1.

The insulating film liner 126 may be deposited using a deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

Although not shown in the drawing, an oxide film (not shown) may be formed on the exposed surface of the substrate 102 using a radical oxidation process before forming the insulating film liner 126. By forming the oxide film (not shown), surface defects in the damaged first active region 108 can be healed during the etching process for forming a plurality of bit line trenches 124. In addition, the stress of the substrate 102 or the insulating film liner 126, which may be generated due to the formation of the insulating film liner 126, can be alleviated.

6A, 6B and 6C, FIG. 6A is a plan view of a region corresponding to a rectangular portion indicated by "P" in the layout illustrated in FIG. 1, FIG. 6B is a cross-sectional view taken along line BX1- BX2 - BX2 '. FIG. 6C is a cross-sectional view corresponding to the cut lines CY1-CY1 'and CY2-CY2' of FIG. 6A.

A second mask layer covering the first mask pattern 114 and the insulating film liner 126 is formed while filling the bit line trenches 124. The second mask layer is patterned to form a second mask pattern 130 including the opening 130H. The opening 130H is formed in an alternately selected bit line trench 124 of a series of bit line trenches 124 disposed along the extending direction of the first active region 108 (x direction in FIG. 6A) . The plurality of openings 130H are alternately formed in the extending direction (the y direction in FIG. 6A) of the bit line trenches 124 in the region intersecting with the first active region 108. As shown in FIG. The plurality of openings 130H may have a circular cross section.

The second mask pattern 130 may be formed of a carbon-containing film such as a SOH (Spin-On Hardmask) film.

7A, 7B and 7C, FIG. 7B is a cross-sectional view corresponding to the cut lines BX1 - BX1 'and BX2 - BX2' of FIG. 7A. FIG. 7C is a cross-sectional view corresponding to the cut lines CY1-CY1 'and CY2-CY2' of FIG. 7A. Also in the following figures, cross-sectional views corresponding to the above cutting lines of Fig. 7A are shown.

The second mask pattern 130 and the insulating film liner 126 and the first isolation film 106 exposed through the plurality of openings 130H are used as an etching mask to expose the plurality of openings 130H, The insulating film liner 126 and the substrate 102 are etched at the bottom surface of the bit line trench 124 to form an element isolation trench 134. [ That is, the device isolation trench 134 may be formed such that a part of the bit line trenches 124 of the plurality of bit line trenches 124 extends to a lower portion of the substrate 102. At this time, part of the nitride film liner 126 exposed at the entrance side of the bit line trench 124 may be partially consumed.

The etching process may include two steps of etching the substrate 102 after etch back the insulating film liner 126. Alternatively, the insulating film liner 126 and the substrate 102 may be sequentially etched in one process.

The device isolation trench 134 may be formed to have a third depth P3 from the top surface of the substrate 102. [ The third depth P3 is greater than the second depth P2 and may be the same as the first depth P1. Alternatively, it may be formed to be larger or smaller than the first depth P1. The device isolation trench 134 and the bit line trench 124 may have the same inner width W3 due to the insulating film liner 126 formed on the sidewall.

The bit line trench 124 and the device isolation trench 134 are formed along the direction in which the first active region 108 extends (x direction in FIG. 6A) as the device isolation trench 134 is formed Are arranged alternately. According to the subsequent process, the device isolation trench 134 performs both a device isolation role and a space for forming a bit line.

As the device isolation trench 134 is formed, the line-shaped first active region 108 is trimmed to form a plurality of second active regions 108A and 108B including two active pillars 108A and 108B. 108I). That is, the first active region 108 is divided into a plurality of second active regions 108I having an island shape.

By this process, the first active region 108 formed in a line shape is divided into the island-shaped second active region 108I by the element isolation trench 134. [ Therefore, as compared with the case where the active region is formed by island patterning by photolithography, there is no problem such as corner rounding of the active region, so that an active region having a constant width along the y direction of FIG. 6A can be formed have. The two active pillars 108A and 108B divided by the element isolation trenches 134 may have a constant length along the x direction of 6a. This, in turn, enables the fabrication of semiconductor devices having a constant channel width.

Referring to FIGS. 8A and 8B, after the second mask pattern 130 is removed, a second isolation layer 136 is formed under the isolation trench 134. Hereinafter, the shortened device isolation trench 134 'positioned on the second isolation film 136 after the second isolation film 136 is formed is indicated by a separate reference numeral.

The second isolation film 136 may be formed through an oxidation process of the substrate 102. For example, when the substrate 102 is a silicon substrate and the insulating film liner 126 is a silicon nitride film, a second isolation film 136 including a silicon oxide film is formed by oxidation of the substrate 102 . The oxidation process can be performed by the same principle as the LOCOS (Local Oxidation of Silicon) process. That is, the oxidation liner 126 may be used as an oxidation prevention layer to oxidize only the exposed portion of the substrate 102. Therefore, in order to form the second device isolation film 136 that can fill the width W3 of the device isolation trench 134, the substrate 102 May be consumed in the second active region < RTI ID = 0.0 > 108I < / RTI >

During the oxidation process for forming the second isolation film 136, the substrate 102 is consumed in the lower part of the device isolation trench 134, and the thickness of the oxide formed under the surface of the substrate 102 and the thickness 102 may be similar in thickness to the oxide produced on the surface. That is, the width W4 of the second isolation film 136 may be greater than the width W3 of the device isolation trench 134, and may be about twice. The second isolation film 136 may have a predetermined length L 1 and the bottom of the second isolation film 136 may be lower than the bottom of the isolation trench 134. That is, the bottom surface of the second isolation layer 136 may be formed to be deeper than the depth P1 of the first isolation layer 106.

The bottom surface of the second isolation film 136 may be formed to be higher or lower than the depth P1 of the first isolation film 106 depending on the formation depth of the isolation trench 134 have. The position of the upper surface of the second isolation film 136 formed in the element isolation trench 134 in the substrate 102 may be similar to the depth of the bit line trench 124. [

According to this step, the second device isolation film 136 can be formed in the element isolation trench 134 formed in a fine size by a simple process. In addition, the second isolation layer 136 can be formed immediately below the portion where the buried bit line 150 (see FIGS. 12A and 12B) is to be formed.

9A and 9B, in order to form the first source / drain region 140 around the bottom surface of the bit line trench 124 in the second active region 108I, Process. For this, a process of removing the insulation film liner 136 formed on the bottom surface of the bit line trench 124 may be performed.

The insulating film liner 136 may be etched back to leave the insulating film liner 136 only on the inner walls of the plurality of bit line trenches 124. The second active region 108I of the substrate 102 is exposed in the bottom surface of the plurality of bit line trenches 124 in the second active region 108I, The first isolation film 106 can be exposed from the bottom surface of the plurality of bit line trenches 124. [

Next, by performing an ion implantation process, a lightly doped region 142 is formed in the second active region 108I around the bottom surface of the bit line trench 124. Next, For example, the lightly doped region 142 may be formed by implantation of N-type impurity ions. However, the present invention is not limited thereto, and a P-type impurity may be implanted. The formation of the lightly doped region 142 by this step is optional, and the present step may be omitted depending on the characteristics of the desired device.

10A and 10B, a second active region 108I, a first device isolation film 106, and a second device isolation film (hereinafter referred to as " first active region 108I ") under the plurality of bit line trenches 124 and element isolation trenches 134 ' 136 are partially removed to extend the bit line trench 124 and the element isolation trench 134 '. After the removal process is performed, the second isolation film 136 remains at a predetermined length (L2) under the element isolation trench 134 '. The first mask pattern 114 on the active pillars 108A and 108B and the first isolation layer 106 may be consumed by the removal process so that the height of the first mask pattern 114 may be lowered have.

The removal process may be performed in a single process using an etchant having the same or similar etch selectivity to the second active region 108I, the first device isolation film 106, and the second device isolation film 136. [ Alternatively, for example, the second active region 108I may be etched first and then the first and second isolation films 106 and 136 may be etched in two or three steps It is possible.

If the first and second isolation films 106 and 136 are made of the same material, the bit line trenches 124 and the isolation trenches 134 'May be formed to have different depths. However, in this case, in the process of forming the buried bit line 150 to be described later with reference to FIGS. 11A and 11B, both of the bit line trenches 124 and the element isolation trenches 134 ' The thickness of the buried bit line 150 must be adjusted so that the buried bit line 150 can be formed.

Next, using the first mask pattern 114 as an ion implantation mask, the first source / drain regions are formed in the second active region 108I exposed at the bottom and both sides of the plurality of element isolation trenches 134 ' An ion implantation process for forming the drain region 140 is performed to form a region of the high concentration dopant 143. The heavily doped region 143 may be formed of the same type of impurity ions as the lightly doped region 142, for example, N-type impurity ions. As a result, a first source / drain region 140 is formed inside the substrate 102 around the bottom of the element isolation trench 134 'in the second active region 108I.

11A and 11B, a conductive material is deposited on the resultant structure in which the first source / drain region 140 is formed, and the conductive material is deposited on the inside of the plurality of bit line trenches 124 and the isolation trenches 134 ' Is formed. Next, an unnecessary portion of the conductive layer is removed by etch-back so that the conductive layer remains only on the bottom surfaces of the plurality of bit line trenches 124 and the element isolation trenches 134 ', thereby forming a plurality of bit line trenches 124 And a conductive layer remaining on the bottom surface of the element isolation trench 134 'are formed.

The buried bit line 150 extends across one of the two active pillars 108A, 108B in one second active region 108I. Two unit memory cells each implemented in two active pillars 108A and 108B included in one second active region 108I are formed between the buried bit line 150 and the buried bit line 150, And the first source / drain region 140 is formed. That is, in one active pillar 108A in one second active region 108I, the second source / drain region 44 (see FIG. 2A) and the first source / drain region 140 may be formed. Also in the one active region 108I, the second source / drain region 44 (see FIG. 2A) formed on the upper surface of the active pillars 108B and the first source / One vertical channel may be formed between the region 140 and the substrate.

The plurality of buried bit lines 150 may comprise a metal, a metal nitride, or a combination thereof. For example, the buried bit line 150 may be formed from a group of tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), and ruthenium And may include one or more metals selected. Alternatively, the buried bit line 150 may be formed of a material selected from the group consisting of titanium nitride (TiN), titanium nitride / tungsten (TiN / W), titanium / titanium nitride Ti / TiN, tungsten nitride WN, tungsten / tungsten nitride ), At least one metal nitride selected from the group consisting of tantalum nitride (TaN), tantalum / tantalum nitride (Ta / TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN) and tungsten silicon nitride (WSiN) . In addition, the plurality of buried bit lines 150 may have a multi-layer structure including a diffusion prevention layer (not shown).

The plurality of buried bit lines 150 may have a top surface formed at a second depth P2. Alternatively, it may be formed higher or lower. In this case, the upper surfaces of the plurality of buried bit lines 150 are formed lower than the upper surface of the substrate 102, and the bottom surfaces of the plurality of buried bit lines 150 are formed higher than the bottom surface of the second isolation film 136 .

The plurality of buried bit lines 150 are formed so that the bottom surface of the portion located on the second active region 108I and the bottom surface of the portion located on the first isolation film 106 and the second isolation film 136 are substantially the same And the distance from the upper surface of the substrate 102 can be made approximately the same. 10A and 10B, depending on the degree of etch back of the first active region 108I of the first isolation film 106, the second isolation film 136, and the substrate 102, The bottom surfaces of the plurality of buried bit lines 150 may be formed at different depths. As a result, the height of the buried bit line 150 formed on the second active region 108I and the buried bit line 150 formed on the second isolation film 136 is reduced to the same level, Can be different.

12A and 12B, an insulation material is deposited on the entire surface of the resultant formed with the buried bit line 150 so that the spaces inside the plurality of bit line trenches 124 and the isolation trenches 134 ' A planarization process is performed until a top surface of the substrate 102 is exposed using a CMP process so that the bit line trenches 124 and the device isolation trenches 134 ' 150 are formed on the upper surface of the semiconductor substrate. The buried insulating film 158 may be formed of, for example, a silicon nitride film or a silicon oxide film. During the CMP process, the second mask pattern 114 and the pad oxide film pattern 112 on the substrate 102 may be removed. Alternatively, the buried insulating layer 158 may be formed after the second mask pattern 114 and the pad oxide layer pattern 112 are removed by a separate process.

The buried insulating film 158 covers the buried bit line 150 in a space between two active pillars 108A and 108B included in each one second active region 108I. The buried insulating film 158 traverses the plurality of active regions 108 through the internal spaces of the bit line trenches 124 and the element isolation trenches 134 from above the plurality of buried bit lines 150, And extends in parallel with line 150.

13A and 13B, a process of forming the contact gate 174CG and the word line 174WL of the semiconductor device may be performed after the buried bit line 150 is formed. After the formation of the buried insulating layer 158, ion implantation for forming the second source / drain region 160 may be performed on the upper surface of the active pillars 108A and 108B of the exposed substrate 102.

After the oxide film pattern 164 is formed on the buried insulating film 158, a contact gate recess (not shown) is formed in an area where the contact gate 30CG (see FIG. 1) shown in FIG. 1 is to be formed. Thereafter, an insulating material for forming the gate insulating film 172G and an inner space of the gate recess (not shown) are filled in the inner wall of the contact gate recess (not shown) Thereby forming a conductive layer (not shown). Next, a pattern of the capping insulating layer 176 is formed on the conductive layer (not shown), and a plurality of word lines 174WL extending parallel to each other are formed.

The contact gate 174CG is disposed between two adjacent second active regions 108I along the x-direction and the y-direction in FIG. 1, for example, along the oblique (DL) do. A unit memory cell including one active pillar 108A included in one of the two adjacent second active areas 108I and one active pillar 108A included in one of the two adjacent second active areas 108I, The unit memory cell including one active pillar 108B included in the memory cell 108I shares one contact gate 174CG.

Next, a process of forming the buried contact hole 184H and the capacitor lower electrode 192 can be performed.

Insulating spacers 178 are formed on both sidewalls of the word line 174WL and the capping insulating film 176. [ The insulating spacer 178 may be formed of a silicon nitride film. A planarized insulating film 180 is formed on the entire surface of the substrate 102 on which the insulating spacer 178 is formed. The planarized insulating film 180 and the capping insulating film 176 are etched and the exposed oxide film pattern 164 is etched to form a plurality of buried contact holes 184H.

Thereafter, a conductive layer completely filling the plurality of buried contact holes 184H is formed, and then the conductive layer is planarized until the upper surface of the planarized insulating layer 180 is exposed, A plurality of buried contact plugs 184 are formed in the contact holes 184H.

The conductive layer for forming the plurality of buried contact plugs 184 may be formed of doped polysilicon. In this case, when the doped polysilicon is deposited in the plurality of buried contact holes 184H to form the plurality of buried contact plugs 184, the dopant contained in the doped polysilicon contacts the buried contact Drain region 160 may be diffused into the second active region 108I exposed through the hole 184H so that ion implantation for forming the second source / drain region 160 may be performed on the upper surface of the second active region 108I.

A plurality of capacitor lower electrodes 192 electrically connected to the plurality of buried contact plugs 184 are formed on the buried contact plugs 184. A plurality of lower electrodes 192 are formed in the plurality of storage node holes 190H in contact with the plurality of buried contact plugs 184 after the sacrificial insulating film pattern 190 having the plurality of storage node holes 190H is formed, .

Next, although not shown, the sacrificial insulating film pattern 190 is removed, and a plurality of capacitors are formed by forming a dielectric film and an upper electrode on the plurality of lower electrodes 192, respectively.

According to the method for fabricating a semiconductor device according to the embodiment of the present invention, in the process of forming the plurality of bit line trenches 124 and the process of forming the plurality of device isolation trenches 134, an undesired misalignment in the photolithography process The widths of the active pillars 108A and 108B in the plurality of second active regions 108I can be uniformly formed. That is, since a plurality of device isolation trenches 134 are formed on the first active region 108 in the form of a line, the width dispersion of active pillars 108A and 108B by misalignment can be reduced. Therefore, since the channel width of the contact gate 174CG is uniformly formed, electrical characteristic variations in the plurality of unit memory cells implemented on the substrate 102 can be minimized.

Since the buried bit line 150 is formed by self-aligning in the second isolation film 136, the buried bit line 150 formed in the second isolation film 136 and the adjacent second active region 108I can be electrically The possibility of a short circuit can be minimized.

FIG. 14 is a partial perspective view showing a three-dimensional arrangement relationship of components constituting a cell array region in a semiconductor device according to another embodiment of the present invention. FIG. In Fig. 14, the same reference numerals as those in Fig. 2A denote the same elements, and a duplicate description will be omitted.

14, a semiconductor device 200 according to the present invention includes a substrate 102 having a plurality of island-shaped active areas 10 defined by a first isolation layer 106 and a second isolation layer 136 ). The plurality of active regions 10 can be divided into two active pillars 10A and 10B on the upper surface side of the substrate 102 by the trenches 10T each recessed to a predetermined depth from the central portion of the upper surface thereof . A first source / drain region 42 is formed at a portion where the two active pillars 10A and 10B branch off from the plurality of active regions 10. A second source / drain region 44 may be formed on the top surfaces 12A and 12B of the two active pillars 10A and 10B, respectively.

A plurality of buried bit lines 20 may be located at the bottom of the trenches 10T to bisect the active pillars 10A, 10B in one active region 10. The plurality of buried bit lines 20 extend in the direction of the short axis Y of the plurality of active regions 10 in the substrate 102 while the active region 10, the first isolation film 106, Lt; RTI ID = 0.0 > 136 < / RTI >

The buried bit line 20 may be formed on the upper surface of the second isolation film 136. Thus, the upper surface of the second isolation film 136 is disposed below the buried bit line 20. [ The manufacturing method thereof will be described in detail below with reference to Figs. 15A and 15B.

The active pillars 10A and 10B in the active region 10 include a vertical side 10CH for providing a channel surface on which a vertical channel is formed. The vertical side 10CH may face the contact gate 30CG.

The bottom surface of the contact gate 30CG in the substrate 102 may be formed at the same depth as the top surface of the buried bit line 10. [ The distance from the top surfaces 12A and 12B of the active pillars 10A and 10B on the top surface of the substrate 102 to the bottom surface of the contact gate 30CG is larger than the distance from the top surfaces 12A and 12B of the active pillars 10A and 10B May be equal to the distance to the top surface of the buried bit line 20.

A plurality of word lines 30WL extend parallel to each other in a direction orthogonal to the extending direction of the plurality of buried bit lines 20 (x direction in FIG. 14). The plurality of word lines 30WL may be electrically connected to a plurality of contact gates 30CG arranged in a line along the extension direction thereof.

FIGS. 15A and 15B are views for explaining the method of manufacturing the semiconductor device of FIG. Fig. 15A is a sectional view corresponding to the cut lines BX1 - BX1 'and BX2 - BX2' in Fig. 7A. 15B is a cross-sectional view corresponding to the cut lines CY1-CY1 'and CY2-CY2' in Fig. 7A.

Referring to FIGS. 15A and 15B, the ion implantation process described above with reference to FIGS. 3A to 9B is performed after the same process is performed. However, in the ion implantation process of this embodiment, only a low concentration dopant region (not shown) for forming the first source / drain region 240 in the second active region 208I around the bottom of the bit line trench 224 A high concentration dopant region 243 may be formed. That is, both the low concentration dopant region (not shown) and the high concentration dopant region 243 can be formed. For example, the first source / drain region 240 may be formed by implantation of N-type impurity ions. In addition, the formation of the lightly doped region (not shown) by this step is optional and may be omitted depending on the characteristics of the desired device.

Next, the second active region 208I under the plurality of bit line trenches 224 and the element isolation trenches 234 ', which is the process described above with reference to FIGS. 10A and 10B, The buried bit line 250 is formed without performing a process of partially removing the first isolation film 206 and the second isolation film 236. The process of forming the buried bit line 250 is the same as the process described above with reference to FIGS. 11A and 11B. A conductive material is deposited on the resultant structure in which the first source / drain regions 240 are formed to form conductive layers filling the bit line trenches 224 and the element isolation trenches 234. Thereafter, a plurality of bit line trenches 224 and a plurality of buried bit lines 250 made of conductive layers remaining on the bottom surfaces of the element isolation trenches 234 are formed by etch-back.

The subsequent process can be performed in the same manner as the process described above with reference to Figs. 12A to 13B.

According to the method of manufacturing a semiconductor device according to the present embodiment, since the etch back process for the portions under the plurality of bit line trenches 224 and the device isolation trenches 234 'is omitted, the process can be further simplified.

16 is a plan view of a memory module 1000 including a semiconductor device according to the technical idea of the present invention.

The memory module 1000 may include a printed circuit board 1100 and a plurality of semiconductor packages 1200.

A plurality of semiconductor packages 1200 may include semiconductor devices according to embodiments of the present invention. In particular, the plurality of semiconductor packages 1200 may include a characteristic structure of at least one semiconductor device selected from the semiconductor devices shown in Figs. 1 to 15B according to the technical idea of the present invention described above.

The memory module 1000 according to the technical idea of the present invention is a SIMM (Single In-Line Memory Module) having a plurality of semiconductor packages 1200 mounted on only one side of a printed circuit board or a plurality of semiconductor packages 1200, Or a dual in-line memory module (DIMM). In addition, the memory module 1000 according to the technical idea of the present invention may be a fully buffered DIMM (FBDIMM) having an AMB (Advanced Memory Buffer) that provides signals from the outside to a plurality of semiconductor packages 1200, respectively.

17 is a schematic view of a memory card 2000 including a semiconductor device according to the technical idea of the present invention.

The memory card 2000 may be arranged such that the controller 2100 and the memory 2200 exchange electrical signals. For example, if the controller 2100 issues a command, the memory 2200 can transmit data.

The memory 2200 may include a semiconductor device according to embodiments of the present invention. In particular, the memory 2200 may include a characteristic structure of at least one semiconductor device selected from the semiconductor devices shown in Figs. 1 to 15B according to the technical idea of the present invention described above.

The memory card 2000 may include various types of cards such as a memory stick card, a Smart Media card (SM), a Secure Digital card (SD), a Mini-Secure Digital A memory card, a mini-Secure Digital card, and a MultiMedia Card (MMC).

18 is a schematic diagram of a system 3000 including a semiconductor device according to the technical idea of the present invention.

In the system 3000, the processor 3100, the memory 3200, and the input / output device 3300 can communicate with each other using a bus 3400.

The memory 3200 of the system 3000 may include a random access memory (RAM) and a read only memory (ROM). In addition, the system 3000 may include a peripheral device 3500 such as a floppy disk drive and a CD (compact disk) ROM drive.

The memory 3200 may include a semiconductor device according to embodiments of the present invention. In particular, the memory 3200 may include a characteristic structure of at least one semiconductor device selected from the semiconductor devices shown in FIGS. 1 to 15B according to the technical idea of the present invention described above.

The memory 3200 may store code and data for operation of the processor 3100. [

The system 3000 may be implemented in a mobile phone, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state disk (SSD), or a household appliances Can be used.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

10: active region 10A, 10B: active pillar
10T: Trench 10CH: Vertical side
12A, 12B: upper surface 20: buried bit line
CP_20: Core / Perry bit line 30CG: Contact gate
30 WL: word line 42: first source / drain region
44: second source / drain region 50: buried contact plug
100, 200: semiconductor element 102: substrate
104: trench 106: first element isolation film
108: first active region 108A, 108B: active pillar
112: pad oxide film pattern 114: first mask pattern
124: bit line trench 126: insulating film liner
130: second mask pattern 134, 134 ': element isolation trench
136: second isolation film 140: first source / drain region
142: low concentration dopant region 143: high concentration dopant region
150: buried bit line 158: buried insulating film
160: second source / drain region 164: oxide film pattern
172G: gate insulating film 174CG: contact gate
174 WL: word line 176: capping insulating film
178: Insulation spacer 180; The planarized insulating film
184H: buried contact hole 184: buried contact plug
190: sacrificial insulating film pattern 190H: storage node hole
192: capacitor lower electrode

Claims (10)

Forming a plurality of line-shaped first device isolation films on the substrate extending from the upper surface of the substrate to a first depth and extending in a first direction to define a plurality of line-shaped active regions extending in the first direction;
Forming a plurality of trenches extending in a second direction perpendicular to the first direction and having a second depth less than the first depth and having a first width;
Forming a plurality of device isolation trenches having a third depth greater than the second depth by etching the substrate on the bottom surface of the plurality of trenches selected at regular intervals among the plurality of trenches;
Forming a second device isolation layer including an insulating material below the plurality of device isolation trenches; And
Forming buried bit lines on the bottom surface of the plurality of trenches and the plurality of device isolation trenches;
Wherein the semiconductor device is a semiconductor device. The method according to claim 1,
In the step of forming the second element isolation film,
Wherein the second isolation film is formed by oxidizing the substrate exposed on the bottom and side surfaces of the plurality of element isolation trenches. The method according to claim 1,
After forming the plurality of trenches,
Forming an insulating film liner in the plurality of trenches;
Further comprising the step of: The method of claim 3,
Wherein forming the plurality of device isolation trenches comprises:
Forming a mask pattern including an opening for exposing the plurality of trenches in an area in which the element isolation trenches are to be formed among the plurality of trenches;
Removing the insulating film liner on the bottom surface of the plurality of trenches exposed by the opening; And
Etching the substrate on the bottom surface of the plurality of trenches exposed by the removed insulating film liner;
And forming a second insulating film on the semiconductor substrate. The method of claim 3,
In the step of forming the second element isolation film,
Wherein the second isolation film is formed by a LOCOS method for selectively oxidizing the bottoms of the plurality of element isolation trenches using the insulating film liner formed on the sidewall of the plurality of element isolation trenches as an oxidation prevention film A method of manufacturing a semiconductor device. The method according to claim 1,
In forming the plurality of element isolation trenches,
The plurality of device isolation trenches are formed in an area alternately selected along the second direction among the plurality of trenches alternately selected along the first direction intersecting with the plurality of active areas Wherein the semiconductor device is a semiconductor device. The method according to claim 1,
After forming the second isolation film,
Partially etching the substrate and the first isolation film on the bottom surface of the plurality of trenches and the second isolation film on the bottom surface of the plurality of isolation trenches;
Further comprising the step of: The method according to claim 1,
After the step of forming the second element isolation film,
An ion implantation step for forming a first source region and a drain region;
Further comprising the step of: The method according to claim 1,
And the bottom face of the buried bit line is located at a depth smaller than the second depth. The method according to claim 1,
Wherein the active region comprises two active pillars between the plurality of device isolation trenches, wherein the active pillars are bisected about the plurality of trenches.

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