KR20020049373A - Method for Fabricating of Semiconductor Device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent an etch stop phenomenon in forming a contact and to prevent a short circuit between the contact and a gate line, by increasing the critical dimension of the first interlayer dielectric exposed by etching the second etch barrier layer. CONSTITUTION: A predetermined isolation region is formed in a semiconductor substrate(31) to define a field region and an active region. A gate(33) is formed on the semiconductor substrate in the active region. An insulation layer sidewall(34) is formed on both side surface of the gate. The first etch barrier layer(35) is formed on the semiconductor substrate. The first interlayer dielectric(36) and the second etch barrier layer(37) are sequentially formed on the entire surface. The second etch barrier layer is selectively removed to expose a predetermined region of the first interlayer dielectric in which the critical dimension of the region is from 0.9 to 1.1 pitch. The second interlayer dielectric(38) is formed on the semiconductor substrate. The second interlayer dielectric is formed on a region from which the second etch barrier layer is removed and its adjacent region in a polymer formation atmosphere. The first interlayer dielectric exposed by removing the second etch barrier layer and the first etch barrier layer under the first interlayer dielectric are eliminated to form a contact hole. The contact hole is filled with a conductive material to form a metal line(41).

Description

Method for manufacturing a semiconductor device {Method for Fabricating of Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for preventing an electrical short circuit between a contact and a gate line by preventing an etch stop phenomenon of a self-aligned etching process.

In a memory device with a design rule of 0.15 μm or more, a metal plug is formed to electrically connect a contact to the outside, and a metal line is formed thereon to form a metal plug. The electrical connection of the metal line was made.

But. In a memory device having a design rule of 0.15 μm or less, misalignment occurs due to a lack of an overlay margin with an underlying layer.

In this case, as the contact area of the metal plug and the metal line is reduced, there is a problem in that the contact resistance is increased to deteriorate the characteristics of the device.

In order to solve this problem, a dual damascene process is used in which a metal plug and a metal line are formed at the same time to secure a contact contact resistance more than a predetermined specification. However, as contact holes are formed in addition to the active region, contact and Due to misalignment of the gate lines, there is a problem that an electrical short circuit occurs between the metal plug and the gate.

In order to prevent this, a self-aligned etching method having a selectivity to the lower layer through polymer formation is being researched and developed.

Hereinafter, a manufacturing method of a conventional semiconductor device will be described.

1A to 1D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, a field oxide film 12 is formed on a semiconductor substrate 11 by a shallow trench isolation (STI) process to define a field region and an active region.

A plurality of gates 13 are formed on a predetermined region of the semiconductor substrate 11.

Here, the gate 13 is a stack gate, for example, a polysilicon film (Poly-Si), a tungsten silicon film (W-Si) and a silicon nitride film (SiN).

An insulating film is deposited on the semiconductor substrate 11 and the insulating film sidewall 14 is formed by etching back the insulating film so as to remain on both sides of the gate 13.

In order to minimize the loss of the field oxide layer 12 during contact etching, a first etch stop layer 15 is deposited on the surface of the semiconductor substrate 11.

Here, the first etch stop layer 15 is a nitride film.

As shown in FIG. 1B, a first interlayer insulating layer 16 is formed on the semiconductor substrate 11, and a second etch stop layer 17 is deposited on the first interlayer insulating layer 16.

Here, the first interlayer insulating film 16 is an oxide film, and the second etch stop layer 17 is a nitride film.

The second etch stop layer 17 is selectively removed to expose the first interlayer insulating layer 16 by a photo and etching process.

In this case, the second etch stop layer 17 is etched such that the first interlayer insulating layer 16 is exposed to the CD size of the gate 13.

As shown in FIG. 1C, a second interlayer insulating film 18 is deposited on the semiconductor substrate 11, and a photoresist 19 is coated on the second interlayer insulating film 18.

The photoresist 19 is patterned to expose the exposed first interlayer insulating layer 16 and the second interlayer insulating layer 18 adjacent to the second etch stop layer 17 adjacent thereto. .

The second interlayer insulating layer 18 may be exposed to a predetermined portion of the field oxide layer 12 by a self-aligned etching process using the patterned photoresist 19 and the second etch stop layer 17 as a mask in a polymer forming atmosphere. ), The first interlayer insulating layer 16 and the first etch stop layer 15 are removed to form the contact hole 20.

In this case, an area of the first interlayer insulating layer 16 exposed by the second etch stop layer 17 is small, and a polymer is deposited on both sides of the contact hole 20 in the contact hole 20 etching process so that the contact hole ( 20) Since the size is reduced, they are stuck together and the etching process is stopped.

As shown in FIG. 1D, the photoresist 19 is removed, and a tungsten film is deposited on the semiconductor substrate 11 including the contact hole 20.

In addition, the tungsten layer is removed by a chemical mechanical polishing (CMP) process to form a metal line 21 in the contact hole 20 to complete a semiconductor device according to the prior art.

However, the conventional method of manufacturing a semiconductor device as described above has a problem that the contact and the gate line are electrically shorted due to the etching stop phenomenon of the self-aligned etching process, thereby causing a defect in the device and lowering the yield.

An object of the present invention is to provide a method for manufacturing a semiconductor device suitable for improving the yield of the device by preventing the etch stop phenomenon of the self-aligned etching process to solve the above problems.

1A to 1D are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols for the main parts of drawings

31 semiconductor substrate 32 field oxide film

33 gate 34 insulating film sidewall

35 first etching preventing film 36 first interlayer insulating film

37: second etching preventing film 38: second interlayer insulating film

39: photoresist 40: contact hole

41: metal line

The semiconductor device manufacturing method of the present invention for achieving the above object is to form a device isolation region on the semiconductor substrate to define a field region and an active region, and to form a gate on the semiconductor substrate of the active region Forming insulating film sidewalls on both sides, forming a first etch stop layer on the surface of the semiconductor substrate, and then forming a first interlayer insulating film and a second etch stop layer on the front surface, and a CD size of 0.9 to 1.1 pitch. Selectively removing the second etch stop layer to expose a predetermined region of the first interlayer insulating layer, forming a second interlayer insulating film on the entire surface of the semiconductor substrate, and removing the second etch stop layer in a polymer forming atmosphere. A second interlayer insulating layer over the region adjacent to the region and the first interlayer exposed by removing the second etch stop layer And forming a contact hole by removing the insulating film and the first etch stop layer under the insulating film, and forming a metal line by filling a conductive material in the contact hole.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.

In the prior art, a method of manufacturing a semiconductor device, as shown in FIG. 2A, defines a field region and an active region by forming a field oxide layer 32 in a predetermined region of a semiconductor substrate 31 by a shallow trench isolation (STI) process. do.

Then, a polysilicon film, a tungsten silicon film, and a silicon nitride film are sequentially deposited on the semiconductor substrate 31 in the active region, and a nitride film hard mask (not shown) is deposited on the entire surface at a thickness of 1500 to 2000 GPa.

The nitride film hard mask is patterned to remain on the semiconductor substrate 31 in the active region.

The silicon nitride film, the tungsten silicon film, and the polysilicon film are selectively removed using the patterned nitride film hard mask to form a plurality of gates 33.

Then, a surface oxide film (not shown) is formed on the surface of the semiconductor substrate 31 to a thickness of 100 to 200Å, a nitride film is deposited on the entire surface, and the entire surface is etched back to etch back the both sides of the gate 33. An insulating film sidewall 34 is formed on the substrate.

In order to minimize the loss of the field oxide layer 32 during contact etching, a first etch stop layer 35 is formed on the surface of the semiconductor substrate 31 to have a thickness of 150 to 200 占 퐉.

Here, the first etch stop layer 35 is a nitride film.

2B, a first interlayer insulating layer 36 is formed on the semiconductor substrate 31, and a second etch stop layer 37 is formed on the first interlayer insulating layer 36.

Here, the first interlayer insulating film 36 is formed of an oxide film so as to have a thickness of 1500 to 2000 kPa from the upper surface of the gate 33, and the second etch stop layer 37 is formed of a nitride film of 300 to 600 kPa.

The second etch stop layer 37 is selectively removed to expose the first interlayer insulating layer 36 at a CD size of 0.9 to 1.1 pitch in the photo and etching process.

As shown in FIG. 2C, a second interlayer insulating film 38 is formed on the entire surface of the semiconductor substrate 31, and a photoresist 39 is coated on the second interlayer insulating film 38.

Here, the second interlayer insulating film 38 is an oxide film and is deposited to have a thickness of 3000 to 10000 kPa.

The photoresist 39 is patterned to expose the exposed first interlayer insulating layer 36 and the second interlayer insulating layer 38 adjacent to the second etch stop layer 37 adjacent thereto. .

The second interlayer insulating film 38 may be exposed to a predetermined portion by a self-aligned etching process using the patterned photoresist 39 and the second etch stop layer 37 as a mask in a polymer forming atmosphere. The first interlayer insulating layer 36 and the first etch stop layer 35 are removed to form the contact hole 40.

At this time, the contact hole 40 is formed along the surface of the insulating film sidewall 34 due to the polymer generation.

As shown in FIG. 2D, a tungsten (W) film is deposited on the semiconductor substrate 31 including the contact hole 40, and the tungsten remains only inside the contact hole 40 by a chemical mechanical polishing (CMP) process. The film is removed to form a metal line 41 to complete the semiconductor device of the present invention.

As described above, the method of manufacturing a semiconductor device according to the present invention increases the CD of the first interlayer insulating layer exposed by etching the second etch stop layer, thereby preventing an etch stop phenomenon when forming a contact, thereby preventing a short circuit between the contact and the gate line. It can work.

Claims (3)

Forming a device isolation region in the semiconductor substrate to define a field region and an active region; Forming a gate on the semiconductor substrate in the active region and forming insulating film sidewalls on both sides thereof; Forming a first etch stop layer on a surface of the semiconductor substrate and sequentially forming a first interlayer insulating layer and a second etch stop layer on a front surface of the semiconductor substrate; Selectively removing the second etch stop layer such that a predetermined region of the first interlayer insulating layer is exposed with a CD size of 0.9 to 1.1 pitch; Forming a second interlayer insulating film on the entire surface of the semiconductor substrate and removing the second etch stop layer in a polymer forming atmosphere; Forming a contact hole by removing the interlayer insulating film and the first etch stop layer under the interlayer insulating film; And embedding a conductive material in the contact hole to form a metal line. The method of claim 1, wherein the first etch stop layer and the second etch stop layer are formed of a nitride film, and the first interlayer insulating film and the second interlayer insulating film are formed of an oxide film. The method of manufacturing a semiconductor device according to claim 1, wherein the second interlayer insulating film is formed to a thickness of 3000 to 10000 GPa.