KR100304967B1 - Metal line of semiconductor device and method for fabricating the same - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring of a semiconductor device and a method of forming the same for forming reliable contact wiring by reducing loss of an isolation region in a borderless contact. In order to achieve the above object, wiring of a semiconductor device includes a trench isolation region formed in an isolation region of a semiconductor substrate, a gate insulating film and a gate electrode stacked on an active region of the semiconductor substrate, and impurities formed in the semiconductor substrate on both sides of the gate electrode. A first insulating film formed on the semiconductor substrate including the region, the gate electrode, and a fourth insulating film above the gate electrode and the impurity region so that the third insulating film on the gate electrode is not exposed. A portion formed with a first width in the same depth therein, and a contact window formed in the first, second, third, and fourth insulating films in a width narrower than the first width so that the gate electrode and the impurity region are exposed; A barrier metal layer formed along the contact window surface, and a contact wiring layer formed in the contact window on the barrier metal layer. Characterized by configured.

Description

Wiring and Forming Method of Semiconductor Device {METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a wiring of a semiconductor device suitable for borderless contact and a method of forming the same.

Referring to the accompanying drawings, a method of forming a wiring of a conventional semiconductor device will be described below.

1A to 1F are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.

In the conventional wiring forming method of the semiconductor device, as shown in FIG. 1A, a trench is formed in an isolation region of the semiconductor substrate 1, and an insulating film is formed to fill the trench to form the trench isolation region 2. Thereafter, the gate insulating film 3 and the gate electrode 4 are stacked in one region of the active region of the semiconductor substrate 1. The source / drain impurity regions 5 are formed in the semiconductor substrate 1 on both sides of the gate electrode 4.

The interlayer insulating film 6 is deposited on the entire surface of the semiconductor substrate 1 including the gate electrode 4 with an oxide film, and then the interlayer insulating film 6 is planarized by a chemical mechanical polishing process.

Next, as shown in FIG. 1B, a first photosensitive film 7 is coated on the interlayer insulating film 6, and then an upper side of the source / drain impurity region 5 on one side of the gate electrode 4 and the gate electrode 4 is applied. The first photosensitive film 7 is selectively patterned by an exposure and development process so as to open. Subsequently, the interlayer insulating film 6 is etched to expose the gate electrode 4 and the source / drain impurity region 5 on one side of the gate electrode 4 by using the patterned first photoresist film 7 as a mask. ).

In this case, the contact window of the source / drain impurity region 5 on one side of the gate electrode 4 may extend to one side of the trench isolation region 2 so that one side of the trench isolation region 2 may be damaged as shown in FIG. 1B. .

After removing the first photosensitive film 7 as shown in FIG. 1C, the barrier metal layer 9 and the metal layer 10 made of tungsten or sphere are deposited on the entire surface of the interlayer insulating film 6 including the contact window 8. do.

As shown in FIG. 1D, the contact plug 10a is formed in the contact window 8 by chemical mechanical polishing or etch back process. At this time, the barrier metal layer 9 remains as it is.

As shown in FIG. 1E, an aluminum layer 11 is deposited on the entire surface in contact with the contact plug 10a, and a second photosensitive film 12 is coated on the aluminum layer 11. The second photosensitive film 12 is patterned. In this case, the second photoresist layer 12 is patterned to remain selectively only on the contact plug 10a.

Subsequently, as shown in FIG. 1F, the aluminum layer 11 and the barrier metal layer 9 are anisotropically etched using the patterned second photosensitive layer 12 as a mask to form the aluminum wiring layer 11a on the contact plug 10a. do.

The wiring formation method of the conventional semiconductor device as described above has the following problems.

Since the interlayer insulating film is formed of only an oxide film, a direct contact window is formed on the gate electrode and the source / drain impurity region, thereby damaging the upper portion of the gate electrode. In addition, one side of the trench isolation region may be lost in the contact window portion extending from the source / drain impurity region to the trench isolation region to generate a junction leakage current.

The present invention has been made to solve the above problems, and in particular, provides a semiconductor device wiring and a method of forming the same for forming a reliable contact wiring by reducing the loss of the isolation region in borderless contact (Borderless Contact) Its purpose is to.

1A to 1F are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.

2 is a structural sectional view showing the wiring of the semiconductor device of the present invention

3A to 3G are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 trench isolation region

33: gate insulating film 34: gate electrode

35 first nitride film 36 first oxide film

37: second nitride film 38: second oxide film

39: first photosensitive film 40: first contact window

41 second photosensitive film 42 second contact window

43: barrier metal layer 44: metal layer

44a: contact wiring layer

The wiring of the semiconductor device according to the present invention for achieving the above object is a trench isolation region formed in an isolation region of the semiconductor substrate, a gate insulating film and a gate electrode formed on the active region of the semiconductor substrate, the semiconductor substrate on both sides of the gate electrode The first and second, third and fourth insulating layers formed on the semiconductor substrate including the gate electrode and the third insulating layer above the gate electrode so as not to be exposed. A contact portion formed in the first, second, third, and fourth insulating films having a width narrower than the first width so as to expose the gate electrode and the impurity region, and a portion formed in the insulating film having the first width at the same depth. A window, a barrier metal layer formed along the contact window surface, and a contact wiring layer formed in the contact window on the barrier metal layer. Characterized in that configured to include.

In a method of forming a wiring of a semiconductor device according to the present invention, the method may include forming a trench isolation region in an isolation region of a semiconductor substrate, stacking a gate insulating layer and a gate electrode in an active region of the semiconductor substrate, and forming the gate electrode. Forming an impurity region in the semiconductor substrate at both sides, and depositing first, second, third, and fourth insulating films on the semiconductor substrate including the gate electrode in order, and above the gate electrode and one side of the gate electrode Etching the fourth insulating film and the third insulating film to form a first contact window so that the second insulating film over the impurity region of the substrate is exposed, and the first insulating film is exposed by a mask having a width wider than that of the first contact window. The fourth insulating film and the second insulating film on the impurity region on the gate electrode and on one side of the gate electrode are etched until Forming a second contact window by removing the first insulating film so that the impurity region of the gate electrode and one side of the gate electrode is exposed; forming a barrier metal layer along the surfaces of the first and second contact windows; And forming a contact wiring layer in the first and second contact windows on the barrier metal layer.

A wiring and a method of forming the semiconductor device of the present invention will be described with reference to the accompanying drawings.

2 is a structural cross-sectional view showing the wiring of the semiconductor device of the present invention, Figures 3a to 3g is a process cross-sectional view showing a wiring forming method of the semiconductor device of the present invention.

The present invention relates to the formation of wires for borderless contacts. The structure of the interlayer insulating film is deposited between the oxide film and the nitride film with a high etch selectivity between the oxide film, and then the upper side of the gate electrode and one side thereof by a multi-step etching method. When the contact window is formed in the contact hole of the same etching time to reduce the overall etching time and at the same time to reduce the loss of the trench isolation region, the configuration and method will be described in more detail as follows.

2, the trench isolation region 32 is formed in an isolation region of the semiconductor substrate 31, and the gate insulation layer 33 is formed in one region of the active region of the semiconductor substrate 31. ) And a gate electrode 34 are formed. A source / drain impurity region 30 is formed in the semiconductor substrate 31 on both sides of the gate electrode 34.

The first nitride film 35, the first oxide film 36, the second nitride film 37, and the second oxide film 38 are sequentially deposited on the entire surface including the gate electrode 34. At this time, the first and second nitride films 35 and 37 are formed to a thickness of 500 kPa or less, and the second oxide film 38 is deposited thicker than the first oxide film 36.

The first nitride layer 35, the first oxide layer 36, and the second nitride layer 37 are exposed to expose the source / drain impurity region 30, the trench isolation region 32 adjacent thereto, and the upper portion of the gate electrode 34. A contact window is formed in the second oxide film 38.

In this case, the contact window is formed with a first width at a depth where the second nitride film 37 on the gate electrode 34 is not exposed, and the source / drain impurity region 30 is narrower than the first width. The upper portion of the gate electrode 34 may be divided into portions that are exposed.

In this case, a portion having a first width in the contact window is formed to have the same depth on the gate electrode 34 and the source / drain impurity region 30. This is because the etching time for forming the contact window on the gate electrode 34 and the source / drain impurity region 30 is the same.

The contact window formed on the source / drain impurity region 30 may extend beyond the boundary region with the trench isolation region 32 adjacent thereto.

A barrier metal layer 43 is formed along the surface of the contact window so as to contact the source / drain impurity region and the gate electrode 34, and a contact wiring layer 44a made of tungsten or copper is formed flat in the contact window. .

In this case, the trench isolation region 32 below the contact window formed on the source / drain impurity region 30 and the trench isolation region 32 adjacent thereto is formed intact and flat. In other words, the trench isolation region 32 under the borderless contact is formed intact and flat.

In the wiring forming method of the semiconductor device of the present invention having the above configuration, as shown in FIG. 2A, the trench isolation region 32 is formed by forming a trench in an isolation region of the semiconductor substrate 31 and forming an insulating film to fill the trench. To form.

Thereafter, a gate insulating film 33 and a gate electrode 34 are stacked in one region of the active region of the semiconductor substrate 31. The source / drain impurity region 30 is formed in the semiconductor substrate 31 on both sides of the gate electrode 34.

3B, the first nitride film 35, the first oxide film 36, the third nitride film 37, and the fourth oxide film 38 are disposed on the entire surface of the semiconductor substrate 31 including the gate electrode 34. To form a laminate.

At this time, the first and second nitride films 35 and 37 are thinly deposited to 500 Å or less.

The second oxide film 38 is deposited thicker than the first oxide film 36. This is because the second oxide film 38 is also used to etch the first oxide film 36 using the second photoresist film 41 as a mask when the second contact window 42 is formed after the first contact window 40 is formed. This is because the second nitride film 37 is not exposed at this time.

Subsequently, as illustrated in FIG. 3C, the first photoresist film 39 is coated on the entire surface, and the first contact window is formed on the source / drain impurity region 30 on one side of the gate electrode 34 and on one side of the gate electrode 34. For this purpose, the first photosensitive film 39 is selectively patterned by exposure and development processes.

Thereafter, the second oxide film 38 and the second nitride film 37 are removed to form the first contact window 40 so that the second oxide film 36 is exposed using the patterned first photoresist film 39 as a mask. . Then, the first photosensitive film 39 is removed.

As shown in FIG. 3D, the second photoresist layer 41 is coated on the entire surface, and an exposure and development process is performed so that the upper part of the upper side of the gate electrode 34 and the one side of the trench isolation region 32 is extended to open. The second photosensitive film 41 is selectively patterned. At this time, the patterned width of the second photosensitive film 41 is wider than the patterned width of the first photosensitive film 41.

Thereafter, as shown in FIG. 3E, the first oxide layer 36 is anisotropically etched using the patterned second photosensitive layer 41 as a mask until the first nitride layer 35 is exposed.

Thereafter, the first nitride layer 35 is removed to expose the source / drain impurity region 30 on the upper side of the gate electrode 34 and one side of the trench isolation region 32, and the one side of the gate electrode 34 to remove the second contact window ( To form 42).

When the first oxide layer 36 is etched, the second oxide layer 38 is also etched using the patterned second photosensitive layer 41 as a mask, and the thickness of the second oxide layer 38 is equal to the first oxide layer 36. It is thicker than, so that the second nitride film 37 is not etched.

Next, as shown in FIG. 3F, the second photosensitive film 41 is removed and a barrier metal layer 43 and a metal layer 44 such as tungsten or copper are deposited on the entire surface.

Thereafter, as shown in FIG. 3G, the planarization process is performed to form the contact wiring layer 44a evenly between the first and second contact windows 40 and 42.

The wiring and the method of forming the semiconductor device of the present invention as described above have the following effects.

First, in the contact window formed on the gate electrode and the source / drain impurity region, the depth of the wide first width portion is formed only to the upper part of the second nitride film on the gate electrode, thereby preventing damage to the upper part of the gate electrode later. In addition, one side of the trench isolation region may be prevented from being damaged due to overetching.

Second, since a nitride film having an etch selectivity higher than that of an oxide film is formed between the oxide films as an interlayer insulating film, a multi-step etching method is used, so that the etching time of the contact window is the same at the top of the gate electrode and the top of the source / drain impurity region, thereby reducing the overall etching time. have.

Claims (12)

Trench isolation regions formed in the isolation region of the semiconductor substrate, A gate insulating film and a gate electrode stacked on an active region of the semiconductor substrate; An impurity region formed in the semiconductor substrate on both sides of the gate electrode, First, second, third, and fourth insulating films formed on the semiconductor substrate including the gate electrode; A portion having a first width at a same depth within the gate electrode and the fourth insulating layer above the impurity region so that the third insulating layer on the gate electrode is not exposed, and the gate electrode and the impurity region are exposed. A contact window formed in the first, second, third, and fourth insulating films in a width narrower than one width; A barrier metal layer formed along the contact window surface; And a contact wiring layer formed in the contact window on the barrier metal layer. 2. The wiring of claim 1, wherein the first and third insulating films are formed of a nitride film. The wiring of a semiconductor device according to claim 1, wherein said second and fourth insulating films are formed of an oxide film. The semiconductor device wiring according to claim 1, wherein said first and third insulating films have a thickness of 500 kW or less. The semiconductor device wiring according to claim 1, wherein the fourth insulating film is formed thicker than the third insulating film. The wiring of claim 1, wherein the contact window formed on the impurity region extends to one side of the trench isolation region adjacent to the contact window. Forming a trench isolation region in the isolation region of the semiconductor substrate, Stacking a gate insulating film and a gate electrode in an active region of the semiconductor substrate; Forming an impurity region in the semiconductor substrate on both sides of the gate electrode; Sequentially depositing first, second, third and fourth insulating films on the semiconductor substrate including the gate electrode; Etching the fourth insulating film and the third insulating film to form a first contact window so that the second insulating film on the gate electrode and on the impurity region on one side of the gate electrode is exposed; Etching the fourth insulating film and the second insulating film on the impurity region above the gate electrode and on one side of the gate electrode until the first insulating film is exposed by a mask having a width wider than the first contact window; Forming a second contact window by removing the first insulating layer to expose the gate electrode and an impurity region on one side of the gate electrode; Forming a barrier metal layer along the surface of the first and second contact windows; And forming a contact wiring layer in the first and second contact windows on the barrier metal layer. 8. The method of claim 7, wherein the first and third insulating films are formed of a nitride film. 8. The method of claim 7, wherein the second and fourth insulating films are formed of an oxide film. 8. The method of claim 7, wherein the first and third insulating films are formed to have a thickness of 500 kW or less. 8. The method of claim 7, wherein the fourth insulating film is formed thicker than the second insulating film. 8. The method of claim 7, wherein the second contact window extends to one side of the trench isolation region.