KR100315457B1 - a manufacturing method of a semiconductor device - Google Patents

a manufacturing method of a semiconductor device Download PDF

Info

Publication number
KR100315457B1
KR100315457B1 KR1019990067720A KR19990067720A KR100315457B1 KR 100315457 B1 KR100315457 B1 KR 100315457B1 KR 1019990067720 A KR1019990067720 A KR 1019990067720A KR 19990067720 A KR19990067720 A KR 19990067720A KR 100315457 B1 KR100315457 B1 KR 100315457B1
Authority
KR
South Korea
Prior art keywords
film
oxide film
contact hole
wiring
tungsten
Prior art date
Application number
KR1019990067720A
Other languages
Korean (ko)
Other versions
KR20010066136A (en
Inventor
박태희
Original Assignee
황인길
아남반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남반도체 주식회사 filed Critical 황인길
Priority to KR1019990067720A priority Critical patent/KR100315457B1/en
Publication of KR20010066136A publication Critical patent/KR20010066136A/en
Application granted granted Critical
Publication of KR100315457B1 publication Critical patent/KR100315457B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

절연막 위에 알루미늄과 같은 금속 따위로 이루어진 배선을 형성하고 배선 위에 TEOS 산화막과 같은 절연막을 증착한다. 이어, TEOS 산화막을 식각하여 배선을 드러내는 접촉 구멍을 형성하고 접촉 구멍의 벽에 배리어막을 증착한 후 텅스텐막으로 접촉 구멍을 채운다. 이어, 텅스텐막 위에 산화막을 증착하고 산화막 위에 접촉 구멍과 동일한 패턴의 감광막 패턴을 형성한다. 이어, 감광막 패턴을 마스크로 산화막을 식각하여 텅스텐막 위에 산화막을 남긴다. 이때, 오정렬로 인한 마진을 확보하기 위해 산화막을 경사지게 식각하여 산화막이 접촉 구멍의 크기보다 더 넓은 범위로 남도록 한다. 이어, 감광막 패턴을 제거한 후 CF4기체 따위를 이용하여 산화막과 텅스텐막을 식각한다. 이때, 텅스텐막보다 산화막의 식각이 더 빠른 식각 선택비로 식각하여 배리어막과 동일한 높이로 평탄하게 텅스텐막이 남게 된다. 이렇게 평탄화된 텅스텐막 위에는 배선을 균일하게 형성할 수 있다.A wiring made of a metal such as aluminum is formed on the insulating film, and an insulating film such as a TEOS oxide film is deposited on the wiring. Subsequently, the TEOS oxide film is etched to form a contact hole that exposes the wiring, a barrier film is deposited on the wall of the contact hole, and the contact hole is filled with a tungsten film. Next, an oxide film is deposited on the tungsten film, and a photosensitive film pattern having the same pattern as that of the contact hole is formed on the oxide film. Subsequently, the oxide film is etched using the photoresist pattern as a mask to leave an oxide film on the tungsten film. At this time, the oxide film is etched obliquely to secure a margin due to misalignment so that the oxide film remains in a wider range than the size of the contact hole. Subsequently, the oxide film and the tungsten film are etched using the CF 4 gas after removing the photoresist pattern. At this time, the oxide film is etched at an etching selectivity faster than the tungsten film, so that the tungsten film remains flat at the same height as the barrier film. The wiring can be evenly formed on the flattened tungsten film.

Description

반도체 소자의 제조 방법{a manufacturing method of a semiconductor device}A manufacturing method of a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device.

일반적으로 반도체 소자에는 n형 또는 p형의 기판 위에 채널, 소스, 드레인 영역 등의 불순물이 도핑되어 있는 활성(active) 영역이 형성되어 있으며, 그 위에는 각각의 영역 상부에 접촉 구멍(contact)을 가지는 절연막이 형성되어 있으며 절연막 위에는 접촉 구멍을 통하여 각각의 영역과 연결되는 배선이 형성되어 있다.In general, a semiconductor device is formed with an active region doped with impurities such as a channel, a source, and a drain region on an n-type or p-type substrate, and a contact hole is formed over each region. An insulating film is formed, and wirings connected to the respective regions are formed on the insulating film through contact holes.

여기서, 반도체 소자가 점점 집적화될수록 반도체 소자의 면적이 줄어들기 때문에 배선을 무한정 길게 형성하는 데는 한계가 있다. 따라서, 이를 해결하기 위해서는 배선 층간에 절연막을 형성하고 절연막에 뚫린 접촉 구멍(via)을 통해 배선을 서로 연결하는 다층 배선을 형성하는 것이 효과적이다.Here, there is a limit to forming the wiring indefinitely because the area of the semiconductor device is reduced as the semiconductor device is increasingly integrated. Therefore, in order to solve this problem, it is effective to form an insulating film between the wiring layers and to form a multilayer wiring connecting the wirings to each other through contact holes (vias) formed in the insulating film.

그러면, 종래의 다층 배선 구조를 갖는 반도체 소자에 대하여 도 1을 참조하여 설명한다.Next, a semiconductor device having a conventional multilayer wiring structure will be described with reference to FIG.

도 1에서와 같이 절연막(1) 위에 금속 따위로 이루어진 배선(2)이 형성되어 있다. 배선(2)은 TEOS 산화막과 같은 절연막(3)으로 덮여 있고, TEOS 산화막(3)에는 배선(2)을 드러내는 접촉 구멍(4)이 형성되어 있다. 접촉 구멍(4)의 벽에는 티타늄막(5)과 질화 티타늄막(6)의 이중막으로 이루어진 배리어막이 형성되어 있고, 접촉 구멍(4)은 텅스텐막(7)으로 채워져 있다. 이때, 절연막(3) 위의 배리어막(5, 6) 상부에는 텅스텐막(7)이 완전히 제거되어야 하므로 텅스텐막(7)을 과도 식각(overetch)하여 텅스텐막(7)이 접촉 구멍(4) 상부까지 채워지지 않을 수 있다. 이러한 경우 텅스텐막(7) 위에 알루미늄막(8)과 같은 배선이 형성될 때 접촉 구멍(4) 상부의 알루미늄막(8)이 움푹 들어가게 되어 알루미늄막(8)이 균일하게 형성되지 못하고 알루미늄막(8) 내에 공백이 형성될 수도 있다.As shown in FIG. 1, a wiring 2 made of metal is formed on the insulating film 1. The wiring 2 is covered with an insulating film 3 such as a TEOS oxide film, and the contact hole 4 exposing the wiring 2 is formed in the TEOS oxide film 3. A barrier film made of a double film of a titanium film 5 and a titanium nitride film 6 is formed on the wall of the contact hole 4, and the contact hole 4 is filled with a tungsten film 7. At this time, since the tungsten film 7 must be completely removed on the barrier films 5 and 6 on the insulating film 3, the tungsten film 7 is overetched so that the tungsten film 7 contacts the contact hole 4. It may not be filled to the top. In this case, when a wire such as the aluminum film 8 is formed on the tungsten film 7, the aluminum film 8 on the contact hole 4 is recessed, so that the aluminum film 8 is not uniformly formed and the aluminum film ( A blank may be formed in 8).

본 발명이 이루고자 하는 기술적 과제는 배선을 연결하는 접촉 구멍 내의 금속막을 평탄하게 형성하는 것이다.The technical problem to be achieved by the present invention is to flatten the metal film in the contact hole for connecting the wiring.

도 1은 종래의 기술에 따른 반도체 소자를 도시한 단면도이고,1 is a cross-sectional view showing a semiconductor device according to the prior art,

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention in accordance with a process sequence thereof.

이러한 과제를 달성하기 위하여 본 발명에서는 텅스텐막 위에 산화막을 접촉 구멍의 크기보다 넓은 범위로 남도록 한 후 산화막과 텅스텐막을 함께 식각한다.In order to achieve this problem, in the present invention, the oxide film and the tungsten film are etched together after leaving the oxide film on the tungsten film in a wider range than the size of the contact hole.

본 발명에 따른 반도체 소자를 제조할 때, 먼저 배선을 형성하고 배선을 덮는 절연막을 형성한다. 이어, 절연막을 식각하여 배선을 드러내는 접촉 구멍을 형성한다. 이어, 접촉 구멍의 벽에 배리어막을 형성하고 접촉 구멍을 텅스텐막으로 채운다. 이어, 접촉 구멍 위의 텅스텐막 위에 산화막을 증착하고, 산화막을 경사지게 패터닝하여 접촉 구멍 위의 부분만 남긴다. 이어, 산화막과 텅스텐막을 함께 식각하여 평탄화한다.In manufacturing the semiconductor device according to the present invention, first, a wiring is formed and an insulating film covering the wiring is formed. Subsequently, the insulating film is etched to form contact holes that expose the wiring. Then, a barrier film is formed on the wall of the contact hole and the contact hole is filled with a tungsten film. Then, an oxide film is deposited on the tungsten film on the contact hole, and the oxide film is patterned obliquely, leaving only the portion above the contact hole. Next, the oxide film and the tungsten film are etched together and planarized.

여기서, 산화막의 패터닝은 CF4기체를 이용한 비등방 식각을 이용하는 것이 바람직하다.Here, it is preferable to use anisotropic etching using CF 4 gas for patterning the oxide film.

이러한 본 발명의 제조 방법에서는 감광막 패턴이 오정렬되더라도 산화막을 비등방 식각하여 접촉 구멍의 크기보다 더 넓은 범위로 남게 하고, 산화막의 식각이 더 빠른 식각 선택비로 산화막과 텅스텐막을 함께 식각하여 텅스텐막을 평탄화할 수 있다.In the manufacturing method of the present invention, even if the photoresist pattern is misaligned, the oxide film is anisotropically etched to remain in a wider range than the size of the contact hole, and the oxide film and the tungsten film are etched together at a faster etching selectivity, so that the tungsten film can be flattened. have.

그러면, 첨부한 도면을 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도로 상세히 설명한다.Next, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same.

도 2a 내지 도 2f를 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조 방법에 대하여 상세히 설명한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2F.

먼저, 도 2a에서와 같이 절연막(11) 위에 알루미늄과 같은 금속 따위로 이루어진 배선(12)을 형성하고 배선(12) 위에 TEOS 산화막과 같은 절연막(13)을 화학 기상 증착법 따위로 증착한다. 이어, TEOS 산화막(13)을 식각하여 배선(12)을 드러내는 접촉 구멍(14)을 형성한다.First, as shown in FIG. 2A, a wiring 12 made of a metal such as aluminum is formed on the insulating film 11, and an insulating film 13, such as a TEOS oxide film, is deposited on the wiring 12 by chemical vapor deposition. Subsequently, the TEOS oxide film 13 is etched to form a contact hole 14 exposing the wiring 12.

이어, 도 2b에서와 같이 접촉 구멍(14)의 벽에 티타늄막(15)과 질화 티타늄막(16)의 이중막으로 이루어진 배리어막을 차례로 증착한 후 텅스텐막(17)을 화학 기상 증착법 따위로 증착하여 접촉 구멍(14)을 채운다. 텅스텐막(17) 위에는 산화막(18)을 증착한다.Subsequently, as shown in FIG. 2B, a barrier film made of a double film of a titanium film 15 and a titanium nitride film 16 is sequentially deposited on the wall of the contact hole 14, and then the tungsten film 17 is deposited by chemical vapor deposition. The contact hole 14 is filled. An oxide film 18 is deposited on the tungsten film 17.

이어, 도 2c에서와 같이 산화막(18) 위에 감광막 패턴(19)을 형성한다. 이때, 감광막 패턴(19)은 접촉 구멍(14)과 동일한 패턴으로 형성하는데 오정렬로 인해 접촉 구멍(14)의 크기(l)에서 벗어날 수도 있다.Subsequently, a photosensitive film pattern 19 is formed on the oxide film 18 as shown in FIG. 2C. At this time, the photoresist pattern 19 is formed in the same pattern as the contact hole 14, but may be out of the size l of the contact hole 14 due to misalignment.

이어, 도 2d에서와 같이 감광막 패턴(19)을 마스크로 하여 산화막(18)을 식각하여 접촉 구멍(14) 위의 텅스텐막(17) 위에 산화막(18)을 남긴다. 이때, 산화막(18)은 수직하게 식각하지 않고 CF4따위의 기체를 이용하여 경사지게 식각하는 비등방 식각을 한다. 이러한 식각을 통해 접촉 구멍(14)에서 벗어나는 부분(l1)을 포함하면서 산화막(18)이 접촉 구멍(14)의 크기보다 더 넓은 범위로 남게 된다.Next, as illustrated in FIG. 2D, the oxide film 18 is etched using the photosensitive film pattern 19 as a mask to leave the oxide film 18 on the tungsten film 17 on the contact hole 14. In this case, the oxide film 18 is anisotropically etched obliquely using a gas such as CF 4 instead of vertically etched. This etching leaves the oxide film 18 in a wider range than the size of the contact hole 14 while including the portion l 1 deviating from the contact hole 14.

이어, 도 2e에서와 같이 감광막 패턴(19)을 제거한 후, 도 2f에서와 같이 산화막(18)과 텅스텐막(17)을 함께 식각한다. 이때, 산화막(18)의 식각이 텅스텐막(17)의 식각보다 더 빠른 식각 선택비로 식각하여 텅스텐막(17)이 배리어막(16)과 동일한 높이가 될 때까지 평탄화한다. 이때, TEOS 산화막(13) 위의 배리어막(16)도 약간 식각될 수 있다.Subsequently, after removing the photosensitive film pattern 19 as shown in FIG. 2E, the oxide film 18 and the tungsten film 17 are etched together as shown in FIG. 2F. At this time, the etching of the oxide film 18 is etched at an etching selectivity faster than the etching of the tungsten film 17, and the planarization is performed until the tungsten film 17 becomes the same height as the barrier film 16. In this case, the barrier layer 16 on the TEOS oxide layer 13 may also be slightly etched.

이와 같이, 감광막 패턴(19)의 오정렬을 고려하여 산화막(18)을 경사지게 식각하여 접촉 구멍(14)의 크기보다 넓은 범위로 산화막(18)이 남도록 하고,산화막(18)의 식각이 텅스텐막(17)의 식각보다 더 빠른 식각 선택비를 사용하여 텅스텐막(17)과 산화막(18)을 함께 식각하여 텅스텐막(17)을 평탄화할 수 있다.As described above, the oxide film 18 is inclined etched in consideration of misalignment of the photosensitive film pattern 19 so that the oxide film 18 remains in a wider range than the size of the contact hole 14, and the etching of the oxide film 18 is performed by a tungsten film ( The tungsten film 17 may be planarized by etching the tungsten film 17 and the oxide film 18 together using an etching selectivity faster than the etching of 17.

이와 같이 본 발명에서는 접촉 구멍 내의 금속막을 평탄하게 형성하여 그 위의 배선 또한 평탄하게 형성할 수 있다.As described above, in the present invention, the metal film in the contact hole can be formed flat, and the wiring thereon can also be formed flat.

Claims (3)

배선을 형성하는 단계,Forming wiring, 상기 배선을 덮는 절연막을 형성하는 단계,Forming an insulating film covering the wiring; 상기 절연막을 식각하여 상기 배선을 드러내는 접촉 구멍을 형성하는 단계,Etching the insulating film to form a contact hole exposing the wiring; 상기 접촉 구멍의 벽에 배리어막을 형성하는 단계,Forming a barrier film on the wall of the contact hole; 상기 접촉 구멍을 텅스텐막으로 채우는 단계,Filling the contact hole with a tungsten film, 산화막을 증착하는 단계,Depositing an oxide film, 상기 산화막을 경사지게 패터닝하여 상기 접촉 구멍 위의 부분만 남기는 단계,Patterning the oxide film obliquely, leaving only a portion above the contact hole; 상기 산화막과 상기 텅스텐막을 함께 식각하여 평탄화하는 단계Etching and planarizing the oxide film and the tungsten film together 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에서,In claim 1, 상기 산화막의 패터닝은 비등방 식각을 이용하는 반도체 소자의 제조 방법.The patterning of the oxide film is a method of manufacturing a semiconductor device using anisotropic etching. 제2항에서,In claim 2, 상기 산화막의 패터닝은 CF4기체를 이용하는 반도체 소자의 제조 방법.The patterning of the oxide film is a method of manufacturing a semiconductor device using a CF 4 gas.
KR1019990067720A 1999-12-31 1999-12-31 a manufacturing method of a semiconductor device KR100315457B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990067720A KR100315457B1 (en) 1999-12-31 1999-12-31 a manufacturing method of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990067720A KR100315457B1 (en) 1999-12-31 1999-12-31 a manufacturing method of a semiconductor device

Publications (2)

Publication Number Publication Date
KR20010066136A KR20010066136A (en) 2001-07-11
KR100315457B1 true KR100315457B1 (en) 2001-11-28

Family

ID=19634820

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990067720A KR100315457B1 (en) 1999-12-31 1999-12-31 a manufacturing method of a semiconductor device

Country Status (1)

Country Link
KR (1) KR100315457B1 (en)

Also Published As

Publication number Publication date
KR20010066136A (en) 2001-07-11

Similar Documents

Publication Publication Date Title
US7932173B2 (en) Method of fabricating integrated circuitry
KR100215847B1 (en) Metal interconnector of semiconductor device and process for forming the same
US6008114A (en) Method of forming dual damascene structure
KR100277377B1 (en) Formation method of contact/through hole
KR100333382B1 (en) Method for forming multi-level metal interconnection of semiconductor device
JPH07122638A (en) Fabrication of semiconductor device
US20090286396A1 (en) Method for manufacturing a semiconductor device having a stepped through-hole
US20060160356A1 (en) Method for fabricating self-aligned contact hole
KR100303366B1 (en) method of forming interconnection line for semicodudctor device
US6933229B2 (en) Method of manufacturing semiconductor device featuring formation of conductive plugs
KR100315457B1 (en) a manufacturing method of a semiconductor device
KR100432885B1 (en) Method Of Forming Interlayer Dielectric Pattern
KR100193889B1 (en) Via hole formation method of semiconductor device
KR100439477B1 (en) Fabricating method of Tungsten plug in semiconductor device
KR100235960B1 (en) Method of forming conducting line in semiconductor device
KR19990033624A (en) Contact Forming Method of Semiconductor Device
US20040238482A1 (en) Method for fabricating semiconductor device
KR100338605B1 (en) Method for forming contact hole of semiconductor
KR100349346B1 (en) Method of defining a wire pattern in a semiconductor device
KR100203298B1 (en) Interconnecting method of semiconductor device
KR19990060819A (en) Metal wiring formation method of semiconductor device
KR100304967B1 (en) Metal line of semiconductor device and method for fabricating the same
KR100249130B1 (en) Method for forming metal line of semiconductor device
KR100313537B1 (en) Capacitor forming method
JPH09266252A (en) Semiconductor device manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111020

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20121026

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee