JPH07122638A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To make a highly accurate contact hole without causing any damage on the underlying substrate. CONSTITUTION:The method for fabricating a semiconductor device comprises a step for forming a columnar resist pattern at a part for making a contact hole 5 on a conductive pattern 2 formed on a substrate 1, a step for exposing the upper end part of the resist pattern 3 onto the substrate 1 where the resist pattern 3 is formed and forming a planarized insulation film 4, and a step for removing the resist pattern 3 to make a contact hole 5 partially exposing the conductive pattern 2 through the insulation film 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to a method for forming an insulating film having a contact hole.

In recent years, with the high integration of semiconductor devices, the types of conductive films used for securing low resistance of electrodes and wirings have been diversified, and insulation for forming contact holes with these conductive films has been diversified. It is becoming difficult to obtain a sufficient etching selection ratio with respect to the film.

Further, since the wiring width has been reduced extremely, it is easy to cause the positional deviation between the conductive film pattern forming the wiring and the contact hole. for that reason,
In the contact hole formation process, the contact resistance of the wiring is increased due to damage to the base under the contact hole, and there is a short circuit between the wiring and the substrate. Contact hole forming technology is desired.

[0004]

2. Description of the Related Art FIGS. 4 and 5 are schematic process sectional views showing a conventional example of a method of forming an insulating film and a contact hole in manufacturing a MOS type semiconductor device, and FIGS. 6 and 7 show respective problems. It is a schematic cross section.

Referring to FIG. 4 (a), in the first example of forming a contact hole in an insulating film which is directly in contact with a conventional MOSFET, a field oxide film 12 of a silicon (Si) substrate 11 is formed by a well-known MOS process. A gate electrode 15 having a tungsten polycide structure is formed on the separated element region 13 via a gate oxide film 14, for example, a tungsten silicide (WSi) layer 15b is laminated on a poly Si layer 15a, and this gate is formed. Using the electrode 15 as a mask, a low impurity concentration source region 16S and a drain region 16D are formed by ion implantation, and a silicon oxide (SiO ₂ ) side wall 17 is formed on the side surface of the gate electrode 15 by a known method. Using the gate electrode 15 having the wall 17 as a mask, a source region 18S and a drain region 18D having a high impurity concentration are formed by ion implantation means,
Next, a thin titanium (Ti) film with a thickness of several hundred Å is formed on the entire surface of the substrate, and heat treatment is applied to silicify the WSi layer 15b and the Ti film in the portion in direct contact with the surface of the Si substrate 11, and then to silicide. By selectively removing the Ti film on the insulating film such as the SiO ₂ side wall 17 not covered with the wet etching method using an aqueous solution of ammonium peroxide, the WSi layer 13 is formed.
b and Titanium silicide that contributes to the reduction of contact resistance on the Si substrate 11 and also functions as an etching barrier
A (TiSi) film 19 is formed.

Next, referring to FIG. 4 (b), a CVD-SiO ₂ film 20 for surface protection is formed on the substrate, and then a spin-on-glass (SOG) layer serving as an insulating film having a flat surface is formed on the substrate. 21 is formed by coating, and then heat treatment is performed to sinter and cure the SOG layer 21 to form an insulating film.

Next, referring to FIG. 4 (c), a resist film 22 is formed by coating on the SOG layer 21.
After exposure and development, the resist film 22 is provided with a contact hole and drain region 18 for the gate electrode 15, for example.
Openings 23G and 23D for forming contact holes for D
To form.

Next, referring to FIG. 4 (d), using the resist film 22 as a mask, the openings 23G and
The SOG layer 21 and its lower part are etched through 23D through anisotropic dry etching such as reactive ion etching (RIE) using a fluorine-based gas such as (CF ₄ + CHF ₃ ) gas as an etching gas. CVD-SiO ₂
A method of forming a gate contact hole 24G and a drain contact hole 24D penetrating the films at once in the film 20 has been used. The figure shows the state after the resist film 22 is removed.

However, in the above-mentioned conventional method for forming the MOSFET, there have been problems as shown in FIGS. 6 (a) and 6 (b). That is, the first problem is that in the etching with the fluorine-based gas at the time of forming the contact hole, the insulating film such as the SOG layer 21 and the CVD-SiO ₂ film 20 and the TiSi film 19 or
Since the etching selectivity with respect to the silicide film such as the WSi layer 15b is not sufficiently large, when over-etching is performed to compensate for the variation in the etching amount within the substrate surface, as shown in FIG. 6 (a), In particular, in the contact hole 24G portion on the gate electrode 15, the TiSi film 19 exposed at the bottom of the contact hole 24G is removed by etching, and the WSi film 15b thereunder is also etched.
That is, the film 15b becomes extremely thin, and the contact resistance between the gate electrode 15 connected via the contact hole 24G and the wiring is significantly increased.

A second problem is that, as shown in FIG. 6B, when the contact hole 24G is misaligned, the gate electrode exposed at the bottom of the contact hole 24G by etching for forming the contact hole. The insulating film such as the SiO ₂ sidewall 17 on the 15 side surface is also etched, and the Si substrate 11
Since the surface is exposed, the gate electrode 15 and the source regions 16S, 18S are formed by the wiring formed on the contact hole 24G.
(Alternatively, a short circuit with the drain regions 16D and 18D) occurs.

See FIG. 5A. Further, when forming an interlayer insulating film and a contact hole in the conventional process of forming a multilayer wiring, for example, a first interlayer insulating film 25 made of PSG or the like covering a semiconductor substrate is formed. For example, after forming a lower layer wiring 26 of a three-layer structure in which a Ti film 26a, a titanium nitride (TiN) film 26b, and a tungsten (W) film 26c are sequentially stacked, a surface protection layer is formed on the lower layer wiring 26. CVD-SiO ₂ film 27 is formed.

Next, as shown in FIG. 5B, a SOG layer 28, which will be a second interlayer insulating film for planarization, is applied on the surface covered with the CVD-SiO ₂ film 27 to a thickness such that the surface becomes flat. After being formed, heat treatment is performed to cure the SOG layer 28 to form an insulating film.

Next, a resist film 29 is formed on the SOG layer 28 and exposed and developed to form an opening 30 for forming a contact hole in the resist film 29, as shown in FIG. 5C.

As shown in FIG. 5D, similarly to the first conventional example, the resist film 29 is used as a mask and a fluorine-based gas such as (CF ₄
An anisotropic dry etching method using + CHF ₃ ) gas as an etching gas, such as reactive ion etching
A method has been used in which the inter-wiring contact hole 31 is formed through the SOG layer 28 and the CVD-SiO ₂ film 27 under the same by performing etching by (RIE) processing.
The figure shows the state after the resist film 29 is removed.

However, also in the second example, the following problems occur as in the first example. That is, the first problem is
In the etching using the fluorine-based gas for forming the contact hole, the over-etching is performed because the selection ratio between the insulating film such as the SOG layer 28 and the CVD-SiO ₂ film 27 and the uppermost W film 26c of the lower wiring 26 is low. As a result, as shown in FIG. 7A, the uppermost W film 26c of the lower layer wiring 26 is thinly etched, and the contact resistance of the interlayer connection of the wiring via the contact hole 31 increases.

The second problem is that, as shown in FIG. 7B, when the wiring contact hole 31 is misaligned,
The CVD of the side surface of the lower layer wiring 26 exposed at the bottom of the contact hole 31 by the etching for forming the wiring contact hole
The SiO ₂ film 27 and the first interlayer insulating film 25 thereunder are removed by etching to remove the conductive layer (not shown) below the first interlayer insulating film 25 and the upper layer formed on the contact hole 31. A short circuit occurs with the wiring (not shown).

[0017]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a contact hole forming method capable of forming a highly accurate contact hole without damaging the substrate under the contact hole.

[0018]

To solve the above-mentioned problems, an insulating film having a contact hole which covers the substrate and exposes a part of the conductive pattern is formed on a substrate having a conductive pattern. At that time, a step of forming a columnar resist pattern at a place where a contact hole is formed on the conductive pattern formed on the substrate, and exposing the upper end portion of the resist pattern on the substrate on which the resist pattern is formed And a step of forming an insulating film having a flattened surface, and removing the resist pattern to form a contact hole in the insulating film, the contact hole being composed of a removed portion of the resist pattern and exposing a part of the conductive pattern. A method for manufacturing a semiconductor device according to the present invention, which comprises a step, or a step of forming an insulating film for surface protection on a substrate having a conductive pattern; Forming a hole in the protective insulating film to expose at least a region including a contact hole disposition region on the conductive pattern; and forming a columnar resist pattern on the conductive pattern exposed in the aperture. A step of forming, an step of forming an insulating film having a flattened surface and exposing the upper end portion of the resist pattern on the substrate on which the resist pattern is formed, and removing the resist pattern to form an insulating film And a step of forming a contact hole which is composed of the removed portion of the resist pattern and exposes a part of the conductive pattern.

[0019]

1 (a) and 1 (b) are sectional views for explaining the principle of the present invention. In the method of the present invention, as shown in FIG. 1 (a), a columnar shape having a size and shape corresponding to the contact hole is provided above the position on the substrate 1 where the contact hole of the conductive pattern 2 is provided. After the resist pattern 3 is formed, as shown in FIG.
On top of this, for example, an SOG layer to be the insulating film 4 is formed by coating so that the resist pattern 3 is buried.
As shown in FIG. 1 (c), an insulating film 4 is formed by exposing the upper end of the resist pattern 3 and flattening the surface by a method such as etching back the G layer. The resist pattern 3 is selectively removed by a predominant etching means, and as shown in FIG. 1 (d), the area of the insulating film 4 where the resist pattern 3 is removed has the same size and shape as the resist pattern 3 and is electrically conductive. By forming the contact hole 5 exposing a part of the pattern 2, the flat insulating film 4 having the contact hole 5 exposing a part of the conductive pattern 2 on the substrate 1 having the conductive pattern 2. To form.

As is well known, the resist is oxygen (O ₂ ) or O ₂
It is extremely easily ashed by a dry etching means using a gas containing as a main component. However, inorganic insulating films such as SOG and SiO ₂ , semiconductor materials such as Si, and metallic materials such as TiSi, WSi, and W must be etched by dry etching means using O ₂ or a gas containing O ₂ as a main component. Is almost none. Therefore, as described above, the columnar resist pattern 3
According to the method of the present invention for removing the ashing to form the contact hole 5, even if the etching selectivity between the lower conductive pattern and the insulating film on which the upper contact hole is formed is low, The conductive pattern below the contact hole 5 (pattern made of the metal material or the like) is not damaged at the time of formation. Further, even when the formation position of the contact hole deviates from above the conductive pattern, the insulating film around the conductive pattern is not deeply etched.

Therefore, according to the method of the present invention, the contact resistance between the wiring formed on the contact hole and the conductive pattern under the contact hole is prevented from increasing, and the conductive pattern is formed on the contact hole portion. It is possible to prevent a short circuit between the conductive base below the insulating film in the periphery thereof and the conductive base via the wiring formed on the contact hole. Furthermore, since the insulating film 4 around the resist pattern 3 is not etched when the resist pattern is removed, a highly accurate contact hole 5 self-aligned with the resist pattern 3 is formed.

When forming an insulating film on a conductive pattern covered with an insulating film for surface protection and forming a contact hole for exposing the conductive pattern in the insulating film, a contact hole is provided. After opening the surface protection film in a region to be made larger than the size of the contact hole by using an etching means such as wet etching so as not to damage the conductive pattern as much as possible, according to the above process, An insulating film having a contact hole is formed in. In this way, the conductive pattern and the insulating film around it are hardly damaged when the surface protection insulating film is removed, and the same effect as in the case without the surface protection insulating film is obtained.

[0023]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. FIG. 2 is a process sectional view of one embodiment of the method of the present invention,
FIG. 3 is a process sectional view of another embodiment of the method of the present invention.

Referring to FIG. 2 (a), when forming a MOSFET using the method of the present invention, the thickness is formed on the element region 13 separated by the field oxide film 12 of the Si substrate 11 by the MOS process similar to the conventional one. For example, through the gate oxide film 14 of about 80 Å, for example, a thickness of 500
Approximately 1500 Å WSi layer 15b on poly-Si layer 15a of about Å
A gate electrode 15 of a tungsten polycide structure is formed by stacking the layers, and using the gate electrode 15 as a mask, a low impurity concentration source region 16S and a drain region 16D are formed by ion implantation, and the gate electrode is formed by a well-known method.
A SiO ₂ sidewall 17 is formed on the side surface of 15, and a source region 18S and a drain region 18D having a high impurity concentration are formed by ion implantation means using the gate electrode 15 having the sidewall 17 as a mask to complete the MOSFET. A thin Ti film with a thickness of about 300 Å is formed on the entire surface of the substrate, and heat treatment is applied to silicify the Ti film of the WSi layer 15b and the portion of the Si substrate 11 that is in direct contact, and then the non-silicided SiO ₂ By selectively removing the Ti film on the insulating film such as the sidewall 17 by a wet etching method using an aqueous solution of ammonium peroxide, the WSi layer 13b and the Si substrate 1 can be formed.
A TiSi film 19 having a thickness of about 400 Å that contributes to the reduction of contact resistance and also functions as an etching barrier is formed on 1.

Next, referring to FIG. 2 (b), a thickness of 6000 ~ is formed on the substrate by spin coating.
A resist film of about 7,000 Å (for example, a novolac-based bodi resist) is applied and exposed and developed to form a contact hole. For example, on the gate electrode 15 and the drain region 18D (more specifically, on the TiSi film 19 at each place). Then, columnar resist patterns R _G and R _D having a sectional shape corresponding to the contact hole to be formed are formed.

Next, referring to FIG. 2C, an SOG layer having a thickness of, for example, about 1 μm is formed on the surface on which the above-mentioned columnar resist patterns R _G and R _D are formed so that these resist patterns are buried and the surface becomes substantially flat. 21 is formed by spin coating.

Next, referring to FIG. 2D, the SOG layer 21 is dried under predetermined step drying conditions (for example, 150 ° C.-220 ° C.-270 ° C.), and then the SOG layer 21 is patterned into resist patterns R _G and R _D. Etching back is performed by using a reactive ion etching (RIE) method until the upper end portion of the is exposed and has a predetermined thickness of, for example, about 5000 Å.

The conditions of the above-mentioned etch back are, for example, as follows. Etching gas CF ₄ / CHF ₃ = 100/60 N ₂ sccm Pressure 20 mTorr RF power 350 W See Fig. 2 (e) Next, for example, downflow method using ashing gas in which CF ₄ for maintaining activity is added to O ₂ By selectively removing the resist patterns R _G and R _D, etc.
The removed resist patterns R _G and R _D are formed on the SOG layer 21.
Contact holes C _G for the gate electrode 15 and a contact hole C for the drain region 18D, which are self-aligned with each other.
Form _D etc.

The ashing conditions are as follows, for example. Ashing gas O ₂ / CF ₄ = 744/153 sccm Pressure 0.9 Torr μ Wave power 800 W Next, the SOG layer 21 is cured at a temperature of, for example, about 450 ° C. to form an insulating film, which is cured on the MOSFET.
Consists of SOG layer 21, for example the gate electrode of the MOSFET
An insulating film having contact holes C _G and C _D is formed on 15 and the drain region 18D.

Since the ashing removal of the resist patterns R _G , R _D, etc. when forming the contact holes C _G , C _D etc. is performed using the gas containing O ₂ as a main component as described above, The TiSi film 19 exposed on the bottom of the contact holes C _G , C _D, etc. and the SOG layer 21 on the side have sufficient etching resistance and are not damaged by etching. Therefore, the TiSi film 19 remains in a perfect state on the bottom surfaces of the contact holes C _G , C _{D and the} like to ensure a good contact resistance, and the dimensional accuracy of the contact holes C _G , C _D, etc. is also good. To be kept.

Further, even when the contact hole C _G is displaced, SiO ₂ which appears at the bottom of the contact hole C _G.
The insulating film such as the sidewalls 17 is not damaged by the removal process of the resist pattern R _G , and a short circuit failure between the gate and the source or the gate and the drain through the wiring material deposited on the contact hole C _G. Is also prevented.

After that, although not shown, wiring of aluminum alloy or the like derived from the contact holes C _G , C _D, etc. is formed on the insulating film made of the SOG layer 21 to form the insulating film and the contact hole according to the present invention. The formed MOSFET is completed.

Next, another embodiment in which the present invention is applied to the formation of multilayer wiring will be described with reference to FIG. Refer to FIG. 3 (a). When forming an interlayer insulating film having a contact hole by using the method of the present invention, the first interlayer insulating film is formed on the Si substrate 11 on which semiconductor elements (not shown) and the like are formed as in the conventional case.
25 is formed on the first interlayer insulating film 25, which is derived from a semiconductor element (not shown) and has a thickness of 200 Å from the lower layer.
Ti film 26a, 500 Å TiN film 26b, 1500 Å W film 26c
A lower wiring pattern 26 having a layered structure is formed, and the surface for forming the wiring pattern 26 has a thickness of 2000 for surface protection.
The wiring pattern is first formed by photolithography using a substrate covered with a CVD-SiO ₂ film 27 having a thickness of about Å, and a wet etching means using a hydrofluoric acid-based solution as an etching means.
CVD-Si on the area where 26 contact holes are to be formed
An opening H larger than the contact hole is formed in the O ₂ film 27. Since the uppermost W film 26c of the wiring pattern 26 has sufficient resistance to a hydrofluoric acid-based solution, the wiring pattern 26 is not damaged when the opening H is formed.

Next, referring to FIG. 3B, a positive resist film of, for example, a novolac system having a thickness of about 6000 to 7,000 Å is applied on the substrate on which the CVD-SiO ₂ film 27 having the opening H is formed by spin coating. Corresponding to the contact hole which is to be formed and exposed and developed to be formed on the wiring pattern 26 exposed in the opening H of the CVD-SiO ₂ film 27 (more specifically, on the W film 26c which is the uppermost layer of the wiring pattern). A column-shaped positive resist pattern _RL having a size and shape is formed.

Next, referring to FIG. 3C, on the surface on which the columnar resist pattern R _L is formed,
An SOG layer 28 is formed by a spin coating method so that the resist pattern is buried and the surface becomes substantially flat, for example, to a thickness of about 1 μm.

Next, as shown in FIG. 3D, after the SOG layer 28 is dried in the same manner as in the above embodiment,
The SOG layer 28 is etched back using the reactive ion etching (RIE) method similar to the above embodiment until the upper end of the resist pattern R _L is exposed and has a predetermined thickness of, for example, about 5000 Å.

Next, as shown in FIG. 3E, the resist pattern R _L is selectively removed by a down-flow ashing process under the above conditions using an ashing gas containing O ₂ gas as a main component as in the above embodiment. In the SOG layer 28, contact holes _CL are formed between the wirings that are self-aligned with the resist pattern _RL . Here, the ashing conditions were the same as those in the above-mentioned embodiment.

Next, for example, at a temperature of about 450 ° C., the SOG layer 28
Is cured to form an insulating film, and the lower wiring pattern 26
On the forming surface, made of SOG layer 28 which is cured, the having a contact hole C _L for the upper layer wiring (not shown) in the lower layer wiring pattern in the opening H of the CVD-SiO ₂ film 27 on 26 2 Is formed.

Thereafter, although not shown, an upper layer wiring made of, for example, an Al alloy, which is led out from the W film 26c of the lower layer wiring pattern 26 to the second interlayer insulating film through the contact hole C _L, is formed. Then, the multilayer wiring structure according to the present invention is formed.

Since the ashing removal of the resist pattern R _{L at} the time of forming the contact hole C _L is performed by using a gas containing O ₂ as a main component as in the above embodiment, the bottom surface of the contact hole C _L is removed. Exposed W film 26c
Also, the SOG layer 28 on the side surface has sufficient etching resistance and is not damaged by etching. Therefore, a good connection between wirings having a low contact resistance can be obtained, and a highly accurate contact hole that is faithfully matched to the size and shape of the resist pattern R _L is formed.

Even when the contact hole C _L is misaligned, the insulating films 27 and 25 exposed at the bottom of the contact hole C _L are not etched and damaged when the contact hole C _{L is} formed. the upper layer of the wiring material is deposited C _L shape, the lower layer wiring pattern 26
It is also possible to prevent short-circuiting between the conductive layer and the conductive layer disposed thereunder.

Although the resist pattern on the pillar is formed of the positive resist in the above embodiment, the resist pattern may be formed of the negative resist, as a matter of course. Then, this resist pattern is formed into a reverse taper shape by exposing the resist pattern using an excimer laser using a negative resist such as a mixture of cyclized isoprene rubber and bisazide to remove the resist pattern. Since the contact hole formed in the SOG layer is formed in a forward tapered shape, the step coverage of the upper layer wiring in this contact hole portion is improved, and the effect of preventing deterioration of the upper layer wiring is produced.

Further, by forming the resist pattern with a photosensitive polyimide having heat resistance, it becomes possible to cure the SOG layer before removing the columnar polyimide pattern and prevent the SOG layer from being deformed. The contact hole formation accuracy is further improved.

Furthermore, a conductive antireflection film made of, for example, amorphous carbon is provided on the surface of the conductive pattern below the contact hole formation portion of the SOG layer, that is, the gate electrode and the wiring pattern of the lower layer in the above embodiment. As a result, the reflected light from the upper surfaces of the electrodes and wirings is suppressed, so that the accuracy of forming the resist pattern, and thus the accuracy of forming the contact hole, is further improved.

Furthermore, in the above embodiment, the contour is
Kuto Hall C_G, C_D, C_LSOG layer on the insulating film having
21 or 28 is used, and this SOG layer 21 is contacted
Columnar resist pattern R corresponding to the hole_G, R_D,
R_LEtch back or
Expose the upper edge of the resist pattern by polishing.
The contact pattern by removing the resist pattern.
Le C_G, C_D, C_LAnd so on. However, the above SOG layer
21 is applied with a resist pattern R_G, R_D, R _LEtc.
Even if the end portion is formed to have a thickness that is exposed from the beginning, the same effect can be obtained.
Of course, if the result is obtained and the surface is flattened,
There is no.

The method for forming the insulating film is not limited to the coating and forming means for the SOG layer, and any method capable of forming a flat insulating film at a low temperature that does not deform the resist pattern may be used. A low temperature chemical vapor deposition method using water + tetraethyl orthosilicate] or the like as a growth gas may be used.

[0047]

As described above, according to the present invention, the etching selection ratio between the insulating film in which the contact hole is to be provided and the conductive film forming the conductive pattern such as the electrode or wiring under the contact hole is selected. Even when the size is small, an interlayer insulating film having a highly accurate contact hole can be formed on the conductive pattern without damaging the conductive pattern and the lower insulating film around the conductive pattern. It is possible to prevent an increase in resistance and a short circuit failure with the lower conductive layer in the contact hole portion.

Therefore, the present invention largely contributes to the improvement of the performance and the yield of the semiconductor device which is highly integrated and has a multilayer wiring.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining the principle of the present invention.

FIG. 2 is a process sectional view of an embodiment of the method of the present invention.

FIG. 3 is a process sectional view of another embodiment of the method of the present invention.

FIG. 4 is a process sectional view of a first example of a conventional method.

FIG. 5 is a process sectional view of a second example of a conventional method.

FIG. 6 is a schematic cross-sectional view showing a problem of the first example of the conventional method.

FIG. 7 is a schematic cross-sectional view showing a problem of the second example of the conventional method.

[Explanation of symbols]

1 Substrate 2 Conductive Pattern 3 Columnar Resist Pattern 4 Insulating Film 5 Contact Hole 11 Si Substrate 12 Field Oxide Film 13 Element Area 14 Gate Oxide Film 15 Gate Electrode 15a Poly Si Layer 15b WSi Layer 16S Low Impurity Concentration Source Area 16D Low Impurity Concentration drain region 17 SiO ₂ sidewall 18S High impurity concentration source region 18D High impurity concentration drain region 19 TiSi film 21, 28 SOG layer 25 First interlayer insulating film 26 Lower wiring pattern 26a Ti film 26b TiN film 26C W film 27 CVD -SiO ₂ film R _G, R _D, R _L columnar resist pattern C _G, C _D, C _L contact hole

Claims (6)

[Claims] 1. A substrate (1) having a conductive pattern,
When forming an insulating film having a contact hole (5) covering the base (1) and exposing a part of the conductive pattern (2), the conductive pattern formed on the base (1) (2) A step of forming a columnar resist pattern (3) at the place where the contact hole (5) is to be formed, and the resist pattern (3) on the substrate (1) on which the resist pattern (3) is formed. A step of forming an insulating film (4) whose upper end is exposed and the surface of which is flattened, and the insulating film by removing the resist pattern (3)
A contact hole (5) consisting of a removed part of the resist pattern (3) in (4) and exposing a part of the conductive pattern (2)
And a step of forming a semiconductor device. 2. When forming an insulating film on a substrate having a conductive pattern and having a contact hole covering the substrate and exposing a part of the conductive pattern, the substrate having the conductive pattern is formed. A step of forming an insulating film for surface protection on the surface, a step of forming an opening in the insulating film for surface protection that exposes at least an area including a contact hole disposition area on the conductive pattern, and the opening. A step of forming a columnar resist pattern on a conductive pattern exposed inside, and forming an insulating film on the substrate on which the resist pattern is formed, exposing the upper end portion of the resist pattern and planarizing the surface. And a step of removing the resist pattern to form a contact hole in the insulating film, the contact hole consisting of a removed portion of the resist pattern and exposing a part of the conductive pattern. The method of manufacturing a semiconductor device, characterized in that. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the opening is formed in the surface protection insulating film by wet etching with an aqueous solution containing fluorine. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the resist pattern has an inverse taper shape. 5. The resist according to claim 1, wherein the resist is made of photosensitive polyimide.
A method for manufacturing a semiconductor device as described above. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the upper surface of the conductive substrate is covered with an antireflection film having conductivity.