KR20020096533A - Method of Forming Gate Pattern - Google Patents

Abstract

PURPOSE: A gate pattern formation method is provided to prevent an etch damage of a semiconductor substrate and to easily form a gate pattern having a vertical sidewall. CONSTITUTION: A first and a second insulating layer having different etching selectivities are sequentially formed on a semiconductor substrate(100) having an isolation layer(110). A second insulating pattern(131) and a first insulating pattern(121) are sequentially formed to expose the semiconductor substrate(100) by patterning the second and first insulating layer. A gate oxide layer is formed on the exposed semiconductor substrate(100). A gate conductive pattern(200) is formed on the gate oxide layer. Then, the second insulating pattern(131) and the first insulating pattern(121) are removed. A silicon nitride layer is used as the first insulating layer, and a silicon oxide layer is used as the second insulating layer.

Description

Method of Forming Gate Pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate pattern.

For high integration of semiconductor devices, semiconductor fabrication techniques are in miniaturization trend to reduce the width of the gate pattern and the gap between the gate patterns. However, when the width of the gate pattern decreases, the resistance value of the word line increases, which is not preferable in consideration of power consumption and operating speed of the semiconductor device. In order to solve this problem, a method of canceling an increase in resistance value as the width of the gate pattern decreases by increasing the thickness of the gate pattern is used.

1 and 2 are cross-sectional views illustrating a method of forming a gate pattern according to the related art.

Referring to FIG. 1, the device isolation layer pattern 20 is formed on the semiconductor substrate 10. A gate oxide layer 30, a polycrystalline silicon layer 40, a silicide layer 50, and a capping insulation layer 60 are sequentially formed on the semiconductor substrate 10 including the device isolation layer pattern 20. A photoresist pattern 70 for forming a gate pattern is formed on the capping insulating layer 60.

Referring to FIG. 2, the capping insulating layer 60, the silicide layer 50, and the polycrystalline silicon layer 40 are sequentially patterned using the photoresist pattern 70 as an etching mask. As a result, a gate pattern 80 including the capping insulating layer pattern 61, the gate upper electrode 51, and the gate lower electrode 41 is formed.

The gate oxide layer 30 is used as an etch stop layer in the etching process for forming the gate pattern 80, thereby preventing the etching damage to the semiconductor substrate 10. However, as described above, the increase in the thickness of the gate pattern 80 due to the high integration of the semiconductor device makes it difficult for the gate oxide layer 30 to prevent etching damage to the semiconductor substrate 10. This is because, as the thickness of the film to be etched increases, the error limit of the etching process also increases, and the etching selectivity of the silicon oxide film is not large in the polysilicon etching process.

In addition, the sidewall profile of the gate pattern 80 is preferably vertical. However, when the material is formed of various material layers as described above, it is difficult to form a vertical sidewall profile in the etching process for forming the gate pattern 80.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming a gate pattern having a vertical sidewall profile while preventing etching damage to a semiconductor substrate.

1 and 2 are process cross-sectional views illustrating a gate pattern forming method according to the prior art.

3 to 8 are process cross-sectional views illustrating a gate pattern forming method according to a preferred embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a method of forming a gate pattern by forming an insulating film pattern on a semiconductor substrate, and subsequently forming a gate oxide film and a gate conductive film on the semiconductor substrate between the insulating film patterns. do. This method forms a first insulating film and a second insulating film that are sequentially stacked on a semiconductor substrate, and exposes the semiconductor substrate by patterning the second and first insulating films in sequence, thereby sequentially turning the second insulating film pattern and the first insulating film pattern. Forming a step. A gate oxide film is formed on the exposed semiconductor substrate, and a gate conductive film pattern is formed between the second insulating film patterns to cover the gate oxide film, and then the second insulating film pattern and the first insulating film pattern are sequentially removed. .

Preferably, the first insulating film is formed of one of a silicon nitride film and an oxynitride film, and the second insulating film is formed of a silicon oxide film. The gate oxide layer may be formed by a thermal oxidation process, and the first insulating layer pattern may be formed by an isotropic etching method.

The gate conductive layer pattern may be formed of a polysilicon layer and a silicide layer, which are sequentially stacked, and the method may include forming a polysilicon layer on the entire surface of the semiconductor substrate including the gate oxide layer. In this case, the polysilicon film fills a region between the second insulating film patterns. The polysilicon layer is etched entirely to form a polysilicon pattern having an upper surface lower than an upper surface of the second insulating layer pattern. A silicide layer is formed on the entire surface of the semiconductor substrate including the polysilicon pattern. Similarly, the silicide film fills a region between the second insulating film patterns. The silicide layer is entirely etched to form a silicide layer pattern interposed between the second insulating layer patterns to cover the polysilicon pattern.

The gate conductive layer pattern may be formed of a polysilicon layer or a metal material layer. The method may include forming a gate conductive layer over the entire semiconductor substrate including the gate oxide layer. The gate conductive layer fills a region between the second insulating layer patterns. Thereafter, the gate conductive layer is etched entirely to expose the upper portion of the second insulating layer pattern, thereby forming a gate conductive layer pattern interposed between the second insulating layer patterns.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

3 to 8 are cross-sectional views illustrating a method of forming a gate pattern according to an exemplary embodiment of the present invention.

Referring to FIG. 3, an isolation layer 110 is formed on the semiconductor substrate 100 using a conventional isolation technique. A first insulating film 120, a second insulating film 130, and a photoresist film are sequentially formed on the entire surface of the semiconductor substrate including the device isolation layer 110. The photoresist film is patterned to form a photoresist pattern 140.

The first insulating film 120 is preferably formed of a silicon nitride film or an oxynitride film. In addition, the second insulating film 130 is preferably formed of a silicon oxide film. In addition, the thicknesses of the first and second insulating layers 120 and 130 should be determined in consideration of the required width of the gate pattern and the resistance of the gate electrode.

Referring to FIG. 4, the second insulating layer 130 is etched by using the photoresist pattern 140 as an etching mask until the first insulating layer 120 is exposed. Form. The forming of the second insulating layer pattern 131 may be performed by using an etching recipe having an etching selectivity with respect to the first insulating layer 120. In this case, etching damage to the semiconductor substrate 100 under the first insulating layer 120, which may occur in the process of etching the second insulating layer 130, may be prevented. As described above, when the first insulating layer 120 is formed of silicon nitride and the second insulating layer 130 is formed of silicon oxide, the etching selectivity of the etching process may be further increased.

In addition, the etching process for forming the second insulating layer pattern 131 is preferably performed by an anisotropic etching method. Since the second insulating layer 130 is composed of a single layer of a silicon oxide film, the anisotropic etching process may form a vertical sidewall more easily than the prior art.

The exposed first insulating layer 120 is etched to form a first insulating layer pattern 121. Accordingly, the semiconductor substrate 100 is exposed between the first insulating layer patterns 121. The etching process for forming the first insulating layer pattern 121 may be performed by using a silicon nitride etching recipe having an etching selectivity with respect to the silicon oxide and silicon. In this case, etching damage may be prevented from occurring on the second insulating layer pattern 131, the device isolation layer 110, and the semiconductor substrate 100.

In addition, the etching process for forming the first insulating layer pattern 121 is preferably performed by an isotropic etching method. By the method of isotropic etching, the first insulating layer pattern 121 has a profile cut under the second insulating layer pattern 131. An etching process for forming the first insulating layer pattern 121 may be performed by an anisotropic etching method.

Referring to FIG. 5, a gate oxide layer 150 is formed on the semiconductor substrate 100 exposed between the first insulating layer patterns 121. In order to improve electrical characteristics of the semiconductor transistor, the gate oxide film 150 is preferably a thermal oxide film formed through a thermal process. Alternatively, the gate oxide film (not shown) may be formed of an oxide film deposited by a CVD method.

As described above, when the first insulating film pattern 121 is formed by an isotropic etching method, the first insulating film pattern 121 has a profile undercut under the second insulating film pattern 131. In this case, the gate oxide film 150 has a width wider than an interval between the second insulating film patterns 131 on the exposed semiconductor substrate. Since a gate conductive layer pattern is to be formed on the gate oxide layer 150, the first insulating layer pattern 121 is formed by the isotropic etching so that the gate oxide layer 150 has a wider width than the gate conductive layer pattern. The method is preferred.

Referring to FIG. 6, a gate conductive layer pattern 200 is formed between the second insulating layer patterns 131 to cover the gate oxide layer 150.

The gate conductive layer pattern 200 may be formed of various material layers. Preferably, the gate conductive layer pattern 200 includes a polysilicon layer and a silicide layer that are sequentially stacked. The silicide layer is preferably formed of one of tungsten silicide, cobalt silicide and titanium silicide.

The method of forming the gate conductive layer pattern 200 using the polysilicon layer and the silicide layer, which are sequentially stacked, includes forming a polysilicon layer on the entire surface of the semiconductor substrate on which the gate oxide layer 150 is formed. The polysilicon film is deposited by a CVD method and fills a region between the second insulating film patterns 131. The polycrystalline silicon layer is etched entirely to form a polysilicon pattern 160 having an upper surface lower than an upper surface of the second insulating layer pattern 131. A silicide layer is formed on the entire surface of the semiconductor substrate including the polysilicon pattern 160. The silicide layer fills a region between the second insulating layer pattern 131 on the polysilicon pattern 160. The silicide layer pattern 170 is interposed between the second insulation layer pattern 131 by exposing the upper surface of the second insulation layer pattern 131 by etching the entire surface of the silicide layer. The polysilicon pattern 160 and the silicide layer pattern 170 constitute a gate conductive layer pattern 200.

The front side etching of the polysilicon layer and the front side etching of the silicide layer are preferably performed by etching back or chemical mechanical polishing (CMP).

The gate conductive layer pattern 200 may be formed of a material layer having a single layer of a polysilicon layer or a metal layer. The formation method is the same as the method up to the formation of the polysilicon pattern 160 described with reference to FIG. 6. That is, in this method, after the gate conductive film is formed on the entire surface of the semiconductor substrate on which the gate oxide film 150 is formed, the gate conductive film is etched entirely, and the gate conductive film has a lower surface than the upper surface of the second insulating layer pattern 131. Forming a pattern 200.

When the gate conductive layer pattern 200 is formed of a metal material layer, the gate conductive layer pattern 200 may have a low height due to the low resistance of the metal. Nevertheless, one of the reasons for not using a metal material film, especially a copper film, in the semiconductor manufacturing process in the prior art is the difficulty of the dry etching process for the copper film. However, the method of the present invention can minimize the difficulty of the dry etching process as in the prior art in that there is an etching step for the copper film only in the CMP process.

Referring to FIG. 7, the second insulating layer pattern 131 and the first insulating layer pattern 121 are sequentially removed to leave the gate oxide layer 150 and the gate conductive layer pattern 200 that are sequentially stacked.

Removing the second insulating layer pattern 131 may be performed by using a silicon oxide layer etching recipe having an etching selectivity with respect to the silicon nitride layer. In addition, in order to prevent the gate oxide layer 150 from being damaged in the process of removing the second insulating layer pattern 131, the first insulating layer 120 may be formed thicker than the gate oxide layer 150. In this case, the first insulating layer 120 is connected to the gate conductive layer pattern 200 to prevent the gate oxide layer from being etched in the etching process of the second insulating layer pattern 131.

When the anisotropic etching method is used to remove the second insulating layer pattern 131, the gate conductive layer pattern 200 may be recessed even if an etching recipe having an etching selectivity is used. To prevent this, a capping insulating layer pattern may be further formed on the gate conductive layer pattern 200 before etching the second insulating layer pattern 131. An etching process for removing the second insulating layer pattern 131 may be performed by an isotropic etching method, in which case the capping insulating layer pattern is not necessary.

The removing of the first insulating layer pattern 121 may be performed by using a silicon nitride layer etching recipe having an etching selectivity with respect to silicon and a silicon oxide layer.

According to the present invention, a gate pattern is formed by forming an insulating film pattern, forming a gate oxide film and a gate conductive film pattern sequentially stacked on a semiconductor substrate between the insulating film patterns, and then removing the insulating film pattern. As a result, a gate pattern having vertical sidewalls can be easily formed, and the etching damage can be prevented from occurring in the semiconductor substrate during the formation thereof. In addition, it is possible to use a metal material film as the gate electrode, thereby manufacturing a semiconductor device with a faster operating speed.

Claims (10)

Forming a first insulating film and a second insulating film sequentially stacked on the semiconductor substrate; Patterning the second and first insulating films in sequence to expose the semiconductor substrate, thereby sequentially forming a second insulating film pattern and a first insulating film pattern; Forming a gate oxide film on the exposed semiconductor substrate; Forming a gate conductive layer pattern interposed between the second insulating layer patterns to cover the gate oxide layer; And And sequentially removing the second insulating film pattern and the first insulating film pattern. The method of claim 1, And the first insulating film is formed of one of a silicon nitride film and an oxynitride film. The method of claim 1, And the second insulating film is formed of a silicon oxide film. The method of claim 1, Forming the gate conductive layer pattern Filling a region between the second insulating layer patterns by forming a gate conductive layer on an entire surface of the semiconductor substrate including the gate oxide layer; And And etching the gate conductive layer on the entire surface to expose an upper portion of the second insulating layer pattern. The method of claim 1, And the gate conductive layer pattern is formed of a polysilicon layer. The method of claim 1, And the gate conductive layer pattern is formed of a metal material layer. The method of claim 1, And the gate conductive layer pattern is formed of a polysilicon layer and a silicide layer that are sequentially stacked. The method of claim 7, wherein In order to form the gate conductive film pattern of a polysilicon film and a silicide film laminated in sequence, Forming a polysilicon film on an entire surface of the semiconductor substrate including the gate oxide film to fill a region between the second insulating film patterns; Etching the entire polysilicon layer to form a polysilicon pattern having an upper surface lower than an upper surface of the second insulating layer pattern; Forming a silicide layer on an entire surface of the semiconductor substrate including the polysilicon pattern to fill a region between the second insulating layer patterns; And Forming a silicide layer pattern interposed between the second dielectric layer pattern by exposing the upper surface of the second dielectric layer pattern by etching the silicide layer on the entire surface. The method of claim 1, Forming the gate oxide film is a gate pattern forming method, characterized in that performed by a thermal oxidation process. The method of claim 1, And forming the first insulating layer pattern by using isotropic etching.