KR100344826B1 - Method for fabricating node contact of semiconductor device - Google Patents
Method for fabricating node contact of semiconductor device Download PDFInfo
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- KR100344826B1 KR100344826B1 KR1019990051379A KR19990051379A KR100344826B1 KR 100344826 B1 KR100344826 B1 KR 100344826B1 KR 1019990051379 A KR1019990051379 A KR 1019990051379A KR 19990051379 A KR19990051379 A KR 19990051379A KR 100344826 B1 KR100344826 B1 KR 100344826B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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Abstract
본 발명은 스토리지 노드 콘택(Storage Node Contact) 공정시 공정을 단순화시킴과 동시에 포토의 해상력 및 오버레이 마진을 향상시키도록 한 반도체 소자의 노드 콘택 형성방법에 관한 것으로서, 반도체 기판상에 일정한 간격으로 도전성 플러그가 형성된 절연막을 형성하는 단계와, 상기 도전성 플러그를 포함한 전면에 층간 절연막을 형성하는 단계와, 상기 층간 절연막상에 일정한 간격을 갖는 비트 라인을 형성하는 단계와, 상기 층간 절연막상에 제 1 질화막과 산화막과 제 2 질화막을 차례로 형성하는 단계와, 상기 제 2 질화막상에 평탄화용 절연막을 형성하는 단계와, 상기 도전성 플러그의 표면이 소정부분 노출되도록 상기 평탄화용 절연막, 제 2 질화막, 산화막, 제 1 질화막, 층간 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a node contact of a semiconductor device for simplifying a process in a storage node contact process and improving a resolution and overlay margin of a photo. Forming an insulating film on which the insulating plug is formed; forming an interlayer insulating film on the entire surface including the conductive plug; forming a bit line having a predetermined interval on the interlayer insulating film; and forming a first nitride film on the interlayer insulating film; Forming an oxide film and a second nitride film in sequence, forming a planarizing insulating film on the second nitride film, and forming the planarizing insulating film, the second nitride film, the oxide film, and the first film so that the surface of the conductive plug is partially exposed. Selectively removing the nitride film and the interlayer insulating film to form contact holes; The name of a feature.
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 스토리지 노드콘택(Storage Node Contact)공정시 공정을 단순화시키는데 적당한 반도체 소자의 노드 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming a node contact of a semiconductor device suitable for simplifying a process in a storage node contact process.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 노드 콘택 형성방법을 설명하면 다음과 같다.Hereinafter, a node contact forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 반도체 소자의 노드 콘택 형성방법을 나타낸 공정단면도이다.1A through 1E are cross-sectional views illustrating a method for forming node contacts in a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 절연막(12)을 형성하고, 포토 (Photo)및 식각공정을 통하여 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 상기 절연막(12)을 선택적으로 제거하여 콘택홀을 형성한다.As shown in FIG. 1A, an insulating film 12 is formed on the semiconductor substrate 11, and the insulating film 12 is exposed to expose a predetermined portion of the surface of the semiconductor substrate 11 through a photo and etching process. Is selectively removed to form a contact hole.
이어, 상기 콘택홀을 포함한 반도체 기판(11)의 전면에 제 1 폴리 실리콘층을 형성한 후 CMP(Chemical Mechanical Polishing) 또는 에치백(Etch Back) 공정을 실시하여 콘택홀의 내부에 폴리 실리콘 플러그(13)를 형성한다.Subsequently, a first polysilicon layer is formed on the entire surface of the semiconductor substrate 11 including the contact hole, and then a CMP (Chemical Mechanical Polishing) or an etch back process is performed to form a polysilicon plug 13 inside the contact hole. ).
도 1b에 도시한 바와 같이, 상기 폴리 실리콘 플러그(13)를 포함한 반도체 기판(11)의 전면에 층간 절연막(14)을 형성하고, 상기 층간 절연막(14)상에 텅스텐(W)막을 형성한다.As shown in FIG. 1B, an interlayer insulating film 14 is formed on the entire surface of the semiconductor substrate 11 including the polysilicon plug 13, and a tungsten (W) film is formed on the interlayer insulating film 14.
이어, 포토 및 식각공정으로 상기 텅스텐막을 선택적으로 제거하여 층간 절연막(14)상에 일정한 간격을 갖는 비트 라인(Bit Line)(15)을 형성한다.Subsequently, the tungsten film is selectively removed by a photo and etching process to form bit lines 15 having a predetermined interval on the interlayer insulating film 14.
그리고 상기 비트 라인(15)을 포함한 반도체 기판(11)의 전면에 질화막(16)을 600Å 두께로 형성한다.The nitride film 16 is formed on the entire surface of the semiconductor substrate 11 including the bit line 15 to a thickness of 600 Å.
도 1c에 도시한 바와 같이, 상기 질화막(16)상에 USG(Undoped SilicateGlass)막(17)을 형성한 후 CMP 공정을 실시하여 표면을 평탄화하고, 상기 USG막(17)상에 하드 마스크(Hard Mask)용 제 2 폴리 실리콘층(18)을 형성한다.As shown in FIG. 1C, after forming a USG (Undoped SilicateGlass) film 17 on the nitride film 16, a CMP process is performed to planarize the surface, and a hard mask (Hard) on the USG film 17. A second polysilicon layer 18 for a mask is formed.
이어, 상기 제 2 폴리 실리콘층(18)상에 포토레지스트막(19)을 도포한 후, 노광 및 현상공정으로 포토레지스트막(19)을 패터닝하여 콘택영역을 정의한다.Next, after the photoresist film 19 is coated on the second polysilicon layer 18, the photoresist film 19 is patterned by an exposure and development process to define a contact region.
그리고 상기 패터닝된 포토레지스트막(19)을 마스크로 이용하여 상기 제 2 폴리 실리콘층(18)을 선택적으로 제거한다.The second polysilicon layer 18 is selectively removed by using the patterned photoresist film 19 as a mask.
도 1d에 도시한 바와 같이, 상기 포토레지스트막(19)을 제거하고, 상기 선택적으로 제거된 제 2 폴리 실리콘층(18)을 마스크로 이용하여 상기 폴리 실리콘 플러그(13)의 표면이 소정부분 노출되도록 상기 USG막(17) 및 질화막(16) 그리고 층간 절연막(14)을 선택적으로 제거하여 콘택홀(20)을 형성한다.As shown in FIG. 1D, the surface of the polysilicon plug 13 is partially exposed by removing the photoresist film 19 and using the selectively removed second polysilicon layer 18 as a mask. The contact hole 20 is formed by selectively removing the USG film 17, the nitride film 16, and the interlayer insulating film 14 as much as possible.
도 1e에 도시한 바와 같이, 상기 하드 마스크용 제 1 폴리 실리콘층(18)을 제거하고, 상기 콘택홀(20)을 포함한 반도체 기판(11)의 전면에 제 3 폴리 실리콘층을 형성한 후 에치백하여 상기 콘택홀(20)의 내벽에 폴리 실리콘 측벽(21)을 형성한다.As shown in FIG. 1E, after removing the first polysilicon layer 18 for the hard mask and forming the third polysilicon layer on the entire surface of the semiconductor substrate 11 including the contact hole 20. The back side is formed to form the polysilicon sidewall 21 on the inner wall of the contact hole 20.
그러나 상기와 같은 종래의 반도체 소자의 노드 콘택 형성방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method for forming a node contact of a semiconductor device as described above, there are the following problems.
첫째, 스토리지 노드 콘택 공정시 폴리 실리콘 플러그와의 오버레이 마진(Overlay Margin) 및 포토의 한계 해상력을 고려하여 하드 마스크용 폴리 실리콘을 이용하여 절연막을 식각하여 콘택홀을 형성한 후 콘택홀 내벽에 폴리 실리콘측벽을 형성함으로서 스토리지 노드 콘택의 형성 공정이 복잡하다.First, in the storage node contact process, in consideration of the overlay margin with the polysilicon plug and the limit resolution of the photo, the insulating layer is etched using polysilicon for hard mask to form the contact hole, and then the polysilicon is formed on the inner wall of the contact hole. By forming sidewalls, the process of forming storage node contacts is complicated.
둘째, 콘택홀의 내벽에 폴리 실리콘 측벽의 형성시 발생된 이물질 때문에 콘택홀 오픈(Contact Hole Open)이 발생하여 생산성 및 수율 감소를 가져온다.Second, contact hole open occurs due to the foreign matter generated when the polysilicon sidewall is formed on the inner wall of the contact hole, resulting in reduced productivity and yield.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 스토리지 노드 콘택 공정시 공정을 단순화시킴과 동시에 포토의 해상력 및 오버레이 마진을 향상시키도록 한 반도체 소자의 노드 콘택 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned problems and provides a method for forming a node contact of a semiconductor device to simplify the process during the storage node contact process and to improve the resolution and overlay margin of the photo. There is this.
도 1a 내지 도 1e는 종래의 반도체 소자의 노드 콘택 형성방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method for forming a node contact of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 노드 콘택 형성방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method for forming a node contact of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 32 : 절연막31 semiconductor substrate 32 insulating film
33 : 폴리 실리콘 플러그 34 : 층간 절연막33 polysilicon plug 34 interlayer insulating film
35 : 비트 라인 36 : 제 1 질화막35: bit line 36: first nitride film
37 : 산화막 38 : 제 2 질화막37 oxide film 38 second nitride film
39 : USG막 40 : 포토레지스트막39: USG film 40: photoresist film
41 : 콘택홀41: contact hole
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 노드 콘택 형성방법은 반도체 기판상에 일정한 간격으로 도전성 플러그가 형성된 절연막을 형성하는 단계와, 상기 도전성 플러그를 포함한 전면에 층간 절연막을 형성하는 단계와, 상기 층간 절연막상에 일정한 간격을 갖는 비트 라인을 형성하는 단계와, 상기 층간 절연막상에 제 1 질화막과 산화막과 제 2 질화막을 차례로 형성하는 단계와, 상기 제 2 질화막상에 평탄화용 절연막을 형성하는 단계와, 상기 도전성 플러그의 표면이 소정부분 노출되도록 상기 평탄화용 절연막, 제 2 질화막, 산화막, 제 1 질화막, 층간 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The method for forming a node contact of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an insulating film formed with a conductive plug at regular intervals on a semiconductor substrate, and forming an interlayer insulating film on the entire surface including the conductive plug. Forming a bit line with a predetermined interval on the interlayer insulating film, sequentially forming a first nitride film, an oxide film, and a second nitride film on the interlayer insulating film, and a planarizing insulating film on the second nitride film. Forming a contact hole by selectively removing the planarization insulating film, the second nitride film, the oxide film, the first nitride film, and the interlayer insulating film so that the surface of the conductive plug is partially exposed. It features.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 노드 콘택 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a node contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 노드 콘택 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method for forming a node contact of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(31)상에 절연막(32)을 형성하고, 포토 및 식각공정을 통하여 상기 반도체 기판(31)의 표면이 소정부분 노출되도록 상기 절연막(32)을 선택적으로 제거하여 콘택홀을 형성한다.As shown in FIG. 2A, an insulating film 32 is formed on the semiconductor substrate 31, and the insulating film 32 is selectively exposed so that a predetermined portion of the surface of the semiconductor substrate 31 is exposed through photo and etching processes. To form a contact hole.
이어, 상기 콘택홀을 포함한 반도체 기판(31)의 전면에 폴리 실리콘을 형성한 후 CMP 또는 에치백 공정을 실시하여 콘택홀의 내부에 폴리 실리콘 플러그(33)를 형성한다.Subsequently, after the polysilicon is formed on the entire surface of the semiconductor substrate 31 including the contact hole, the polysilicon plug 33 is formed inside the contact hole by performing a CMP or etch back process.
도 2b에 도시한 바와 같이, 상기 폴리 실리콘 플러그(33)를 포함한 반도체 기판(31)의 전면에 층간 절연막(34)을 형성하고, 상기 층간 절연막(34)상에 텅스텐막을 형성한다.As shown in FIG. 2B, an interlayer insulating film 34 is formed on the entire surface of the semiconductor substrate 31 including the polysilicon plug 33, and a tungsten film is formed on the interlayer insulating film 34.
이어, 포토 및 식각공정으로 상기 텅스텐막을 선택적으로 제거하여 층간 절연막(34)상에 일정한 간격을 갖는 비트 라인(35)을 형성한다.Subsequently, the tungsten film is selectively removed by a photo and etching process to form bit lines 35 having a predetermined gap on the interlayer insulating film 34.
그리고 상기 비트 라인(35)을 포함한 반도체 기판(31)의 전면에 제 1 질화막(36)을 600Å 두께로 형성하고, 상기 제 1 질화막(36)상에 산화막(37)을 형성하고, 상기 산화막(37)상에 제 2 질화막(38)을 600Å 두께로 형성한다.A first nitride film 36 is formed on the entire surface of the semiconductor substrate 31 including the bit line 35 to a thickness of 600 Å, an oxide film 37 is formed on the first nitride film 36, and the oxide film ( A second nitride film 38 is formed on the substrate 37 at a thickness of 600 mm 3.
여기서 상기 제 1, 제 2 질화막(36,38)을 적층하여 형성하는 이유는 스토리지 노드 콘택 형성시 콘택홀의 슬로프(Slope)를 발생하여 바텀(Bottom) CD(Critical Dimension)를 확보하기 위해서이다.The first and second nitride layers 36 and 38 are stacked to form slopes of contact holes when forming storage node contacts to secure bottom CD (Critical Dimension).
도 2c에 도시한 바와 같이, 상기 제 2 질화막(38)상에 USG막(39)을 형성한 후 CMP 공정을 실시하여 표면을 평탄화한다.As shown in FIG. 2C, after forming the USG film 39 on the second nitride film 38, the CMP process is performed to planarize the surface.
이어, 상기 USG막(39)상에 포토레지스트막(40)을 도포한 후, 노광 및 현상공정으로 포토레지스트막(40)을 패터닝하여 콘택영역을 정의한다.Subsequently, after applying the photoresist film 40 on the USG film 39, the photoresist film 40 is patterned by an exposure and development process to define a contact region.
그리고 상기 패터닝된 포토레지스트막(40)을 마스크로 이용하여 상기 폴리 실리콘 플러그(33)의 표면이 소정부분 노출되도록 상기 USG막(39), 제 2 질화막(38), 산화막(37), 제 1 질화막(36), 층간 절연막(34)을 선택적으로 제거하여 콘택홀(41)을 형성한다.The USG film 39, the second nitride film 38, the oxide film 37, and the first film are exposed to a predetermined portion of the surface of the polysilicon plug 33 by using the patterned photoresist film 40 as a mask. The nitride film 36 and the interlayer insulating film 34 are selectively removed to form the contact hole 41.
여기서 상기 산화막(37)을 사이에 두고 제 1, 제 2 질화막(36,38)을 형성함으로써 콘택홀(41)을 형성하기 위해 산화막(37)의 식각시 슬로프(Slope)를 발생시키어 CD를 줄일 수 있다.Here, by forming the first and second nitride films 36 and 38 with the oxide film 37 interposed therebetween, a slope is generated during etching of the oxide film 37 to form the contact holes 41, thereby reducing CD. Can be.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 노드 콘택 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a node contact of a semiconductor device according to the present invention has the following effects.
첫째, 하드 마스크용 폴리 실리콘의 증착 및 식각, 폴리 실리콘 측벽 공정이 필요하지 않기 때문에 공정 스텝(Step) 수를 줄이어 공정을 단순화시킬 수 있다.First, since the deposition and etching of polysilicon for the hard mask and the polysilicon sidewall process are not required, the process can be simplified by reducing the number of process steps.
둘째, 질화막의 층수 및 두께 조절을 통하여 오버레이 마진을 확보할 수 있다.Second, overlay margin can be secured by adjusting the number and thickness of the nitride film.
셋째, 폴리 실리콘 측벽을 형성하지 않기 때문에 폴리 실리콘을 스토리지 노드 콘택 공정에 사용시 최종 공정후에 발생하는 이물에 의해 콘택홀 오픈이 발생하여 수율 저하 등의 치명적인 원인이 일어나는 것을 방지할 수 있다.Third, since the polysilicon sidewalls are not formed, contact holes open due to foreign matters generated after the final process when the polysilicon is used in the storage node contact process, thereby preventing fatal causes such as yield decrease.
넷째, 폴리 실리콘을 사용하지 않음으로 웨이퍼 주변부의 폴리 실리콘층이 벗겨지는 현상을 방지할 수 있다.Fourth, the polysilicon layer around the wafer may be peeled off by not using polysilicon.
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