KR20000019959A - Method for forming plug of semiconductor device - Google Patents
Method for forming plug of semiconductor device Download PDFInfo
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- KR20000019959A KR20000019959A KR1019980038322A KR19980038322A KR20000019959A KR 20000019959 A KR20000019959 A KR 20000019959A KR 1019980038322 A KR1019980038322 A KR 1019980038322A KR 19980038322 A KR19980038322 A KR 19980038322A KR 20000019959 A KR20000019959 A KR 20000019959A
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- forming
- insulating film
- plug
- contact hole
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000001312 dry etching Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract 5
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 공정 마진을 향상시키도록 한 반도체 소자의 플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a method for forming a plug of a semiconductor device to improve process margins.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 플러그 형성방법을 설명하면 다음과 같다.Hereinafter, a plug forming method of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래 기술의 반도체 소자의 플러그 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a plug of a semiconductor device of the related art.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 게이트 절연막(12)을 개재하여 게이트 전극(13)을 형성하고, 상기 게이트 전극(13)상에 캡 게이트 절연막(14)을 형성한다.As shown in FIG. 1A, the gate electrode 13 is formed on the semiconductor substrate 11 via the gate insulating film 12, and the cap gate insulating film 14 is formed on the gate electrode 13.
여기서 상기 게이트 전극(13)은 폴리 실리콘과 텅스텐 실리사이드가 적층되어 형성된다.The gate electrode 13 is formed by stacking polysilicon and tungsten silicide.
이어, 상기 반도체 기판(11)의 전면에 질화막(15)을 형성한다.Next, a nitride film 15 is formed on the entire surface of the semiconductor substrate 11.
도 1b에 도시한 바와 같이, 상기 질화막(15)상에 HLD(High temperature Low pressure Deposition)막(16)을 형성한 후, 전면에 CMP(Chemical Mechanical Polishing) 공정을 실시하여 표면을 평탄화시킨다.As shown in FIG. 1B, after forming a high temperature low pressure deposition (HLD) film 16 on the nitride film 15, the surface is planarized by performing a chemical mechanical polishing (CMP) process on the entire surface.
도 1c에 도시한 바와 같이, 상기 HLD막(16)상에 포토레지스트(17)를 도포한 후, 노광 및 현상공정을 실시하여 포토레지스트(17)를 패터닝한다.As shown in FIG. 1C, after the photoresist 17 is applied onto the HLD film 16, the photoresist 17 is patterned by performing exposure and development processes.
이어, 상기 패터닝된 포토레지스트(17)를 마스크로 이용하여 상기 반도체 기판(11)의 표면이 노출되도록 상기 HLD막(16) 및 질화막(15)을 건식식각으로 제거하여 콘택홀(18)을 형성한다.Subsequently, the HLD layer 16 and the nitride layer 15 are removed by dry etching to expose the surface of the semiconductor substrate 11 using the patterned photoresist 17 as a mask to form a contact hole 18. do.
이때 상기 HLD막(16) 및 질화막(15)을 건식식각(Dry Etch)으로 제거할 때 캡 게이트 절연막(14)의 에지(Edge)부분도 식각된다.At this time, when the HLD film 16 and the nitride film 15 are removed by dry etching, the edge portion of the cap gate insulating film 14 is also etched.
도 1d에 도시한 바와 같이, 상기 포토레지스트(17)를 제거하고, 상기 콘택홀(18)을 포함한 반도체 기판(11)의 전면에 플러그용 폴리 실리콘을 형성한 후, 전면에 에치백 공정을 실시하여 상기 콘택홀(18)의 내부에 플러그(19)를 형성한다.As shown in FIG. 1D, the photoresist 17 is removed, a plug polysilicon is formed on the entire surface of the semiconductor substrate 11 including the contact hole 18, and then an etch back process is performed on the entire surface. As a result, a plug 19 is formed in the contact hole 18.
그러나 이와 같은 종래의 반도체 소자의 플러그 형성방법에 있어서 다음과 같은 문제점이 있었다.However, such a conventional method for forming a plug of a semiconductor device has the following problems.
즉, 건식식각으로 콘택홀을 형성하기 때문에 게이트와 플러그간의 마진(Margin)의 감소 및 탑(Top) 플러그의 CD(Critical Demension) 편차(Variation)에 따른 후속 포토공정(비트라인 콘택, 스토리지 노드콘택 등)의 오버레이 마진(Overlay Margin)이 감소한다.In other words, since the contact hole is formed by dry etching, a subsequent photo process (bit line contact, storage node contact) according to the reduction of the margin between the gate and the plug and the variation of the CD (Critical Demension) of the top plug Overlay margin) is reduced.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 콘택홀을 크게 디파인(Define)함으로써 후속 포토 공정의 오버레이 마진 증가 및 최종 식각량 감소로 인한 게이트와 플러그간의 마진을 증가시키도록 한 반도체 소자의 플러그 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The semiconductor device is designed to increase the margin between the gate and the plug due to the increase of the overlay margin and the final etching amount of the subsequent photo process by greatly defining the contact hole. The purpose is to provide a method of forming a plug.
도 1a 내지 도 1d는 종래 기술의 반도체 소자의 플러그 형성방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of forming a plug of a semiconductor device of the related art.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 플러그 형성방법을 나타낸 공정단면도2A through 2F are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 게이트 절연막21 semiconductor substrate 22 gate insulating film
23 : 게이트 전극 24 : 캡 게이트 절연막23 gate electrode 24 cap gate insulating film
25 : 질화막 26 : HLD막25 nitride film 26 HLD film
27 : 포토레지스트 28 : 콘택홀27: photoresist 28: contact hole
29 : 플러그29: plug
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 플러그 형성방법은 반도체 기판상에 게이트 절연막을 개재하여 복수개의 게이트 전극들을 형성하는 단계와, 상기 각 게이트 전극상에 캡 게이트 절연막을 형성하는 단계와, 상기 반도체 기판의 전면에 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막상에 제 2 절연막을 형성하는 단계와, 상기 게이트 전극 상부의 제 2 절연막상에 마스크층을 형성하는 단계와, 상기 마스크층을 마스크로 이용하여 건식-습식-건식식각 순으로 상기 제 2 절연막 및 제 1 절연막을 선택적으로 제거하여 반도체 기판의 표면이 노출되도록 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 도전성 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.The method of forming a plug of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a plurality of gate electrodes on the semiconductor substrate via a gate insulating film, and forming a cap gate insulating film on each gate electrode Forming a first insulating film on the entire surface of the semiconductor substrate, forming a second insulating film on the first insulating film, and forming a mask layer on the second insulating film on the gate electrode; Selectively removing the second insulating film and the first insulating film in a dry-wet-dry etching order using the mask layer as a mask to form a contact hole so that the surface of the semiconductor substrate is exposed; And forming a conductive plug.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 플러그 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a plug of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 플러그 형성방법을 나타낸 공정단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 게이트 절연막(22)을 개재하여 복수개의 게이트 전극(23)들을 형성하고, 상기 각 게이트 전극(23)상에 캡 게이트 절연막(24)을 형성한다.As shown in FIG. 2A, a plurality of gate electrodes 23 are formed on the semiconductor substrate 21 via the gate insulating film 22, and a cap gate insulating film 24 is formed on each of the gate electrodes 23. Form.
여기서 상기 게이트 전극(23)은 폴리 실리콘과 텅스텐 실리사이드가 적층되어 형성된다.The gate electrode 23 is formed by stacking polysilicon and tungsten silicide.
이어, 상기 반도체 기판(21)을 전면에 질화막(25)을 형성한다.Next, the nitride film 25 is formed on the entire surface of the semiconductor substrate 21.
여기서 상기 캡 게이트 절연막(24)은 상기 질화막(25)과 식각선택비가 동일한 절연막이다.The cap gate insulating layer 24 is an insulating layer having the same etching selectivity as the nitride layer 25.
도 2b에 도시한 바와 같이, 상기 질화막(25)상에 HLD(High temperature Low pressure Deposition)막(26)을 형성한 후, 전면에 CMP(Chemical Mechanical Polishing) 공정을 실시하여 표면을 평탄화시킨다.As shown in FIG. 2B, after forming a high temperature low pressure deposition (HLD) film 26 on the nitride film 25, the surface is planarized by performing a chemical mechanical polishing (CMP) process on the entire surface.
도 2c에 도시한 바와 같이, 상기 HLD막(26)상에 포토레지스트(27)를 도포한 후, 노광 및 현상공정을 실시하여 포토레지스트(27)를 패터닝한다.As shown in FIG. 2C, after the photoresist 27 is applied onto the HLD film 26, the photoresist 27 is patterned by performing exposure and development processes.
이어, 상기 패터닝된 포토레지스트(27)를 마스크로 이용하여 상기 질화막(25)의 상부 표면이 노출되도록 상기 HLD막(26)을 건식식각 공정을 이용하여 선택적으로 제거한다.Subsequently, the HLD layer 26 is selectively removed using a dry etching process so that the upper surface of the nitride layer 25 is exposed using the patterned photoresist 27 as a mask.
도 2d에 도시한 바와 같이, 상기 포토레지스트(27)를 마스크로 이용하여 상기 HLD막(26)을 표면으로부터 소정두께 만큼 제거되도록 습식식각(Wet Etch) 공정을 실시한다.As shown in FIG. 2D, a wet etching process is performed to remove the HLD layer 26 by a predetermined thickness using the photoresist 27 as a mask.
이때 상기 포토레지스트(27)의 하부에 형성된 HLD막(26)도 안쪽으로 소정두께가 식각된다.At this time, the HLD film 26 formed under the photoresist 27 is also etched inward.
여기서 습식식각 공정을 실시하는 이유는 상기의 건식식각한 후에 재차 습식식각 공정을 실시함으로서 이후에 형성되는 콘택홀의 상부 면적을 넓게 디파인(Define)하기 위해서이다.The wet etching process is performed in order to broaden the upper area of the contact hole to be formed later by performing the wet etching process after the dry etching.
도 2e에 도시한 바와 같이, 상기 포토레지스트(27)를 마스크로 이용하여 상기 반도체 기판(21)의 표면이 노출되도록 건식식각 공정을 실시하여 상기 HLD막(26) 및 질화막(25)을 선택적으로 제거하여 콘택홀(28)을 형성한다.As shown in FIG. 2E, the HLD film 26 and the nitride film 25 are selectively subjected to a dry etching process using the photoresist 27 as a mask to expose the surface of the semiconductor substrate 21. To form a contact hole 28.
여기서 상기 질화막(25)이 선택적으로 제거될 때 상기 캡 게이트 절연막(24)의 에지부분도 선택적으로 제거된다.Here, when the nitride film 25 is selectively removed, the edge portion of the cap gate insulating film 24 is also selectively removed.
도 2f에 도시한 바와 같이, 상기 포토레지스트(27)를 제거하고, 상기 콘택홀(28)을 포함한 반도체 기판(21)의 전면에 플러그용 폴리 실리콘을 형성한 후, 전면에 에치백 공정을 실시하여 상기 콘택홀(28)의 내부에 플러그(29)를 형성한다.As shown in FIG. 2F, the photoresist 27 is removed, a plug polysilicon is formed on the entire surface of the semiconductor substrate 21 including the contact hole 28, and then an etch back process is performed on the entire surface. As a result, a plug 29 is formed in the contact hole 28.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 플러그 형성방법에 있어서 다음과 같은 효과가 있다.As described above, the plug forming method of the semiconductor device according to the present invention has the following effects.
첫째, 콘택홀을 형성할 때 건식식각 공정을 이용하여 절연막을 선택적으로 제거한 후 습식식각 공정을 실시하여 플러그가 형성될 영역을 크게 함으로서 후속 포토 공정에서의 오버레이 마진을 증가할 수 있다.First, when the contact hole is formed, the insulating layer may be selectively removed using a dry etching process, and then a wet etching process may be performed to increase the area where the plug is to be formed, thereby increasing the overlay margin in the subsequent photo process.
둘째, 습식식각 후에 건식식각 공정을 이용하여 콘택홀을 형성함으로써 식각량 감소로 인한 게이트와 플러그간의 마진을 증가시킬 수 있다.Second, by forming a contact hole using a dry etching process after the wet etching, it is possible to increase the margin between the gate and the plug due to the reduction of the etching amount.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980038322A KR20000019959A (en) | 1998-09-16 | 1998-09-16 | Method for forming plug of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980038322A KR20000019959A (en) | 1998-09-16 | 1998-09-16 | Method for forming plug of semiconductor device |
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| KR20000019959A true KR20000019959A (en) | 2000-04-15 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01230252A (en) * | 1988-03-09 | 1989-09-13 | Sharp Corp | Contact-hole forming method |
| KR910010623A (en) * | 1989-11-18 | 1991-06-29 | 문정환 | Contact etching method using characteristics of dry etching and wet etching |
| JPH0574953A (en) * | 1991-09-13 | 1993-03-26 | Fuji Xerox Co Ltd | Manufacture of semiconductor device |
| JPH08213458A (en) * | 1995-02-06 | 1996-08-20 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH1174476A (en) * | 1997-08-29 | 1999-03-16 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR0183764B1 (en) * | 1995-12-05 | 1999-04-15 | 김광호 | Landing pad |
-
1998
- 1998-09-16 KR KR1019980038322A patent/KR20000019959A/en not_active Application Discontinuation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01230252A (en) * | 1988-03-09 | 1989-09-13 | Sharp Corp | Contact-hole forming method |
| KR910010623A (en) * | 1989-11-18 | 1991-06-29 | 문정환 | Contact etching method using characteristics of dry etching and wet etching |
| JPH0574953A (en) * | 1991-09-13 | 1993-03-26 | Fuji Xerox Co Ltd | Manufacture of semiconductor device |
| JPH08213458A (en) * | 1995-02-06 | 1996-08-20 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| KR0183764B1 (en) * | 1995-12-05 | 1999-04-15 | 김광호 | Landing pad |
| JPH1174476A (en) * | 1997-08-29 | 1999-03-16 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
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