KR20000051805A - Manufacturing method for semiconductor memory - Google Patents
Manufacturing method for semiconductor memory Download PDFInfo
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- KR20000051805A KR20000051805A KR1019990002447A KR19990002447A KR20000051805A KR 20000051805 A KR20000051805 A KR 20000051805A KR 1019990002447 A KR1019990002447 A KR 1019990002447A KR 19990002447 A KR19990002447 A KR 19990002447A KR 20000051805 A KR20000051805 A KR 20000051805A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체 메모리 제조방법에 관한 것으로, 특히 플러그 형성을 위한 다결정실리콘의 증착전에 주변회로영역의 상부에 절연층을 미리증착하고, 그 다결정실리콘을 식각하여 플러그를 형성함으로써 주변회로영역의 모스 트랜지스터 측면에 잔존하지 않도록 하여 소자의 신뢰성을 향상시키는데 적당하도록 한 반도체 메모리 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory, and in particular, an MOS transistor in a peripheral circuit region is formed by depositing an insulating layer on the upper portion of a peripheral circuit region in advance and forming a plug by etching the polysilicon layer before depositing polycrystalline silicon for plug formation. The present invention relates to a semiconductor memory manufacturing method suitable for improving the reliability of a device by not remaining on the side surface.
도1a 내지 도1c는 종래 반도체 메모리의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)에 건식식각공정을 통해 트랜치를 형성하고, 그 트랜치가 형성된 기판(1)의 상부전면에 산화막을 증착한 후, 그 산화막을 평탄화하여 상기 트랜치 내에 위치하는 필드산화막(2)을 형성함으로써 반도체 메모리의 메모리셀이 형성될 셀영역(10)과 그 메모리셀을 구동하는 주변회로가 형성될 주변회로영역(20)을 정의하는 단계(도1a)와; 상기 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막, 다결정실리콘, 절연층을 순차적으로 증착하고, 사진식각공정을 통해 상기 적층된 절연층, 다결정실리콘, 게이트산화막을 패터닝하여 상기 셀영역(10)과 주변회로영역(20)의 상부에 게이트를 형성한 후, 불순물 이온주입을 통해 소스 및 드레인을 형성하는 단계(도1b)와; 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 산화막(3)을 증착한 후, 상기 셀영역(10)에 증착된 산화막(3)만을 건식식각하여 상기 셀영역(10)에 형성한 게이트의 측면에 측벽(4)을 형성하고, 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 다결정실리콘을 증착하고, 그 다결정실리콘을 에치백(ETCH BACK)하여 상기 셀영역(10)의 측벽(4) 사이에 위치하는 플러그(5)를 형성하고, 상기 주변회로영역(20)의 산화막(3)을 노출시키는 단계(도1c)를 포함하여 구성된다.1A to 1C are cross-sectional views illustrating a process of manufacturing a conventional semiconductor memory. As shown in FIG. 1, a trench is formed on a substrate 1 through a dry etching process, and an oxide film is formed on an upper surface of the substrate 1 on which the trench is formed. After deposition, the oxide film is planarized to form a field oxide film 2 positioned in the trench, thereby forming a cell region 10 in which a memory cell of a semiconductor memory is to be formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is to be formed. Defining 20 (FIG. 1A); The gate oxide film, the polysilicon, and the insulating layer are sequentially deposited on the upper surface of the substrate 1 on which the field oxide film 2 is formed, and the stacked insulating layer, the polysilicon, and the gate oxide film are patterned by a photolithography process. Forming a source and a drain through impurity ion implantation after forming a gate over the cell region 10 and the peripheral circuit region 20 (FIG. 1B); After depositing an oxide film 3 on the upper surface of the cell region 10 and the peripheral circuit region 20, only the oxide film 3 deposited on the cell region 10 is dry etched to the cell region 10. The sidewalls 4 are formed on the side surfaces of the formed gates, polysilicon is deposited on the upper surface of the cell region 10 and the peripheral circuit region 20, and the polysilicon is etched back to the cell. And forming a plug 5 located between the sidewalls 4 of the region 10 and exposing the oxide film 3 of the peripheral circuit region 20 (FIG. 1C).
이하, 상기와 같은 종래 반도체 메모리 제조방법을 좀 더 상세히 설명한다.Hereinafter, a conventional method of manufacturing a semiconductor memory as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 포토레지스트 패턴을 형성한 후, 그 포토레지스트 패턴을 식각마스크로 사용하는 건식식각공정으로 상기 기판(1)의 일부영역을 식각하여 트랜치를 형성한다.First, as shown in FIG. 1A, a photoresist pattern is formed on an upper portion of the substrate 1, and then a partial region of the substrate 1 is etched by a dry etching process using the photoresist pattern as an etching mask. To form.
그 다음, 상기 포토레지스트 패턴을 제거하고 트랜치가 형성된 기판(1)의 상부전면에 산화막을 증착한 후에 에치백하여 상기 트랜치내에 위치하는 필드산화막(2)을 형성한다. 이와 같이 필드산화막(2)을 형성함으로써, 소자형성영역을 정의할 수 있으며, 그 소자형성영역을 셀영역(10)과 주변회로영역(20)으로 구분할 수 있다.Next, the photoresist pattern is removed, an oxide film is deposited on the upper surface of the trench 1, and then etched back to form a field oxide film 2 positioned in the trench. By forming the field oxide film 2 as described above, the device formation region can be defined, and the device formation region can be divided into the cell region 10 and the peripheral circuit region 20.
그 다음, 도1b에 도시한 바와 같이 상기 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막, 다결정실리콘, 절연층을 순차적으로 증착하고, 사진식각공정을 통해 상기 적층된 절연층, 다결정실리콘, 게이트산화막을 패터닝하여 상기 셀영역(10)과 주변회로영역(20)의 상부에 게이트를 형성한다.Next, as illustrated in FIG. 1B, a gate oxide film, a polysilicon layer, and an insulating layer are sequentially deposited on the upper surface of the substrate 1 on which the field oxide film 2 is formed, and the stacked insulating layers are formed through a photolithography process. The gate layer is formed on the cell region 10 and the peripheral circuit region 20 by patterning the polysilicon and the gate oxide layer.
그 다음, 불순물 이온주입을 통해 저농도 소스 및 드레인을 상기 주변회로영역(20)과 셀영역(10)의 기판(1)하부에 형성한다.Next, a low concentration source and a drain are formed under the substrate 1 of the peripheral circuit region 20 and the cell region 10 through impurity ion implantation.
그 다음, 도1c에 도시한 바와 같이 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 산화막(3)을 증착한 후, 상기 주변회로영역(20)의 상부에 포토레지스트패턴을 형성한다.Next, as shown in FIG. 1C, an oxide film 3 is deposited on the upper surface of the cell region 10 and the peripheral circuit region 20, and then a photoresist pattern is formed on the peripheral circuit region 20. Form.
그 다음, 상기 포토레지스트패턴을 식각마스크로 사용하는 건식식각공정으로 상기 셀영역(10)에 증착된 산화막(3)만을 선택적으로 식각하여 상기 셀영역(10)에 형성한 게이트의 측면에 측벽(4)을 형성한다. 이때의 측벽(4)은 플러그의 형성시 게이트와 전기적으로 접속되는 것을 방지하며, 셀프어라인 방식으로 플러그를 제조하기 위한 것이다.Subsequently, a dry etching process using the photoresist pattern as an etching mask may selectively etch only the oxide film 3 deposited in the cell region 10 to form sidewalls on the side surfaces of the gate formed in the cell region 10. 4) form. At this time, the side wall 4 is to prevent the electrical connection with the gate when the plug is formed, and to manufacture the plug in a self-aligned manner.
그 다음, 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 다결정실리콘을 증착하고, 그 다결정실리콘을 에치백(ETCH BACK)하여 상기 셀영역(10)의 측벽(4) 사이에 위치하는 플러그(5)를 형성하고, 상기 주변회로영역(20)의 산화막(3)을 노출시킨다. 이때, 상기 주변회로영역(20)에 형성된 게이트의 측면 산화막(3)의 측면에는 다결정실리콘이 잔존하게 된다.Next, polysilicon is deposited on the upper surface of the cell region 10 and the peripheral circuit region 20, and the polysilicon is etched back to between the sidewalls 4 of the cell region 10. A plug 5 is positioned to expose the oxide film 3 of the peripheral circuit region 20. In this case, polysilicon remains on the side surface of the side oxide film 3 of the gate formed in the peripheral circuit region 20.
이와 같이 다결정실리콘이 잔존하는 상태에서 후속공정을 진행하는 경우 잔존하는 다결정실리콘에 의해 게이트와 소스 및 드레인이 전기적으로 접속되거나, 서로다른 게이트가 전기적으로 연결되는 경우가 발생하게 된다.As described above, when the subsequent process is performed while the polysilicon remains, the gate, the source, and the drain are electrically connected by the remaining polycrystalline silicon, or different gates are electrically connected.
상기한 바와 같이 종래 반도체 메모리 제조방법은 플러그 형성을 목적으로 다결정실리콘을 증착하고, 에치백하는 과정에서 주변회로영역의 게이트 측면에 다결정실리콘이 잔존하게 되어, 게이트와 소스 및 드레인 또는 게이트간에 전기적인 연결이 발생하여 소자의 신뢰성 및 특성을 저하시키는 문제점이 있었다.As described above, in the conventional semiconductor memory manufacturing method, polycrystalline silicon is deposited on the gate side of the peripheral circuit region in the process of depositing and etching back the polysilicon for the purpose of forming a plug. There was a problem in that connection occurred, which degraded the reliability and characteristics of the device.
이와 같은 문제점을 감안한 본 발명은 주변회로영역에 다결정실리콘 잔류물이 잔존하는 것을 방지할 수 있는 반도체 메모리 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a semiconductor memory manufacturing method capable of preventing the remaining of polysilicon residues in a peripheral circuit region.
도1a 내지 도1c는 종래 반도체 메모리의 제조공정 수순단면도.1A to 1C are cross-sectional views of a manufacturing process of a conventional semiconductor memory.
도2a 내지 도2d는 본 발명 반도체 메모리의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the semiconductor memory of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판2:필드산화막1: Substrate 2: Field oxide film
3:산화막4:측벽3: oxide film 4: side wall
5:플러그6:절연층5: Plug 6: Insulation layer
상기와 같은 목적은 플러그 형성을 목적으로 다결정실리콘을 증착하기 이전에 주변회로영역의 상부전면에 절연막을 형성하고, 플러그를 형성한 후 그 절연막을 제거함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is achieved by forming an insulating film on the upper surface of the peripheral circuit region before depositing polycrystalline silicon for the purpose of plug formation, and removing the insulating film after forming the plug. When described in detail with reference to the drawings as follows.
도2a 내지 도2d는 본 발명 반도체 메모리 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)에 건식식각공정을 통해 트랜치를 형성하고, 그 트랜치가 형성된 기판(1)의 상부전면에 산화막을 증착한 후, 그 산화막을 평탄화하여 상기 트랜치 내에 위치하는 필드산화막(2)을 형성함으로써 반도체 메모리의 메모리셀이 형성될 셀영역(10)과 그 메모리셀을 구동하는 주변회로가 형성될 주변회로영역(20)을 정의하는 단계(도2a)와; 상기 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막, 다결정실리콘, 절연층을 순차적으로 증착하고, 사진식각공정을 통해 상기 적층된 절연층, 다결정실리콘, 게이트산화막을 패터닝하여 상기 셀영역(10)과 주변회로영역(20)의 상부에 게이트를 형성한 후, 불순물 이온주입을 통해 소스 및 드레인을 형성하는 단계(도2b)와; 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 산화막(3)을 증착한 후, 상기 셀영역(10)에 증착된 산화막(3)만을 건식식각하여 상기 셀영역(10)에 형성한 게이트의 측면에 측벽(4)을 형성하고, 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 절연층(6)을 증착하고, 사진식각공정을 통해 패터닝하여 상기 주변회로영역(20)의 상부에만 절연층(6)을 형성한 후, 상기 셀영역(10)과 주변회로영역(20)의 상부에 다결정실리콘을 증착하고, 그 다결정실리콘을 평탄화하여 상기 셀영역(10)의 측벽(4) 사이에 위치하는 플러그(5)를 형성하는 단계(도2c)와; 상기 절연층(6)을 식각하여 주변회로영역(20)의 산화막(3)을 노출시키는 단계(도2d)를 포함하여 구성된다.2A to 2D are cross-sectional views of a semiconductor memory fabrication process of the present invention, in which a trench is formed in the substrate 1 through a dry etching process, and an oxide film is formed on the upper surface of the substrate 1 on which the trench is formed. After deposition, the oxide film is planarized to form a field oxide film 2 positioned in the trench, thereby forming a cell region 10 in which a memory cell of a semiconductor memory is to be formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is to be formed. Defining 20 (FIG. 2A); The gate oxide film, the polysilicon, and the insulating layer are sequentially deposited on the upper surface of the substrate 1 on which the field oxide film 2 is formed, and the stacked insulating layer, the polysilicon, and the gate oxide film are patterned by a photolithography process. Forming a source and a drain through impurity ion implantation after forming a gate over the cell region 10 and the peripheral circuit region 20 (FIG. 2B); After depositing an oxide film 3 on the upper surface of the cell region 10 and the peripheral circuit region 20, only the oxide film 3 deposited on the cell region 10 is dry etched to the cell region 10. The side wall 4 is formed on the side of the gate, the insulating layer 6 is deposited on the upper surface of the cell region 10 and the peripheral circuit region 20, and patterned by a photolithography process to form the peripheral circuit. After the insulating layer 6 is formed only on the region 20, polycrystalline silicon is deposited on the cell region 10 and the peripheral circuit region 20, and the polycrystalline silicon is planarized to form the cell region 10. Forming a plug (5) located between the sidewalls (4) of Fig. 2; The insulating layer 6 is etched to expose the oxide film 3 in the peripheral circuit region 20 (FIG. 2D).
이하, 상기와 같은 본 발명 반도체 메모리 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the semiconductor memory of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 포토레지스트 패턴을 형성한 후, 그 포토레지스트 패턴을 식각마스크로 사용하는 건식식각공정으로 상기 기판(1)의 일부영역을 식각하여 트랜치를 형성하고, 상기 포토레지스트 패턴을 제거한다.First, as shown in FIG. 2A, a photoresist pattern is formed on the substrate 1, and then a portion of the substrate 1 is etched by a dry etching process using the photoresist pattern as an etching mask. To form a photoresist pattern.
그 다음, 트랜치가 형성된 기판(1)의 상부전면에 산화막을 증착한 후에 에치백하여 상기 트랜치내에 위치하는 필드산화막(2)을 형성하여 종래와 동일하게 셀영역(10)과 주변회로영역(20)을 정의한다.Thereafter, an oxide film is deposited on the upper surface of the trench 1, and then etched back to form a field oxide film 2 positioned in the trench, thereby forming the cell region 10 and the peripheral circuit region 20 as in the prior art. ).
그 다음, 도2b에 도시한 바와 같이 상기 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막, 다결정실리콘, 절연층을 순차적으로 증착하고, 사진식각공정을 통해 상기 적층된 절연층, 다결정실리콘, 게이트산화막을 패터닝하여 상기 셀영역(10)과 주변회로영역(20)의 상부에 게이트를 형성하고, 저농도 소스 및 드레인을 형성한다.Next, as illustrated in FIG. 2B, a gate oxide film, a polysilicon layer, and an insulating layer are sequentially deposited on the upper surface of the substrate 1 on which the field oxide film 2 is formed, and the stacked insulating layers are formed through a photolithography process. By patterning the polysilicon and the gate oxide film, a gate is formed on the cell region 10 and the peripheral circuit region 20, and a low concentration source and a drain are formed.
그 다음, 도2c에 도시한 바와 같이 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 산화막(3)을 증착한 후, 셀영역(10)의 산화막(3)을 선택적으로 건식식각하여 상기 셀영역(10)에 형성한 게이트의 측면에 측벽(4)을 형성한다.Next, as shown in FIG. 2C, an oxide film 3 is deposited on the upper surface of the cell region 10 and the peripheral circuit region 20, and then the oxide film 3 of the cell region 10 is selectively dried. The sidewalls 4 are formed on the side surfaces of the gates formed in the cell region 10 by etching.
그 다음, 상기 셀영역(10)과 주변회로영역(20)의 상부에 절연층(6)을 증착하고, 사진식각공정을 통해 상기 셀영역(10)의 상부에 증착된 절연층(6)을 선택적으로 제거하여 상기 주변회로영역(20)의 상부에 증착된 산화막(3)의 상부에 위치하는 절연층(6) 패턴을 형성한다.Next, an insulating layer 6 is deposited on the cell region 10 and the peripheral circuit region 20, and the insulating layer 6 deposited on the cell region 10 is deposited through a photolithography process. It is selectively removed to form a pattern of the insulating layer 6 located on the oxide film 3 deposited on the peripheral circuit region 20.
그 다음, 상기 셀영역(10)과 주변회로영역(20)의 상부전면에 다결정실리콘을 증착하고, 그 다결정실리콘을 에치백하여 상기 셀영역의 측벽(4) 사이에 위치하며, 상기 셀영역(10)에 형성된 저농도 소스 및 드레인에 접속되는 플러그(5)를 형성한다.Next, polycrystalline silicon is deposited on the upper surface of the cell region 10 and the peripheral circuit region 20, and the polycrystalline silicon is etched back and positioned between the sidewalls 4 of the cell region. The plug 5 connected to the low concentration source and drain formed in 10) is formed.
그 다음, 도2d에 도시한 바와 같이 상기 다결정실리콘의 식각으로 노출된 절연층(6)을 제거하여 그 하부의 산화막(3)의 전면을 노출시킨다.Next, as shown in FIG. 2D, the insulating layer 6 exposed by etching of the polysilicon is removed to expose the entire surface of the oxide film 3 below.
이와 같은 과정으로, 상기 주변회로영역(20)에 형성된 모스 트랜지스터의 게이트 측면부에 다결정실리콘이 잔존할 여지는 없으며, 이에 따라 이후의 공정에서 다결정실리콘 잔류물에 의한 쇼트발생을 방지할 수 있게 된다.In this manner, polysilicon does not remain in the gate side portion of the MOS transistor formed in the peripheral circuit region 20, thereby preventing a short circuit caused by polysilicon residues in a subsequent process.
상기한 바와 같이 본 발명은 플러그 형성을 목적으로 하는 다결정실리콘을 증착하기 이전에 주변회로영역의 상부에 절연층 패턴을 형성함으로써, 다결정실리콘의 식각후 주변회로영역에 형성된 게이트의 측면에 다결정실리콘이 잔존하는 것을 방지하여 반도체 메모리의 신뢰성 및 특성을 향상시키는 효과가 있다.As described above, the present invention forms an insulating layer pattern on the upper portion of the peripheral circuit region before depositing the polycrystalline silicon for the purpose of forming the plug, so that the polysilicon is formed on the side of the gate formed in the peripheral circuit region after etching the polycrystalline silicon. There is an effect of preventing the remaining, thereby improving the reliability and characteristics of the semiconductor memory.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100587596B1 (en) * | 2002-10-30 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method for forming plug in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100587596B1 (en) * | 2002-10-30 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method for forming plug in semiconductor device |
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