KR0140726B1 - Method of manufacture semiconductor device - Google Patents
Method of manufacture semiconductor deviceInfo
- Publication number
- KR0140726B1 KR0140726B1 KR1019940037489A KR19940037489A KR0140726B1 KR 0140726 B1 KR0140726 B1 KR 0140726B1 KR 1019940037489 A KR1019940037489 A KR 1019940037489A KR 19940037489 A KR19940037489 A KR 19940037489A KR 0140726 B1 KR0140726 B1 KR 0140726B1
- Authority
- KR
- South Korea
- Prior art keywords
- junction region
- impurity junction
- semiconductor device
- contact
- etching
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 소자분리절연막, 게이트전극 및 불순물 접합영역을 순차적으로 형성하고 콘택마스크를 이용한 식각공정으로 상기 불순물 접합영역의 일정두께까지 식각한 다음, 식각공정시 손상되지 않는 상기 식각된 불순물 접합영역의 측벽을 이용하여 도전층을 콘택함으로써 반도체소자의 콘택저항을 감소시켜 반도체소자의 고집적화를 가능하게 하고 반도체소자의 신뢰성을 향상시키는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, and sequentially forming a device isolation insulating film, a gate electrode, and an impurity junction region on an upper surface of the semiconductor substrate, and etching to a predetermined thickness of the impurity junction region by an etching process using a contact mask. By contacting the conductive layer using the sidewalls of the etched impurity junction region which are not damaged during the etching process, the contact resistance of the semiconductor device is reduced, thereby enabling high integration of the semiconductor device and improving the reliability of the semiconductor device.
Description
제 1a도는 내지 제 1d도는 본 발명의 실시예에 따른 반도체소자 제조공정을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 반도체기판 13 : 소자분리산화막11: semiconductor substrate 13: device isolation oxide film
15 : 게이트전극 17 : 불순물 접합영역15 gate electrode 17 impurity junction region
19 : 산화막 스페이서 21 : 하부절연층19 oxide film spacer 21 lower insulating layer
23 : 감광막패턴 25 : 콘택홀23: photoresist pattern 25: contact hole
27 : 다결정실리콘막27: polycrystalline silicon film
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체기판에 불순물 접합영역을 노출시키는 콘택홀 형성시 상기 불순물 접합영역을 식각하여 상기 식각된 불순물 접합영역의 측벽을 이용하여 도전층을 형성함으로써 반도체소자의 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, when forming a contact hole exposing an impurity junction region on a semiconductor substrate, the semiconductor substrate is formed by etching the impurity junction region to form a conductive layer using sidewalls of the etched impurity junction region. It relates to a technique for improving the reliability of the device.
반도체소자의 고집적화됨에 따라 반도체기판의 작은 손상도 반도체소자의 제조공정에 많은 문제점을 제공하게 된다.As the semiconductor devices are highly integrated, even small damages to the semiconductor substrates provide many problems in the manufacturing process of the semiconductor devices.
종래기술에서는 반도체기판 상부에 소자분리절연막과 게이트전극을 형성하고 게이트전극과 소자분리절연막을 마스크로하여 불순물 접합영역을 형성한 다음, 상기 게이트전극의 측벽에 절연막 스페이서를 형성하고 상부구조를 평탄화시키는 하부절연층을 형성한 다음, 콘택마스크를 이용한 식각공정으로 상기 불순물 접합영역을 노출시키는 콘택홀을 형성하고 이에 접속되는 도전층을 형성한다.In the prior art, an isolation layer and a gate electrode are formed on a semiconductor substrate, and an impurity junction region is formed using the gate electrode and the isolation layer as a mask, and then insulating layer spacers are formed on the sidewalls of the gate electrode to planarize the upper structure. After forming the lower insulating layer, a contact hole exposing the impurity junction region is formed by an etching process using a contact mask, and a conductive layer connected thereto is formed.
그러나, 상기 콘택홀 식각공정시 상가 반도체기판의 불순물 접합영역이 손상을 입는다. 또는, 이물질이 반도체기판 표면에 증착되어 콘택홀을 통하여 접속되는 전도물질과의 접속을 방해한다. 그로인하여, 반도체소자의 콘택저항이 증가되어 콘택하기가 어렵고 형성후에서 반도체소자의 신뢰성을 저하시키는 문제점이 있다.However, the impurity junction region of the additional semiconductor substrate is damaged during the contact hole etching process. Alternatively, foreign matter is deposited on the surface of the semiconductor substrate to interfere with the connection with the conductive material connected through the contact hole. As a result, the contact resistance of the semiconductor element is increased, making it difficult to contact and deteriorating the reliability of the semiconductor element after formation.
따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여, 콘택홀 식각 공정시 반도체기판의 불순물 접합영역을 일정두께 식각하여 노출되는 상기 불순물 접합영역의 측벽을 이용하여 전도물질의 형성함으로써 콘택저항을 낮추고 반도체소자의 신뢰성을 형상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the contact resistance is reduced by forming a conductive material using sidewalls of the impurity junction region exposed by etching a predetermined thickness of the impurity junction region of the semiconductor substrate during the contact hole etching process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that shapes the reliability of the semiconductor device.
이상의 목적을 달성하기위한 본 발명의 특징은, 반도체기판 상부에 소자분리절연막, 게이트전극 및 불순물 접합영역을 순차적으로 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 상기 불순물 접합영역을 노출시키는 공정과, 계속적으로 상기 노출된 불순물 접합영역을 일정두께 이방성식각함으로써 콘택홀을 형성하는 공정과, 상기 식각된 불순물 접합영역에 도전층을 콘택시키는 공정을 포함하는 반도체소자의 제조방법에 있어서, 상기 도전층 콘택공정은 상기 식각된 불순물 접합영역의 측벽을 이용하여 실시되는 것과, 상기 도전층 콘택공정은 상기 식각된 불순물 접합영역의 측벽을 이용하여 실시함으로써 식각공정으로 발생되는 잔유물을 제거하지않는 것이다.Features of the present invention for achieving the above object is a step of sequentially forming a device isolation insulating film, a gate electrode and an impurity junction region on the semiconductor substrate, and exposing the impurity junction region by an etching process using a contact mask; And subsequently forming a contact hole by continuously anisotropically etching the exposed impurity junction region and contacting the conductive layer with the etched impurity junction region. The contact process is performed by using the sidewalls of the etched impurity junction region, and the conductive layer contact process is performed by using the sidewalls of the etched impurity junction region so as not to remove residues generated by the etching process.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 제조공정을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.
제1a도를 참조하면, 반도체기판(11) 상부에 소자분리산화막(13), 게이트전극(15), 불순물 접합영역(17) 및 산화막 스페이서를 순차적으로 형성한다. 이때, 상기 불순물 접합영역(17)은 상기 게이트전극(15)과 소자분리산화막(13)을 마스크로하여 불순물을 주입하는 이온주입공정으로 형성한 것이다. 그 다음에, 상기 게이트전극(15)의 측벽에 산화막 스페이서(19)를 형성한다. 그리고, 상부구조를 평탄화시키는 하부절연층(21)을 형성한다. 그리고, 상기 하부절연층(21) 상부에 감광막패턴(23)을 형성한다. 이때, 상기 감광막패턴(23)은 콘택마스크(도시안됨)을 이용한 식각공정으로 형성된 것이다.Referring to FIG. 1A, an isolation layer 13, a gate electrode 15, an impurity junction region 17, and an oxide spacer may be sequentially formed on the semiconductor substrate 11. In this case, the impurity junction region 17 is formed by an ion implantation process in which impurities are implanted using the gate electrode 15 and the device isolation oxide film 13 as a mask. Next, an oxide spacer 19 is formed on the sidewall of the gate electrode 15. A lower insulating layer 21 is formed to planarize the upper structure. The photoresist pattern 23 is formed on the lower insulating layer 21. In this case, the photoresist pattern 23 is formed by an etching process using a contact mask (not shown).
제1b도를 참조하면, 상기 감광막패턴(23)을 마스크로하여 상기 반도체기판(11)에 형성된 불순물 접합영역(17)이 노출되도록 과도식각한다. 이때, 상기 노출된 불순물 접합영역(17)은 과도식각으로 인하여 일부 손상된 상태이다.Referring to FIG. 1B, the photoresist pattern 23 is overetched to expose the impurity junction region 17 formed on the semiconductor substrate 11. In this case, the exposed impurity junction region 17 is partially damaged due to excessive etching.
제1c도를 참조하면, 제1b도의 공정후에 계속적으로 상기 불순물 접합영역(17)을 일정두께 이방성식각함으로써 콘택홀(25)을 형성한다. 이때, 상기 이방성식각공정은 상기 콘택홀(25)의 하부에 불순물 접합영역(17)이 남아있도록 실시된 것이다. 여기서, 상기 식각된 불순물 접합영역(17)의 저부는 콘택공정시 어느정도 손상된 상태이고, 측벽은 손상되지않은 상태이다. 그리고 후공정에서 상기 식각된 불순물 접합영역(17)의 측벽을 이용하여 콘택을 실시함으로써 상기 식각공정으로 인한 잔유물을 제거하지 않아도 된다.Referring to FIG. 1C, the contact hole 25 is formed by continuously anisotropically etching the impurity junction region 17 after the process of FIG. 1B. In this case, the anisotropic etching process is performed so that the impurity junction region 17 remains in the lower portion of the contact hole 25. Here, the bottom portion of the etched impurity junction region 17 is somewhat damaged during the contact process, and the sidewall is not damaged. In addition, by performing contact by using the sidewall of the etched impurity junction region 17 in a later step, it is not necessary to remove the residues caused by the etch process.
제1d도를 참조하면, 상기 불순물 접합영역(17)에 콘택되는 다결정실리콘막(27)을 형성한다. 이때, 상기 콘택공정은 상기 손상된 불순물 접합영역(17)의 저부도 콘택면적으로 사용될 수 있어 종래보다 증가된 콘택면적을 갖는다. 그로인하여 콘택저항이 감소된다. 그리고, 손상되지않은 상기 불순물 접합영역(17)과 콘택됨으로써 신뢰성을 향상시킨다.Referring to FIG. 1D, a polysilicon film 27 contacting the impurity junction region 17 is formed. At this time, in the contact process, the bottom of the damaged impurity junction region 17 may also be used as the contact area, resulting in an increased contact area than before. As a result, the contact resistance is reduced. In addition, contact with the impurity junction region 17 which is not damaged improves reliability.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은 반도체기판 상부에 소자분리절연막, 게이트적극 및 불순물 접합영역을 순차적으로 형성하고 콘택마스크를 이용한 식각공정으로 상기 불순물 접합영역을 노출시킨 다음, 계속적으로 이방성식각하여 상기 불순물 접합영역을 일정두께 식각함으로써 콘택면적을 증가시키고 손상되지않은 불순물 접합영역의 식각면을 이용하여 도전층을 콘택시킴으로써 반도체소자의 고집적화와 신뢰성 향상을 가능하게 하는 잇점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a device isolation insulating film, a gate active region, and an impurity junction region are sequentially formed on a semiconductor substrate, and the impurity junction region is exposed by an etching process using a contact mask. By continuously anisotropic etching, the impurity junction region is etched to a certain thickness to increase the contact area and to contact the conductive layer by using the etching surface of the intact impurity junction region, thereby increasing the integration and reliability of the semiconductor device. .
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037489A KR0140726B1 (en) | 1994-12-27 | 1994-12-27 | Method of manufacture semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037489A KR0140726B1 (en) | 1994-12-27 | 1994-12-27 | Method of manufacture semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026180A KR960026180A (en) | 1996-07-22 |
| KR0140726B1 true KR0140726B1 (en) | 1998-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019940037489A KR0140726B1 (en) | 1994-12-27 | 1994-12-27 | Method of manufacture semiconductor device |
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| Country | Link |
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| KR (1) | KR0140726B1 (en) |
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1994
- 1994-12-27 KR KR1019940037489A patent/KR0140726B1/en not_active IP Right Cessation
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| KR960026180A (en) | 1996-07-22 |
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