KR20050010272A - Method of forming self align silicide in semiconductor device - Google Patents
Method of forming self align silicide in semiconductor device Download PDFInfo
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- KR20050010272A KR20050010272A KR1020030049318A KR20030049318A KR20050010272A KR 20050010272 A KR20050010272 A KR 20050010272A KR 1020030049318 A KR1020030049318 A KR 1020030049318A KR 20030049318 A KR20030049318 A KR 20030049318A KR 20050010272 A KR20050010272 A KR 20050010272A
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- salicide
- silicide
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 230000000903 blocking effect Effects 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 샐리사이드 형성방법에 관한 것으로, 더욱 상세하게는 도전층 상부에 선택적으로 형성되는 샐리사이드(self align silicide) 형성방법에 관한 것이다.The present invention relates to a method of forming a salicide of a semiconductor device, and more particularly, to a method of forming a salicide (self align silicide) selectively formed on the conductive layer.
반도체 소자가 고집적화 되어감에 따라 게이트의 길이는 0.18㎛이하로 줄어 들게 되고, 이에 따라 소자의 채널저항이 줄어들어 상대적으로 기생저항 성분의 기여도가 커지게 되므로, 전체 저항 중에서 기생저항의 중요도가 커지게 된다. 따라서, 고속도를 요하는 로직 소자에서 게이트의 게이트와 소스/드레인 영역의 저항과 접촉저항을 낮추기 위한 샐리사이드(self aligned silicide) 기술이 필수적이다.As semiconductor devices are highly integrated, the gate length is reduced to 0.18 µm or less, and thus the channel resistance of the device is reduced, so that the contribution of parasitic resistance components becomes relatively large. do. Therefore, a self-aligned silicide technique is required to lower the resistance and contact resistance of the gate and source / drain regions of the gate in logic devices requiring high speed.
한편, 반도체 소자 제조시 IO(input/output)영역과 같이 높은 저항특성을 요구하는 영역이 존재하게 되는 데, 이 같은 영역을 블로킹하여 특정지역에 실리사이드막의 형성을 막도록 하는 샐리사이드 블로킹(blocking)공정이 진행된다.Meanwhile, when semiconductor devices are manufactured, there are regions requiring high resistance characteristics, such as IO (input / output) regions, which block such regions to prevent the formation of silicide films in specific regions. The process proceeds.
샐리사이드 공정의 진행은, 샐리사이드 형성전 게이트전극패턴 및 소스/드레인 영역 등이 형성된 결과물 전면에 절연막을 형성하고, 패턴형성공정을 통해 샐리사이드 블로킹지역의 절연막만 남기고, 샐리사이드 형성영역의 절연막은 제거한 후, 실리사이드막을 형성함으로써, 선택적 샐리사이드공정을 완료한다.The salicide process is performed by forming an insulating film on the entire surface of the gate electrode pattern and the source / drain region formed before forming the salicide, and leaving only the insulating film in the salicide blocking region through the pattern forming process, and insulating film in the salicide forming region. After removing silver, a silicide film is formed to complete the selective salicide process.
그러나 상기 절연막의 제거를 위한 식각 공정시 건식식각공정을 사용하게 되는 데, 이는 게이트전극 패턴 상부에 식각손상 및 잔류물 등의 불량을 발생하게 하여, 소자의 저항특성을 열화시키는 문제점이 있다.However, in the etching process for removing the insulating layer, a dry etching process is used, which causes defects such as etching damage and residues on the gate electrode pattern, thereby deteriorating resistance characteristics of the device.
상술한 문제점을 해결하기 위한 본 발명의 목적은 선택적 샐리사이드공정의형성 공정시 발생하는 소자의 저항특성 열화를 방지할 수 있도록 하는 반도체소자의 샐리사이드 형성방법을 제공함에 있다.An object of the present invention for solving the above problems is to provide a method for forming a salicide of a semiconductor device to prevent the deterioration of the resistance characteristics of the device generated during the formation of the selective salicide process.
도 1 내지 도 3은 본 발명의 바람직한 실시예인 반도체소자의 샐리사이드 형성방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to an exemplary embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10; 반도체기판 12; 소자분리막10; Semiconductor substrate 12; Device Separator
14: 게이트산화막 16: 게이트도전층14: gate oxide layer 16: gate conductive layer
20: LDD영역 22: 스페이서20: LDD region 22: spacer
24: 소스/드레인영역 26: 제2 질화막24: source / drain region 26: second nitride film
28: SOG 산화막 30: 실리사이드막28: SOG oxide film 30: silicide film
상술한 목적을 달성하기 위한 본 발명의 사상은 샐리사이드 형성영역과 샐리사이드 블로킹영역이 구분 정의된 반도체기판에 소자분리막, 게이트전극패턴 및 소스/드레인영역을 형성하는 단계, 상기 결과물 전면에 제1 절연막을 형성하는 단계,상기 샐리사이드 형성영역의 소자분리막 및 샐리사이드 블로킹영역이 노출되도록 포토레지스트 패턴을 형성하는 단계, 상기 포토레지스트 패턴이 형성된 영역을 제외한 영역에 제2 절연막을 형성하고, 상기 포토레지스트 패턴을 제거하는 단계, 상기 결과물에서 노출된 제1 절연막을 제거하는 단계 및 상기 제1 절연막이 제거된 영역에 실리사이드막을 형성하는 단계를 포함한다.According to an aspect of the present invention, a device isolation layer, a gate electrode pattern, and a source / drain region are formed on a semiconductor substrate in which a salicide forming region and a salicide blocking region are defined. Forming an insulating layer, forming a photoresist pattern to expose the device isolation layer and the salicide blocking region of the salicide forming region, forming a second insulating layer in a region other than the region where the photoresist pattern is formed, and forming the photoresist layer Removing the resist pattern, removing the first insulating film exposed from the resultant, and forming a silicide film in a region where the first insulating film is removed.
상기 제1 절연막은 질화막으로 형성하는 것이 바람직하다.The first insulating film is preferably formed of a nitride film.
상기 제2 절연막은 SOG(spin on glass)산화막으로 형성하는 것이 바람직하다.The second insulating layer is preferably formed of a spin on glass (SOG) oxide film.
상기 제1 절연막의 제거는 인산(H3PO4)을 이용한 습식식각공정을 통해 수행하는 것이 바람직하다.The removal of the first insulating layer is preferably performed by a wet etching process using phosphoric acid (H 3 PO 4 ).
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 따라서, 도면에서의 막의 두께 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, although the embodiments of the present invention may be modified in many different forms, the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the thickness of the film and the like in the drawings are exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings mean the same elements. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1 내지 도 3은 본 발명의 바람직한 실시예인 반도체소자의 샐리사이드 형성방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to an exemplary embodiment of the present invention.
도 1을 참조하면, 반도체기판(10)상에 게이트 산화막(14), 게이트 도전층(16)을 순차적으로 형성한 후, 상기 게이트도전층(16)의 소정영역에 포토레지스트 패턴을 형성하고 이를 식각마스크로 식각공정을 수행하여 게이트 전극 패턴(G)을 형성한다. 한편, 반도체기판(10)은 게이트 전극 패턴 영역(a)과 이 게이트 전극 패턴 영역 간에 형성되는 소자분리영역인 소자분리막(b)으로 구분 정의된다.Referring to FIG. 1, after the gate oxide layer 14 and the gate conductive layer 16 are sequentially formed on the semiconductor substrate 10, a photoresist pattern is formed in a predetermined region of the gate conductive layer 16. An etching process is performed using an etching mask to form a gate electrode pattern G. On the other hand, the semiconductor substrate 10 is divided into a gate electrode pattern region (a) and an isolation layer (b) which is an element isolation region formed between the gate electrode pattern region.
이 게이트 전극 패턴(G)을 이온주입마스크로 이온주입공정을 수행하여 LDD영역(20)을 형성한다. 이 게이트 전극 패턴(G) 전면에 제1 질화막을 형성한 후 이를 에치백하여 게이트 전극 패턴(G) 측벽에 스페이서(22)를 형성한다.The gate electrode pattern G is subjected to an ion implantation process using an ion implantation mask to form the LDD region 20. The first nitride layer is formed on the entire surface of the gate electrode pattern G and then etched back to form a spacer 22 on the sidewall of the gate electrode pattern G.
이 스페이서(22) 및 게이트 전극 패턴(G)을 이온주입마스크로 이온주입공정을 수행하여 소스/드레인영역(24)을 형성한다.An ion implantation process is performed on the spacer 22 and the gate electrode pattern G using an ion implantation mask to form a source / drain region 24.
소스 드레인 영역(24)의 형성이 완료된 결과물의 전면에 제2 질화막(26)을 형성한다.The second nitride film 26 is formed on the entire surface of the resultant product in which the source drain region 24 is formed.
이 제2 질화막(26)은 이후 형성될 콘택형성 식각시 식각정지막으로써 사용되기 때문에 이를 감안하여 증착두께를 형성한다.Since the second nitride layer 26 is used as an etch stop layer during subsequent contact formation etching, the second nitride layer 26 forms a deposition thickness in consideration of this.
이 제2 질화막(26)을 증착한 후 샐리사이드 형성을 방지해야 하는 샐리사이드 블로킹영역(A)과 샐리사이드 형성영역(B)의 소자분리막(b) 상부가 노출되도록 포토레지스트 패턴(PR)을 형성한다.After the deposition of the second nitride layer 26, the photoresist pattern PR is exposed to expose the upper portion of the isolation layer (b) of the salicide blocking region (A) and the salicide formation region (B) which should prevent the formation of salicide. Form.
도 2를 참조하면, 포토레지스트 패턴(PR)이 노출된 영역에 SOG(spin on glass)코팅을 진행하여 샐리사이드 블로킹영역(A)과 샐리사이드 형성영역(B)의 소자분리막(b) 상부에 SOG산화막(28)을 형성하고, CMP 공정과 같은 평탄화공정을 수행하여 SOG산화막(28)을 평탄화시킨다.Referring to FIG. 2, a spin on glass (SOG) coating is performed on a region where the photoresist pattern PR is exposed, and is formed on the isolation layer (b) of the salicide blocking region (A) and the salicide forming region (B). The SOG oxide film 28 is formed, and the SOG oxide film 28 is planarized by performing a planarization process such as a CMP process.
이 평탄화된 SOG산화막(28)과, 샐리사이드 블로킹영역(A)과 샐리사이드 형성영역(B)의 소자분리막 영역(b) 이외의 영역에 형성된 포토레지스트 패턴(PR)의 높이가 같아지도록 에치백공정을 수행한다.The flattened SOG oxide film 28 and the etch back so that the height of the photoresist pattern PR formed in the region other than the element isolation film region b of the salicide blocking region A and the salicide forming region B are equal. Perform the process.
이때, 에치백 공정은 SOG산화막(28)과 포토레지스트 패턴의 식각선택비가 낮은 CF4가스를 이용하여 포토레지스트 패턴이 노출되도록 SOG산화막(28)을 에치백한다. 이어서, 노출된 포토레지스트 패턴(PR)을 산소플라즈마공정을 통해 제거되도록 하는 스트립공정을 수행한다.At this time, the etch back process etches back the SOG oxide layer 28 so that the photoresist pattern is exposed using CF4 gas having a low etching selectivity between the SOG oxide layer 28 and the photoresist pattern. Subsequently, a strip process is performed to remove the exposed photoresist pattern PR through an oxygen plasma process.
따라서 제거된 포토레지스트 패턴(PR)에 의해 샐리사이드 형성영역(B)은 노출되고, 샐리사이드 블로킹영역(A)과 샐리사이드 형성영역(B)의 소자분리막(b) 상부에는 SOG 산화막(28)이 형성된 상태가 된다.Accordingly, the salicide forming region B is exposed by the removed photoresist pattern PR, and the SOG oxide layer 28 is disposed on the isolation layer b of the salicide blocking region A and the salicide forming region B. This is a formed state.
도 3을 참조하면, 이 결과물에 인산(H3PO4)을 이용한 습식식각공정을 이용하여 노출된 샐리사이드 형성영역(B)의 제2 질화막(26)을 제거하고, SOG 산화막(28)이 형성된 영역에는 제2 질화막(26)을 제거하지 않고 잔존한다. 제2 질화막(26)이 제거된 샐리사이드 형성영역(A)에는 즉, 게이트전극패턴(G) 상부, LDD 영역(20) 상부에 실리사이드막(30)을 형성하게 된다.Referring to FIG. 3, the second nitride layer 26 of the salicide forming region B is removed by the wet etching process using phosphoric acid (H 3 PO 4 ), and the SOG oxide layer 28 is removed. The formed region remains without removing the second nitride film 26. The silicide layer 30 is formed on the salicide forming region A from which the second nitride layer 26 is removed, that is, on the gate electrode pattern G and on the LDD region 20.
또한, 샐리사이드 블로킹영역(A)에 콘택홀 형성을 위한 식각 공정시 상기 잔존한 제2 질화막(26)은 식각정지막으로써 역할을 수행하여 하부에 형성된 소자분리막(b) 및 실리사이드막(30)의 손상을 방지할 수 있게 된다.In addition, during the etching process for forming the contact hole in the salicide blocking region A, the remaining second nitride layer 26 serves as an etch stop layer to form a lower portion of the device isolation layer (b) and the silicide layer (30). It is possible to prevent the damage.
본 발명에 의하면, 샐리사이드 형성 공정시 샐리사이드 블로킹영역의 질화막 상부에 SOG 산화막을 형성하고, 샐리사이드 형성영역의 질화막을 습식식각으로 제거함으로써, 선택적 샐리사이드 형성 공정시 발생하는 게이트전극패턴 상부의 불량을 방지할 수 있다.According to the present invention, an SOG oxide film is formed on the nitride film of the salicide blocking region during the salicide forming process, and the nitride film of the salicide forming region is removed by wet etching, thereby forming an upper portion of the gate electrode pattern generated during the selective salicide forming process. Defects can be prevented.
이상에서 살펴본 바와 같이 본 발명에 의하면, 샐리사이드 형성 공정시 샐리사이드 블로킹영역의 질화막 상부에 SOG 산화막을 형성하고, 샐리사이드 형성영역의 질화막을 습식식각으로 제거함으로써, 선택적 샐리사이드 형성 공정시 발생하는게이트전극패턴 상부의 불량을 방지할 수 있어, 소자 특성 열화를 방지할 수 있는 효과가 있다.As described above, according to the present invention, the SOG oxide film is formed on the nitride film of the salicide blocking region during the salicide forming process, and the nitride film of the salicide forming region is removed by wet etching, thereby generating the selective salicide forming process. Defects on the upper portion of the gate electrode pattern can be prevented, and thus deterioration of device characteristics can be prevented.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
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| KR100774830B1 (en) * | 2006-07-14 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Patterning method of nonsalicidation region for semiconductor manufacturing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100774830B1 (en) * | 2006-07-14 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Patterning method of nonsalicidation region for semiconductor manufacturing |
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