KR20030058634A - Manufacturing method for semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve an insulation characteristic by preventing an active region of a semiconductor substrate from being damaged by an etch process for forming a contact hole and by preventing a loss of an insulation layer in the vicinity of a gate electrode. CONSTITUTION: A predetermined thickness of an insulation layer is formed on a semiconductor substrate(101) including a conductive interconnection on which a mask insulation layer pattern(109) is stacked. The insulation layer is blanket-etched to form an insulation layer spacer(113) on the sidewall of the conductive interconnection while a contact region of the substrate is exposed. A predetermined thickness of a selective silicon growth layer is grown on the contact region to form the first contact plug(115). An interlayer dielectric(117) having a contact hole exposing the first contact plug is formed on the resultant structure. A selective silicon growth layer is grown on the first contact plug exposed to the contact hole to form the second contact plug(119). The second contact plug and the interlayer dielectric are removed through a chemical mechanical polishing(CMP) process to form a contact plug composed of the second contact plug and the first contact plug wherein the mask insulation layer pattern is used as a polishing barrier in the CMP process.

Description

Manufacturing method for semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by forming a contact plug in two steps using a selective silicon growth film to prevent damage to the active region and to prevent loss of the insulating film around the gate electrode. The present invention relates to a method of manufacturing a semiconductor device for improving the insulation characteristics and process margins of the device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

First, an element isolation insulating film 13 defining an active region is formed on the semiconductor substrate 11.

Next, a stacked structure of a gate insulating film (not shown), a gate electrode conductive layer (not shown), and a mask insulating film (not shown) is formed on the semiconductor substrate 11. In this case, the mask insulating film is formed of a nitride film or an oxide film.

Next, the stack structure is etched using the gate electrode mask as an etch mask to form a mask insulating film pattern 19, a gate electrode 17, and a gate insulating film pattern 15.

Next, an insulating film (not shown) is formed on the entire surface to have a predetermined thickness. In this case, the insulating film may be formed of a nitride film or an oxide film.

Next, the interlayer insulating film 22 is formed on the insulating film, and then planarized.

Next, a photoresist pattern 23 is formed on the interlayer insulating layer 22 to expose portions of the bit line contact and the storage electrode contact.

Next, the interlayer insulating layer 22 and the insulating layer are etched using the photoresist pattern 23 as an etch mask to form a contact hole 25 and an insulating layer spacer 21. (See Figure 1)

Thereafter, a polysilicon layer is formed, and a poly etch (not shown) is formed by performing a front etching process or a chemical mechanical polishing process.

However, in the method of manufacturing a semiconductor device according to the prior art as described above, a nitride film or an oxide film is used as the insulating film spacer formed on the sidewalls of the mask insulating film and the gate electrode, and the thickness of the mask insulating film and the insulating film spacer is constant for insulating the devices. It should be secured over thickness. In the case of using the nitride film, loss of the nitride film should be prevented by using a condition having a high selectivity with respect to the nitride film during the etching process of the interlayer insulating film. In addition, when the oxide film is used, the dielectric constant is relatively smaller than that of the nitride film, and thus the device has a high operating speed due to the reduction of parasitic capacitance. However, the etching selectivity is similar to that of the interlayer insulating film. Since it does not act as a barrier, there is a problem in that processing margins are reduced, such as a dishing phenomenon or severe exposure of the gate electrode.

In order to solve the above problems of the prior art, a gate electrode is formed, a selective silicon growth film is formed to a predetermined thickness to form a first contact plug, an interlayer insulating film is formed, and a bit line contact and a storage electrode contact. The interlayer insulating layer is etched using a contact mask that exposes a predetermined portion to form a contact hole for exposing the first contact plug, and then a selective silicon growth layer is formed on the first contact plug to form a second contact plug. It is an object of the present invention to provide a method of manufacturing a semiconductor device which prevents the active region of the semiconductor substrate from being damaged by the etching process for forming the contact hole and prevents the insulating film around the gate electrode from being lost.

1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11, 101, 201: semiconductor substrate 13, 103: device isolation insulating film

15, 105: gate insulating film pattern 17, 107: gate electrode

19, 109, 207: mask insulating film patterns 21, 113, 211: insulating film spacer

23: photoresist pattern 25: contact hole

111, 209 insulating film 114 first contact hole

115: first contact plug 117: interlayer insulating film

118: second contact hole 119: second contact plug

201: first interlayer insulating film 203: contact plug

205: bit line 213: first storage electrode contact hole

215: first storage electrode contact plug 217: second interlayer insulating film

219: second storage electrode contact hole 221: second storage electrode contact plug

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming an insulating film having a predetermined thickness on the semiconductor substrate on which the conductive wiring on which the mask insulating film pattern is stacked is formed;

Etching the entire insulating film to form insulating film spacers on the sidewalls of the conductive wiring and exposing the contact region of the semiconductor substrate;

Forming a first contact plug by growing a selective silicon growth film in a predetermined thickness in the contact region;

Forming an interlayer insulating film having a contact hole exposing the first contact plug on an entire surface thereof;

Forming a second contact plug by growing a selective silicon growth layer on the first contact plug exposed to the contact hole;

The second contact plug and the interlayer insulating film are removed by a chemical mechanical polishing process to form a contact plug including the second contact plug and the first contact plug, wherein the chemical mechanical polishing process uses the mask insulating film pattern as an abrasive barrier. The process to perform,

The semiconductor substrate is a single crystal silicon layer,

The semiconductor substrate is an SOI substrate,

The conductive wiring is a gate electrode or a bit line;

The insulating film is formed of an oxide film or a nitride film,

The insulating film is formed to a thickness of 50 ~ 500Å,

The first contact plug may be formed by growing a selective silicon growth film to a thickness of 50 to 5000 Pa at a temperature of 300 to 1200 ° C.

Hereinafter, with reference to the accompanying drawings will be described in detail.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

First, an isolation layer 103 is formed on the semiconductor substrate 101 to define an active region.

Next, a stacked structure of a gate insulating film (not shown), a gate electrode conductive layer (not shown), and a mask insulating film (not shown) is formed on the semiconductor substrate 101. In this case, the mask insulating film is formed of a nitride film or an oxide film.

Next, the stack structure is etched using the gate electrode mask as an etch mask to form a mask insulating film pattern 109, a gate electrode 107, and a gate insulating film pattern 105.

Next, an insulating film 111 is formed on the entire surface to have a predetermined thickness. At this time, the insulating film 111 is formed to a thickness of 50 ~ 500Å by using an oxide film or a nitride film. (See Figure 2A)

Subsequently, the insulating layer 111 is entirely etched to form insulating layer spacers 113 on sidewalls of the mask insulating layer pattern 109, the gate electrode 107, and the gate insulating layer pattern 105. The first contact hole 114 exposing the contact region of the film is formed. (See Figure 2b)

Next, the first contact plug 115 is formed by growing a selective silicon growth layer on the bottom of the first contact hole 114 by a predetermined thickness. At this time, the selective silicon growth film is grown to a thickness of 50 to 5000 Pa at a temperature of 300 to 1200 ℃. (See Figure 2c)

Next, an interlayer insulating film 117 is formed over the entire surface. (See FIG. 2D)

Next, a second contact hole 118 exposing the first contact plug 115 is formed by etching the interlayer insulating layer 117 by using a contact mask that exposes a contact region as an etch mask. (See Figure 2E)

Next, an optional silicon growth layer is grown on the first contact plug 115 exposed to the second contact hole 118 to form a second contact plug 119. In this case, the second contact plug 119 is formed at a height similar to that of the interlayer insulating layer 117. (See Figure 2f)

Next, the interlayer insulating layer 117 and the second contact plug 119 are removed by a CMP process to form a contact plug including the second contact plug 119 and the first contact plug 115. In this case, the CMP process is performed using the mask insulating film pattern 109 as the polishing barrier. (See Figure 2g)

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention and illustrate a method of manufacturing a storage electrode contact plug after bit lines are formed.

First, a first interlayer insulating film 202 having a contact plug 203 connected to a portion intended as a bit line contact and a storage electrode contact on an upper portion of a semiconductor substrate 201 including lower structures such as an isolation layer and a gate electrode. ).

Next, a bit line 205 is formed to be connected to a portion of the contact plug 203, which is supposed to be a bit line contact. In this case, a mask insulating film pattern 207 is stacked on the bit line 205.

Next, an insulating film 209 is formed over the entire surface. At this time, the insulating film 209 is formed to a thickness of 50 ~ 500Å by using an oxide film or a nitride film. (See Figure 3A)

Next, the insulating layer 209 is entirely etched to form insulating layer spacers 211 on sidewalls of the bit line 205 and the mask insulating layer pattern 207, and at the same time, the insulating layer 209 is formed as a storage electrode contact among the contact plugs 203. A first storage electrode contact hole 213 exposing the portion is formed.

Next, an optional silicon growth layer is grown on the contact plug 203 exposed to the first storage electrode contact hole 213 to form a first storage electrode contact plug 215. At this time, the selective silicon growth film is grown to a thickness of 50 to 5000 Pa at a temperature of 300 to 1200 ℃.

Next, a second interlayer insulating film 217 is formed over the entire surface. (See FIG. 3D)

Next, the second storage electrode contact hole exposing the first storage electrode contact plug 215 by etching the second interlayer insulating layer 217 using the storage electrode contact mask that exposes a predetermined portion of the storage electrode contact as an etch mask. 219 is formed. (See Figure 3E)

Next, an optional silicon growth layer is grown on the first storage electrode contact plug 215 exposed through the second storage electrode contact hole 219 to form a second storage electrode contact plug 221. In this case, the selective silicon growth layer is grown at a height similar to that of the second interlayer insulating layer 217. (See Figure 3f)

Next, the second storage electrode contact plug 221 and the second interlayer insulating layer 217 are removed by the CMP process, and the storage electrode including the second storage electrode contact plug 221 and the first storage electrode contact plug 215 is formed. A contact plug is formed. In this case, the CMP process is performed using the mask insulating film pattern 207 as a polishing barrier. (See Figure 3g)

Meanwhile, the method of manufacturing a semiconductor device according to the present invention may be applied on an SOI substrate formed of a stacked structure of an upper silicon substrate / oxide film / lower silicon substrate. This has advantages such as high speed due to small junction capacitance, low voltage due to low threshold voltage, and elimination of latch-up due to perfect device isolation, compared to devices formed on semiconductor substrates formed of single crystal silicon layers.

In addition, the SOI substrate may be a separation by implantation of oxygen (SIMOX) SOI substrate, an ELTRAN SOI substrate, or a bonded SOI substrate.

The SOI substrate is formed with a thickness of 500 to 2500 GPa of an upper silicon substrate and 500 to 4000 GPa of an oxide film.

A fully depleted (FD) SOI device or a partially depleted (PD) SOI device is implemented in the SOI structure.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a first contact plug is formed by forming a gate electrode, and forming a selective silicon growth film having a predetermined thickness in a portion of the cell region, which is defined as a bit line contact and a storage electrode contact. Form an interlayer insulating film over the entire surface, and expose the first contact plug by etching the interlayer insulating film with an etch mask using a contact mask that exposes portions intended for bit line contacts and storage electrode contacts. By forming a selective silicon growth layer on the first contact plug to form a second contact plug, an etching process for forming a contact hole is prevented from damaging the active region of the semiconductor substrate and preventing loss of the insulating film around the gate electrode. There is an advantage of improving the insulation properties.

Claims (7)

Forming an insulating film having a predetermined thickness on the semiconductor substrate on which the conductive wiring on which the mask insulating film pattern is stacked is formed; Etching the entire insulating film to form insulating film spacers on the sidewalls of the conductive wiring and exposing the contact region of the semiconductor substrate; Forming a first contact plug by growing a selective silicon growth film in a predetermined thickness in the contact region; Forming an interlayer insulating film having a contact hole exposing the first contact plug on an entire surface thereof; Forming a second contact plug by growing a selective silicon growth layer on the first contact plug exposed to the contact hole; The second contact plug and the interlayer insulating film are removed by a chemical mechanical polishing process to form a contact plug including the second contact plug and the first contact plug, wherein the chemical mechanical polishing process uses the mask insulating film pattern as an abrasive barrier. A semiconductor device manufacturing method comprising the step of performing. The method of claim 1, The semiconductor substrate is a manufacturing method of a semiconductor device, characterized in that the single crystal silicon layer. The method of claim 1, The semiconductor substrate is a manufacturing method of a semiconductor device, characterized in that the SOI substrate. The method of claim 1, And the conductive wiring is a gate electrode or a bit line. The method of claim 1, And the insulating film is formed of an oxide film or a nitride film. The method of claim 1, The insulating film is a method of manufacturing a semiconductor device, characterized in that formed in 50 ~ 500Å thickness. The method of claim 1, The first contact plug is a semiconductor device manufacturing method, characterized in that formed by growing a selective silicon growth film to a thickness of 50 ~ 5000Å at a temperature of 300 ~ 1200 ℃.