KR20040060218A - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR20040060218A KR20040060218A KR1020020086760A KR20020086760A KR20040060218A KR 20040060218 A KR20040060218 A KR 20040060218A KR 1020020086760 A KR1020020086760 A KR 1020020086760A KR 20020086760 A KR20020086760 A KR 20020086760A KR 20040060218 A KR20040060218 A KR 20040060218A
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- insulating film
- forming
- cell region
- bit line
- mask
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/823475—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 전하저장전극 콘택 형성 공정시의 주변회로영역에서의 비트라인 손상을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving process yield and device operation reliability by preventing bit line damage in peripheral circuit areas during a charge storage electrode contact forming process. In providing.
반도체소자의 고집적화에 따라 0.2㎛ 이하의 디자인 룰을 가지는 소자에서는 라인/스페이스 패턴 보다 공정 마진이 작은 전하저장전극 콘택 형성 공정에서 산화막과 질화막의 식각선택비차를 이용하는 자기정렬콘택(self-align contact; 이하SAC라 칭함)을 사용하게 된다. 이러한 SAC 공정도 초기에는 홀 패턴으로 형성하였으나, 소자가 고집적화되어 미세화 됨에 따라 마스크 정렬 마진이 감소되어 라인 패턴 콘택 기술이 도입되었다.In the device having a design rule of 0.2 μm or less due to the high integration of semiconductor devices, a self-aligned contact using an etching selectivity difference between an oxide film and a nitride film in a charge storage electrode contact forming process having a smaller process margin than a line / space pattern; Hereinafter referred to as SAC). The SAC process was also initially formed in a hole pattern, but as the device is highly integrated and miniaturized, the mask alignment margin is reduced to introduce a line pattern contact technology.
도 1은 종래 기술에 따른 반도체소자의 단면도로서, 셀영역(S)과 주변회로영역(P)으로 나누어 도시하였다.1 is a cross-sectional view of a semiconductor device according to the prior art, which is divided into a cell region S and a peripheral circuit region P. Referring to FIG.
먼저, 반도체기판(10)상에 소자분리산화막과 게이트전극등의 소저의 하부 구조물들을 형성하고, 상기 구조의 전표면에 층간절연막(12)을 형성한다. 이때 주변회로영역(P)이 셀영역(S) 보다 높게 단차가 지게된다.First, underlying structures such as a device isolation oxide film and a gate electrode are formed on the semiconductor substrate 10, and the interlayer insulating film 12 is formed on the entire surface of the structure. At this time, the peripheral circuit area P becomes higher than the cell area S.
그다음 상기 층간절연막(12)상에 마스크절연막(15) 패턴과 중첩되어있는 비트라인(14)을 형성하고, 그 절연을 위하여 측벽에 절연막 스페이서(16)를 형성한다.Next, a bit line 14 overlapping the mask insulating film 15 pattern is formed on the interlayer insulating film 12, and an insulating film spacer 16 is formed on the sidewall for insulation.
그후 상기 비트라인(14) 양측의 노출되어있는 층간절연막(12)을 라인 콘택 패턴 기술의 SAC 공정으로 제거하여 전하저장전극용 콘택홀(18)을 형성하고, 상기 구조의 전표면에 콘택플러그가 되는 다결정실리콘층(20)을 도포한다.After that, the exposed interlayer insulating film 12 on both sides of the bit line 14 is removed by a SAC process using a line contact pattern technology to form a contact hole 18 for a charge storage electrode, and a contact plug is formed on the entire surface of the structure. The polysilicon layer 20 is applied.
그다음 상기 다결정실리콘층(20)을 화학-기계적 연마등의 방법으로 전면 식각하여 셀영역의 마스크 절연막(15) 패턴을 노출시키면 다결정실리콘층(20) 패턴으로된 전하저장전극 콘택플러그를 형성한다.Then, the polysilicon layer 20 is etched entirely by chemical mechanical polishing or the like to expose the mask insulating layer 15 pattern of the cell region to form a charge storage electrode contact plug having the polysilicon layer 20 pattern.
상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 전하저장전극 콘택플러그 형성을 위한 다결정실리콘층의 전면 식각 공정에서 주변회로영역과 셀영역 간의 단차에 의해 주변회로영역의 비트라인이 노출되어 손상되는 문제점이 있다.In the method of manufacturing a semiconductor device according to the related art as described above, a bit line of a peripheral circuit region is exposed and damaged by a step between the peripheral circuit region and the cell region in the entire surface etching process of the polysilicon layer for forming the charge storage electrode contact plug. There is a problem.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은The present invention is to solve the above problems, the object of the present invention is
셀영역의 비트라인 상부에 중첩되어있는 마스크절연막 패턴의 상부에 주변회로영역과의 단차 만큼의 두께로지지 절연막을 형성하고, 후속 SAC 공정을 진행하여 주변회로영역의 비트라인 손상을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.A process insulating film is formed on the mask insulating film pattern superimposed on the bit line of the cell region to the thickness of the peripheral circuit region, and the subsequent SAC process is performed to prevent bit line damage of the peripheral circuit region. And it provides a method for manufacturing a semiconductor device that can improve the reliability of device operation.
도 1은 종래 기술에 따른 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2a 및 도 2b는 본 발명에 따른 반도체소자의 제조공정도.2a and 2b is a manufacturing process diagram of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 반도체기판 12 : 층간절연막10 semiconductor substrate 12 interlayer insulating film
14 : 비트라인 15 : 마스크절연막14 bit line 15 mask insulating film
16 : 절연막 스페이서 18 : 전하저장전극 콘택 홀16 insulating film spacer 18 charge storage electrode contact hole
20 : 다결정실리콘층 30 : 지지절연막20 polycrystalline silicon layer 30 support insulating film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
셀영역과 주변회로영역을 구비하는 반도체기판 상에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the semiconductor substrate having a cell region and a peripheral circuit region;
상기 층간절연막상에 마스크절연막 패턴과 중첩되어있는 비트라인을 형성하는 공정과,Forming a bit line overlapping the mask insulating film pattern on the interlayer insulating film;
상기 마스크절연막 패턴들중 셀영역에 있는 부분상에 지지절연막 패턴을 형성하되, 셀영역과 주변회로영역간의 단차 크기로 형성하는 공정과,Forming a supporting insulating film pattern on a portion of the mask insulating film patterns in a cell region, wherein the supporting insulating film pattern is formed to have a step size between the cell region and a peripheral circuit region;
상기 셀영역의 지지절연막 패턴과 마스크절연막 패턴 및 비트라인의 측벽에 절연막 스페이서를 형성하되, 주변회로영역의 비트라인과 마스크절연막 패턴의 측벽에도 형성하는 공정과,Forming an insulating spacer on the sidewalls of the support insulating film pattern, the mask insulating film pattern and the bit line of the cell region, and forming the insulating spacers on the sidewalls of the bit line and the mask insulating film pattern of the peripheral circuit region;
상기 층간절연막을 전하저장전극 콘택 마스크를 이용한 선택 식각 공정으로 전하저장전극 콘택홀을 형성하는 공정과,Forming a charge storage electrode contact hole in the interlayer insulating layer by a selective etching process using a charge storage electrode contact mask;
상기 콘택홀을 메우는 콘택플러그를 형성하는 공정을 구비함에 있다.And forming a contact plug to fill the contact hole.
또한 본 발명의 다른 특징은, 상기 지지절연막을 질화산화막으로 형성함에 있다.Further, another feature of the present invention is that the support insulating film is formed of a nitride oxide film.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명에 따른 반도체소자의 제조공정도이다.2A and 2B are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 도 1에서의 공정과 같이 주변회로영역(P)과 셀영역(S)으로 구분되는 실리콘 웨이퍼 등의 반도체기판(10)상에 소자분리산화막과 게이트전극등의 하부 구조물을 형성하고, 상기 구조의 전표면에 층간절연막(12)을 형성한다.First, as shown in FIG. 1, a lower structure such as an isolation layer and a gate electrode is formed on a semiconductor substrate 10 such as a silicon wafer, which is divided into a peripheral circuit region P and a cell region S. An interlayer insulating film 12 is formed on the entire surface of the structure.
그다음 상기 주변회로영역(P)과 셀영역(S)의 층간절연막(12)상에 질화막이나 산화막등 절연 재질의 마스크절연막(15) 패턴과 중첩되어있는 비트라인(14)을 형성한 후, 상기 셀영역(S)의 마스크절연막(15) 패턴의 상부에만 선택적으로 지지절연막(30)을 형성하되, 상기 주변회로영역(P)과 셀영역(S)간의 단차 크기와 같은 두께로 형성하며, 단차피복성이 떨어지는 질화막 산화막으로 형성한다. 여기서 상기 지지절연막(30)은 오버행을 가지고 형성되는데, 의도하지 않은 부분인 셀영역(S)의 다른 부분에도 일부 두께가 형성될 수 있어 이를 제거하는 식각 공정을 CH3가스로 실시하게 되는데 이때 오버행도 함께 제거된다. 이러한 식각 공정은 실시하지 않을 수도 있다.Next, after forming the bit line 14 on the interlayer insulating film 12 of the peripheral circuit region P and the cell region S, the bit line 14 overlapping the mask insulating film 15 pattern of an insulating material such as a nitride film or an oxide film is formed. The support insulating film 30 is selectively formed only on the mask insulating film 15 pattern of the cell region S, and is formed to have the same thickness as the step size between the peripheral circuit region P and the cell region S. A nitride film oxide film having poor coating properties is formed. In this case, the support insulating layer 30 is formed with an overhang, and some thicknesses may be formed in other portions of the cell region S, which are not intended, and an etching process for removing them is performed using CH 3 gas. Also removed together. This etching process may not be performed.
그후 상기 지지절연막(30)과 마스크절연막(15) 패턴 및 비트라인(14)의 측벽에 산화막이나 질화막등의 절연막 스페이서(16)를 형성하고, 상기 비트라인(14) 양측의 노출되어있는 층간절연막(12)을 라인 콘택 패턴 기술의 SAC 공정으로 콘택 마스크를 이용하여 선택식각하여 전하저장전극용 콘택홀(18)을 형성한다. (도 2a 참조).After that, an insulating spacer 16 such as an oxide film or a nitride film is formed on the sidewalls of the support insulating film 30, the mask insulating film 15, and the bit line 14, and the interlayer insulating film exposed on both sides of the bit line 14 is formed. (12) is selectively etched using a contact mask in a SAC process of line contact pattern technology to form a contact hole 18 for a charge storage electrode. (See FIG. 2A).
그다음 상기 구조의 전표면에 콘택플러그가 되는 다결정실리콘층(20)을 도포한 후, 상기 다결정실리콘층(20)을 화학-기계적 연마등의 방법으로 전면 식각하여 콘택플러그를 형성하면 셀영역(S)의 지지절연막(30)이 노출되며, 주변회로영역(P)에서는 마스크절연막(15) 패턴이 노출되며, 비트라인(14)은 손상되지 않는다. (도 2b 참조).Then, after applying the polysilicon layer 20 to be a contact plug on the entire surface of the structure, the polysilicon layer 20 is etched entirely by chemical-mechanical polishing or the like to form a contact plug. ) Is exposed, the pattern of the mask insulating film 15 is exposed in the peripheral circuit region (P), and the bit line 14 is not damaged. (See FIG. 2B).
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은, 비트라인의 상부에 전하저장전극을 형성하는 메모리 소자의 SAC 공정에서 셀영역의 마스크절연막 패턴 상부에만 주변회로영역과의 단차 높이 크기로 지지절연막을 형성하고, 후속 전하저장전극 콘택플러그 형성 공정을 진행하였으므로, 콘택플러그 형성을 위한 전면 식각 공정시 주변회로영역의 비트라인이 노출되어 손상되는 방지할 수 있어 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the height difference between the peripheral circuit region and only the mask insulation layer pattern of the cell region is only increased in the SAC process of the memory device forming the charge storage electrode on the bit line. Since the support insulating film was formed and the subsequent charge storage electrode contact plug forming process was performed, the bit line of the peripheral circuit area was prevented from being exposed and damaged during the front surface etching process for forming the contact plug, thereby improving process yield and device operation reliability. There is an advantage to improve.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020086760A KR20040060218A (en) | 2002-12-30 | 2002-12-30 | Method for fabricating of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020086760A KR20040060218A (en) | 2002-12-30 | 2002-12-30 | Method for fabricating of semiconductor device |
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| KR20040060218A true KR20040060218A (en) | 2004-07-06 |
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| KR (1) | KR20040060218A (en) |
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