KR100444312B1 - Method for forming fine contact of semiconductor device using insulating spacer - Google Patents

Method for forming fine contact of semiconductor device using insulating spacer Download PDF

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KR100444312B1
KR100444312B1 KR1019970026851A KR19970026851A KR100444312B1 KR 100444312 B1 KR100444312 B1 KR 100444312B1 KR 1019970026851 A KR1019970026851 A KR 1019970026851A KR 19970026851 A KR19970026851 A KR 19970026851A KR 100444312 B1 KR100444312 B1 KR 100444312B1
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forming
layer
etching
conductive layer
insulating film
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금동렬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a fine contact of a semiconductor device is provided to improve isolation property between adjacent conductive layers and to prevent damage of a junction region by forming an insulating spacer at inner walls of a groove. CONSTITUTION: An interlayer dielectric(17) and a conductive layer(8) are sequentially stacked on a substrate(1) having gate electrodes. A planarized insulating layer(10) and an etch barrier layer are sequentially formed on the resultant structure. A groove is formed to expose the conductive layer by etching the etch barrier layer and the planarized insulating layer. The exposed conductive layer is etched by isotropic etching, thereby exposing the interlayer dielectric. An insulating spacer(12) is formed at inner walls of the groove. Then, a contact hole is formed to expose the substrate.

Description

반도체소자의 미세콘택 형성방법Microcontact Formation Method of Semiconductor Device

본 발명은 반도체소자의 미세콘택 형성방법에 관한 것으로, 특히 셀 크기가 작은 고집적화된 반도체소자의 콘택공정을 용이하게 실시할 수 있는 반도체소자의 미세콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a micro contact of a semiconductor device, and more particularly, to a method for forming a micro contact of a semiconductor device which can easily perform a contact process of a highly integrated semiconductor device having a small cell size.

일반적으로, 메모리 소자에서 중요한 특성인 리프레쉬 타임 ( refresh time )은 주로 저장전극 노드와 트랜지스터의 드레인을 연결하는 저장전극 콘택공정시 상기 드레인이 손상되어 발생되는 누설전류에 의하여 결정된다.In general, a refresh time, which is an important characteristic of a memory device, is mainly determined by a leakage current generated by damaging the drain during a storage electrode contact process connecting the storage electrode node and the drain of the transistor.

현재 사용되고 있는 노광기술로는 16 M DRAM 까지 콘택홀을 형성할 때 콘택홀 측벽의 도전층과 절연불량이 발생하지 않고 소자를 형성할 수 있으나, 소자가 고집적화됨에 따라 단위셀의 크기가 축소되고, 그에 따라서 콘택홀과 도전층의 간격이 좁아지게 된다.In the current exposure technology, when forming a contact hole up to 16 M DRAM, a device can be formed without a poor insulation with the conductive layer of the sidewall of the contact hole. However, as the device is highly integrated, the unit cell size is reduced. As a result, the gap between the contact hole and the conductive layer is narrowed.

상기한 바와 같이 콘택홀과 주변 도전층과의 좁은 거리로 인한 절연특성의 열화를 방지하기 위하여, 콘택홀의 크기를 축소시켜야 하였다.As described above, in order to prevent deterioration of insulation characteristics due to a narrow distance between the contact hole and the peripheral conductive layer, the size of the contact hole should be reduced.

상기 콘택홀 크기의 축소를 위하여, 노광방식을 바꾸거나 마스크를 바꾸어서 실시하였다.In order to reduce the size of the contact hole, an exposure method or a mask was changed.

그러나, 상기 콘택홀의 축소는 콘택홀의 단차를 증가시켜 콘택 영역의 절연막을 식각하는 경우 저부에 위치하는 하부구조물이 과도식각될 수밖에 없어 그에 따른 반도체소자의 누설전류가 증가되며 그로 인한 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.However, the shrinkage of the contact hole increases the level of the contact hole, so that when the insulating layer of the contact region is etched, the underlying structure located at the bottom is inevitably overetched, thereby increasing the leakage current of the semiconductor device, thereby increasing the characteristics of the semiconductor device. There is a problem that the reliability is lowered.

본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 콘택 식각 공정시높은 면비 ( aspect ratio ) 에 따른 하부구조물의 과도식각으로 누설전류 특성이 열화되는 현상을 방지할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 미세콘택 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the prior art, it is possible to prevent the phenomenon of the leakage current characteristics deterioration due to the transient etching of the substructure according to the high aspect ratio during the contact etching process characteristics of the semiconductor device and It is an object of the present invention to provide a method for forming a micro contact of a semiconductor device capable of improving reliability.

도 1a 내지 도 1e 는 본 발명의 제1실시예에 따른 반도체소자의 미세콘택 형성방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method for forming a micro contact of a semiconductor device according to a first embodiment of the present invention.

도 2a 내지 도 2e 는 본 발명의 제2실시예에 따른 반도체소자의 미세콘택 형성방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method for forming a micro contact of a semiconductor device according to a second embodiment of the present invention.

＜ 도면의 주요부분에 대한 부호의 설명 ＞<Explanation of symbols for the main parts of the drawings>

1 : 반도체기판 2 : 소자분리절연막1: semiconductor substrate 2: device isolation insulating film

3 : 게이트산화막 4 : 게이트전극3: gate oxide film 4: gate electrode

5 : 마스크산화막 6 : 불순물 접합영역5: mask oxide film 6: impurity junction region

7 : 질화막 스페이서 8 : 다결정실리콘막7 nitride film spacer 8 polysilicon film

9,19 : 감광막패턴 10 : 평탄화절연막9,19 photosensitive film pattern 10 planarization insulating film

11 : 식각장벽층 12 : 절연막 스페이서11 etch barrier layer 12 insulating film spacer

13,A : 홈 B : 언더컷13, A: home B: undercut

17 : 층간절연막 30,50 : 콘택홀17: interlayer insulating film 30, 50: contact hole

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 미세콘택 형성방법은,In order to achieve the above object, the method for forming a micro contact of a semiconductor device according to the present invention,

게이트전극이 형성된 반도체기판의 전체표면상부에 일정두께의 층간절연막 및 도전층을 적층하는 공정과,Stacking an interlayer insulating film and a conductive layer with a predetermined thickness on the entire surface of the semiconductor substrate on which the gate electrode is formed;

반도체기판 상에 평탄화절연막과 식각장벽층의 적층구조를 형성하는 공정과,Forming a stacked structure of a planarization insulating film and an etching barrier layer on the semiconductor substrate;

콘택마스크를 이용한 사진식각공정으로 상기 식각장벽층과 평탄화절연막을 식각하여 상기 도전층을 노출시키는 홈을 형성하는 공정과,Forming a groove exposing the conductive layer by etching the etch barrier layer and the planarization insulating layer by a photolithography process using a contact mask;

상기 노출된 도전층을 등방성식각하여 상기 층간절연막을 노출시키는 공정과,Isotropically etching the exposed conductive layer to expose the interlayer insulating film;

상기 홈의 측벽에 절연막 스페이서를 형성하는 식각공정으로 상기 반도체기판을 노출시키는 콘택홀을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a contact hole exposing the semiconductor substrate by an etching process of forming an insulating film spacer on the sidewall of the groove.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d 는 본 발명의 제1실시예에 따른 반도체소자의 미세콘택 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method for forming a micro contact of a semiconductor device according to a first embodiment of the present invention.

도 1a를 참조하면, 반도체기판(1) 상부에 소자분리절연막(2)을 형성하다.Referring to FIG. 1A, a device isolation insulating film 2 is formed on the semiconductor substrate 1.

상기 반도체기판(1)과의 계면에 게이트산화막(3)이 개재되고, 상측에 마스크산화막(5)이 형성되는 게이트전극(4)을 형성한다.A gate electrode 4 having a gate oxide film 3 interposed at an interface with the semiconductor substrate 1 and a mask oxide film 5 formed thereon is formed.

상기 게이트전극(4)의 측벽에 질화막 스페이서(7)가 형성되고, 그 하측의 활성영역에 불순물 접합영역(6)이 형성된 트랜지스터를 형성한다.A nitride film spacer 7 is formed on the sidewall of the gate electrode 4, and a transistor in which an impurity junction region 6 is formed in the lower active region is formed.

그 다음에, 상기 반도체기판(1)의 전체표면상부에 층간절연막(17)을 형성하고, 그 상부에 다결정실리콘막(8)을 형성한다.Next, an interlayer insulating film 17 is formed over the entire surface of the semiconductor substrate 1, and a polysilicon film 8 is formed thereon.

도 1b를 참조하면, 전체표면상부에 감광막(미도시)을 도포하고 플레이트전극 마스크(도시안됨)를 이용한 노광 및 현상공정으로 상기 반도체기판(1)의 셀부에만 감광막패턴(9)을 형성한다. 그리고, 상기 감광막패턴을 마스크로하여 상기 반도체기판(1)의 주변회로부에 형성된 상기 다결정실리콘막(8)을 식각한다.Referring to FIG. 1B, a photosensitive film (not shown) is coated on the entire surface, and the photosensitive film pattern 9 is formed only in the cell portion of the semiconductor substrate 1 by an exposure and development process using a plate electrode mask (not shown). The polysilicon film 8 formed on the peripheral circuit portion of the semiconductor substrate 1 is etched using the photosensitive film pattern as a mask.

도 1c 참조하면, 상기 감광막패턴(9)을 제거하고, 전체표면상부에 평탄화절연막(10)을 형성한 다음, 그 상부에 식각장벽층(11)을 형성한다.Referring to FIG. 1C, the photoresist pattern 9 is removed, a planarization insulating film 10 is formed on the entire surface, and an etch barrier layer 11 is formed thereon.

그리고, 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 식각장벽층(11) 및 평탄화절연막(10)을 식각하고, 연속적으로 노출되는 다결정실리콘막(8)을 식각하여 상기 층간절연막(17)을 노출시킨다. 이때, 상기 다결정실리콘막(8)은 상기 사진식각공정시 높은 단차로 인하여 수반되는 과도식각으로 하부구조물이 식각되는 것을 방지하는 완충역할을 한다.The etch barrier layer 11 and the planarization insulating film 10 are etched by a photolithography process using a contact mask (not shown), and the polysilicon film 8 which is continuously exposed is etched to etch the interlayer insulating film 17. Expose In this case, the polysilicon film 8 serves as a buffer to prevent the lower structure from being etched due to the excessive etching accompanying the high step in the photolithography process.

이때, 상기 다결정실리콘막(8)의 식각공정은 등방성으로 실시하되, 상기 평탄화절연막(10)의 하부로 "B"와 같이 언더컷 ( under cut ) 이 형성되는 "A" 와 같은 홈을 형성한다.In this case, the etching process of the polysilicon film 8 is isotropically formed, but a groove such as "A" is formed in the lower portion of the planarization insulating film 10 such that an undercut is formed, such as "B".

도 1d를 참조하면, 전체표면상부에 홈의 측벽에 절연막 스페이서(12)를 형성하는 동시에 상기 반도체기판(1)을 노출시키는 콘택홀(30)을 형성한다.Referring to FIG. 1D, the insulating layer spacer 12 is formed on the sidewall of the groove on the entire surface of the groove, and the contact hole 30 exposing the semiconductor substrate 1 is formed.

이때, 상기 절연막 스페이서(12)는 전체표면상부에 절연막을 일정두께 증착하고 이를 이방성식각하여 형성한 것이다.At this time, the insulating film spacer 12 is formed by depositing a predetermined thickness on the entire surface and anisotropically etching it.

상기 이방성식각공정은 저부에 증착된 절연막을 완전히 제거하기 위하여 실시되는 과도식각공정으로 상기 층간절연막(17)을 식각함으로써 상기 반도체기판(1)의 불순물 접합영역(6)을 노출시키는 콘택홀(30)을 형성한다.The anisotropic etching process is a transient etching process performed to completely remove the insulating film deposited on the bottom. The contact hole 30 exposing the impurity junction region 6 of the semiconductor substrate 1 by etching the interlayer insulating film 17. ).

도 2a 내지 도 2e 는 본 발명의 제2실시예에 따른 반도체소자의 미세콘택 형성방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method for forming a micro contact of a semiconductor device according to a second embodiment of the present invention.

도 2a를 참조하면, 반도체기판(1) 상부에 소자분리절연막(2)을 형성하고, 상기 반도체기판(1)과의 계면에 게이트산화막(3)이 개재되고 상측에 마스크산화막(5)이 형성된 게이트전극(4)을 형성한다.Referring to FIG. 2A, a device isolation insulating film 2 is formed on the semiconductor substrate 1, a gate oxide film 3 is interposed at an interface with the semiconductor substrate 1, and a mask oxide film 5 is formed on the semiconductor substrate 1. The gate electrode 4 is formed.

상기 게이트전극(4)의 측벽에 질화막 스페이서(7) 및 불순물 접합영역(6)이 형성된 트랜지스터를 형성한다.A transistor having a nitride spacer 7 and an impurity junction region 6 is formed on sidewalls of the gate electrode 4.

그 다음에, 상기 반도체기판(1)의 전체표면상부에 층간절연막(17)을 형성한다.Next, an interlayer insulating film 17 is formed over the entire surface of the semiconductor substrate 1.

도 2b를 참조하면, 그리고, 전체표면상부에 다결정실리콘막(8)을 형성하고, 그 상부에 감광막패턴(19)을 형성한다. 이때, 상기 감광막패턴(19)은 콘택홀을 형성하는 콘택마스크보다 크게 형성된 것으로, 저장전극마스크나 비트라인마스크를 이용하여 형성할 수도 있다.Referring to FIG. 2B, a polysilicon film 8 is formed on the entire surface, and a photosensitive film pattern 19 is formed thereon. In this case, the photoresist pattern 19 is formed larger than the contact mask for forming the contact hole, and may be formed using a storage electrode mask or a bit line mask.

도 2c를 참조하면, 상기 감광막패턴(19)을 마스크로 상기 다결정실리콘막(8)을 식각하여 상기 다결정실리콘막(8)으로 형성된 콘택패드를 형성하고, 상기 감광막패턴(19)을 제거한다.Referring to FIG. 2C, the polysilicon film 8 is etched using the photoresist pattern 19 as a mask to form a contact pad formed of the polysilicon film 8, and the photoresist pattern 19 is removed.

도 2d를 참조하면, 전체표면상부에 평탄화절연막(10)을 형성하고, 그 상부에 식각장벽층(11)을 형성한다.Referring to FIG. 2D, a planarization insulating film 10 is formed on the entire surface, and an etch barrier layer 11 is formed thereon.

그리고, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 식각장벽층(11)과 평탄화절연막(10)을 식각하여 상기 콘택패드를 노출시키는 홈(13)을 형성한다.In addition, the etching barrier layer 11 and the planarization insulating layer 10 are etched by an etching process using a contact mask (not shown) to form grooves 13 exposing the contact pads.

도 2e를 참조하면, 상기 홈(13) 저부의 다결정실리콘막(8)을 등방성식각방법으로 식각하여 상기 도 1c 와 같이 언더컷을 형성한다.Referring to FIG. 2E, the polysilicon film 8 at the bottom of the groove 13 is etched by an isotropic etching method to form an undercut as shown in FIG. 1C.

그리고, 상기 홈(13) 측벽에 절연막 스페이서(12)를 형성하는 동시에 상기 반도체기판(1)의 불순물 접합영역(6)을 노출시키는 콘택홀(50)을 형성한다.The insulating layer spacer 12 is formed on the sidewall of the groove 13, and the contact hole 50 exposing the impurity junction region 6 of the semiconductor substrate 1 is formed.

이상에서 설명한 바와 같이 종래기술에 따른 반도체소자의 미세콘택 형성방법은, 종래의 노광장치를 이용하여 단위셀의 크기가 축소된 콘택홀을 형성하되, 이웃한 도전층과의 절연특성을 향상시키며, 콘택식각공정시 소오스/드레인 불순물 접합영역이 손상을 방지하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method for forming a micro contact of a semiconductor device according to the prior art forms a contact hole having a reduced size of a unit cell using a conventional exposure apparatus, and improves insulation characteristics with neighboring conductive layers. The source / drain impurity junction region is prevented from being damaged during the contact etching process, thereby improving the characteristics and reliability of the semiconductor device.

Claims (3)

게이트전극이 형성된 반도체기판의 전체표면상부에 일정두께의 층간 절연막 및 도전층을 적층하는 공정과,Stacking an interlayer insulating film and a conductive layer having a predetermined thickness on the entire surface of the semiconductor substrate on which the gate electrode is formed; 반도체기판 상에 평탄화절연막과 식각장벽층의 적층구조를 형성하는 공정과,Forming a stacked structure of a planarization insulating film and an etching barrier layer on the semiconductor substrate; 콘택마스크를 이용한 사진식각공정으로 상기 식각장벽층과 평탄화절연막을 식각하여 상기 도전층을 노출시키는 홈을 형성하는 공정과,Forming a groove exposing the conductive layer by etching the etch barrier layer and the planarization insulating layer by a photolithography process using a contact mask; 상기 노출된 도전층을 등방성식각하여 상기 층간절연막을 노출시키는 공정과,Isotropically etching the exposed conductive layer to expose the interlayer insulating film; 상기 홈의 측벽에 절연막 스페이서를 형성하는 식각공정으로 상기 반도체기판을 노출시키는 콘택홀을 형성하는 공정을 포함하는 반도체소자의 미세콘택 형성방법.And forming a contact hole exposing the semiconductor substrate by an etching process of forming an insulating film spacer on the sidewall of the groove. 제 1 항에 있어서,The method of claim 1, 상기 도전층의 등방성 식각공정시 상기 평탄화절연막의 하부로 언더컷이 형성되는 것을 특징으로 하는 반도체소자의 미세콘택 형성방법.And forming an undercut under the planarization insulating layer during the isotropic etching process of the conductive layer. 제 1 항에 있어서,The method of claim 1, 상기 식각장벽층 및 평탄화절연막의 식각공정은 상기 도전층을 완충막으로 하여 실시하는 것을 특징으로 하는 반도체소자의 미세콘택 형성방법.And etching the etching barrier layer and the planarization insulating layer using the conductive layer as a buffer layer.
KR1019970026851A 1997-06-24 1997-06-24 Method for forming fine contact of semiconductor device using insulating spacer Expired - Fee Related KR100444312B1 (en)

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