KR100351915B1 - Method for fabricating of semiconductor memory device - Google Patents
Method for fabricating of semiconductor memory device Download PDFInfo
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- KR100351915B1 KR100351915B1 KR1020000078517A KR20000078517A KR100351915B1 KR 100351915 B1 KR100351915 B1 KR 100351915B1 KR 1020000078517 A KR1020000078517 A KR 1020000078517A KR 20000078517 A KR20000078517 A KR 20000078517A KR 100351915 B1 KR100351915 B1 KR 100351915B1
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- forming
- landing plug
- front surface
- insulating layer
- metal contact
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 29
- 239000002184 metal Substances 0.000 claims abstract description 43
- 230000002093 peripheral effect Effects 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 150000004767 nitrides Chemical class 0.000 description 9
- 239000000758 substrate Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 주변 회로 영역에 더미 랜딩 패드를 형성하여 주변 회로의 디싱(Dishing) 문제 및 셀 영역과의 단차를 줄일 수 있도록한 반도체 메모리 소자의 제조 방법에 관한 것으로, 셀 영역과 주변 회로 영역에 트랜지스터들을 형성하고 전면에 제 1 절연층을 형성하고 랜딩 플러그 콘택 영역을 형성하는 단계;전면에 랜딩 플러그 형성용 물질층을 증착하고 평탄화하여 셀 영역의 랜딩 플러그와 주변 회로 영역의 더미 랜딩 플러그를 형성하는 단계;전면에 제 2 절연층을 형성하고 트랜지스터의 일측 랜딩 플러그에 콘택되는 비트 라인 콘택 패드 및 비트 라인을 형성하는 단계;전면에 제 3,4, 절연층을 형성하고 트랜지스터의 타측의 랜딩 플러그에 콘택되는 상부 플러그를 형성하고 전면에 제 5 절연층을 형성하는 단계;상기 상부 플러그가 노출되도록 커패시터 형성 영역을 정의하고 하부 전극, 유전층, 상부 전극을 형성하는 단계;전면에 제 6 절연층을 형성하고 제 1 메탈 콘택 마스크를 이용하여 더미 랜딩 플러그가 제거되도록 주변 회로 영역의 메탈 콘택홀들을 형성하는 단계;전면에 제 2 메탈 콘택 마스크를 형성하고 이를 이용하여 셀 영역의 메탈 콘택홀들을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device in which a dummy landing pad is formed in a peripheral circuit region to reduce a dishing problem and a step difference with a cell region. Forming a first insulating layer on the front surface and forming a landing plug contact region; depositing and planarizing a material layer for forming a landing plug on the front surface to form a landing plug in a cell region and a dummy landing plug in a peripheral circuit region Forming a second insulating layer on the front surface and forming a bit line contact pad and a bit line contacting the landing plug on one side of the transistor; forming a third, fourth, insulating layer on the front surface and on the landing plug on the other side of the transistor Forming a contact upper plug and forming a fifth insulating layer on a front surface thereof; capping the upper plug to expose the upper plug; Defining a formation region and forming a lower electrode, a dielectric layer, and an upper electrode; forming a sixth insulating layer on the front surface and forming metal contact holes in the peripheral circuit region to remove the dummy landing plug using a first metal contact mask; Forming a second metal contact mask on the front surface and forming metal contact holes in the cell region using the second metal contact mask.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 주변 회로 영역에 더미 랜딩 패드를 형성하여 주변 회로의 디싱(Dishing) 문제 및 셀 영역과의 단차를 줄일 수 있도록한 반도체 메모리 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of manufacturing a semiconductor memory device in which a dummy landing pad is formed in a peripheral circuit region to reduce a dishing problem and a step with a cell region. .
일반적인 반도체 소자 제조공정에서 사용되고 있는 콘택홀 형성 방법은 크게 다이렉트 콘택(direct contact) 형성 방법과 자기 정합을 이용한 콘택(self align contact;SAC) 형성 방법이 있다.The contact hole forming method used in the general semiconductor device manufacturing process includes a direct contact forming method and a self aligning contact (SAC) forming method using self-alignment.
다이렉트 콘택 형성 방법은 절연막 상에 콘택홀 형성을 위한 감광막 패턴을 사진공정으로 형성한 후, 이를 마스크로 하여 절연막을 식각하는 방법이고, SAC 방법은 감광막 패턴 형성없이 임의 구조물에 자기정합되도록 콘택홀을 형성하는 방법이다.The direct contact forming method is a method of forming a photoresist pattern for forming a contact hole on an insulating film by a photo process, and then etching the insulating film using the mask as a mask. The SAC method forms a contact hole to self-align to an arbitrary structure without forming the photoresist pattern. How to form.
여기서, SAC 방법은 사진식각 공정이 요구되지 않으므로 작은 크기의 콘택홀을 용이하게 형성할 수 있다.In the SAC method, since a photolithography process is not required, a small contact hole can be easily formed.
그러나 SAC 방법으로 콘택홀을 형성할 경우에는 콘택홀의 크기가 너무 작기 때문에, 이 콘택홀을 통해 하부 구조물과 연결되어야 하는 도전층 패턴을 정확히 얼라인시키는 것이 어렵다.However, when the contact hole is formed by the SAC method, since the contact hole is too small in size, it is difficult to accurately align the conductive layer pattern to be connected to the lower structure through the contact hole.
따라서, SAC 방법으로 형성한 콘택홀에 랜딩 패드를 형성하여 이후에 형성될 도전층 패턴과의 접속을 용이하게 하는 방법이 많이 연구되고 있다.Therefore, a lot of researches have been conducted to form a landing pad in a contact hole formed by the SAC method to facilitate connection with a conductive layer pattern to be formed later.
종래 기술의 랜딩 패드 형성 공정에 있어서는 주변 회로 영역의 메탈 콘택의 베리어층으로 질화막을 사용한다.In the landing pad forming process of the prior art, a nitride film is used as the barrier layer of the metal contact in the peripheral circuit region.
질화막은 기판과의 계면에서 질화막 자체의 컴프레스 스트레스(compressstress)성질을 가지고 있으므로 많은 결함들을 발생시킬 수 있다.Since the nitride film has a compressive stress property of the nitride film itself at the interface with the substrate, many defects can be generated.
이와 같은 종래 기술의 반도체 메모리의 제조 공정에 있어서는 다음과 같은 문제가 있었다.In the manufacturing process of such a semiconductor memory of the prior art, there are the following problems.
주변 회로 영역의 메탈 콘택의 베리어층으로 질화막을 사용하기 때문에 질화막 자체의 컴프레스 스트레스에 의해 결함이 발생할 수 있다.Since the nitride film is used as the barrier layer of the metal contact in the peripheral circuit region, defects may occur due to the compression stress of the nitride film itself.
이는 소자의 특성을 저하시키고 디바이스의 오동작을 유발한다.This degrades the device characteristics and causes the device to malfunction.
또한, 베리어층으로 질화막만을 사용하기 때문에 셀 영역의 랜딩 플러그 형성을 위한 CMP 공정시에 주변 회로 영역의 디싱이 발생한다.In addition, since only the nitride film is used as the barrier layer, dishing of the peripheral circuit region occurs during the CMP process for forming the landing plug of the cell region.
그리고 셀 영역과 주변 회로 영역간의 스텝 커버리지가 충분히 확보되지 않아 후속되는 공정 진행시에 공정 마진 확보가 어렵고, 불량 유발 가능성을 높인다.In addition, since the step coverage between the cell region and the peripheral circuit region is not sufficiently secured, it is difficult to secure the process margin during the subsequent process progress and increase the possibility of defects.
이와 같은 종래 기술의 문제들은 결국 수율을 저하시키는 결정적인 원인으로 작용한다.These problems of the prior art eventually act as a decisive factor in lowering the yield.
본 발명은 이와 같은 종래 기술의 문제를 해결하기 위한 것으로, 주변 회로 영역에 더미 랜딩 패드를 형성하여 주변 회로의 디싱(Dishing) 문제 및 셀 영역과의 단차를 줄일 수 있도록한 반도체 메모리 소자의 제조 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention is to solve such a problem of the prior art, and a method of manufacturing a semiconductor memory device in which a dummy landing pad is formed in a peripheral circuit region to reduce a dishing problem of a peripheral circuit and a step with a cell region. The purpose is to provide.
도 1a내지 도 1g는 본 발명에 따른 반도체 소자의 형성을 위한 공정 단면도1A to 1G are cross-sectional views of a process for forming a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11. 반도체 기판 12. 소자 격리층11. Semiconductor substrate 12. Device isolation layer
13. 셀 트랜지스터13. Cell Transistor
14.20.22.23.27.28. 제 1,2,3,4,5,6 절연층14.20.22.23.27.28. 1,2,3,4,5,6 insulation layer
15. 랜딩 플러그 콘택 마스크층 16.17. 랜딩 플러그 콘택 영역15. Landing plug contact mask layer 16.17. Landing plug contact area
18. 랜딩 플러그 19. 더미 랜딩 플러그18. Landing plug 19. Dummy landing plug
21. 비트라인 콘택 패드 24. 하부 전극21. Bitline Contact Pad 24. Lower Electrode
25. 유전층 26. 상부 전극25. Dielectric layer 26. Upper electrode
29. 제 1 메탈 콘택 마스크 30.31.32.34. 메탈 콘택홀29. First metal contact mask 30.31.32.34. Metal contact hole
33. 제 2 메탈 콘택 마스크 35a. 메탈 베리어층33. Second metal contact mask 35a. Metal Barrier Layer
35b. 메탈 배선35b. Metal wiring
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 메모리 소자의 제조 방법은 셀 영역과 주변 회로 영역에 트랜지스터들을 형성하고 전면에 제 1 절연층을 형성하고 랜딩 플러그 콘택 영역을 형성하는 단계;전면에 랜딩 플러그 형성용 물질층을 증착하고 평탄화하여 셀 영역의 랜딩 플러그와 주변 회로 영역의 더미 랜딩 플러그를 형성하는 단계;전면에 제 2 절연층을 형성하고 트랜지스터의 일측 랜딩 플러그에 콘택되는 비트 라인 콘택 패드 및 비트 라인을 형성하는 단계;전면에 제 3,4, 절연층을 형성하고 트랜지스터의 타측의 랜딩 플러그에 콘택되는 상부 플러그를 형성하고 전면에 제 5 절연층을 형성하는 단계;상기 상부 플러그가 노출되도록 커패시터 형성 영역을 정의하고 하부 전극, 유전층, 상부 전극을 형성하는 단계;전면에 제 6 절연층을 형성하고 제 1 메탈 콘택 마스크를 이용하여 더미 랜딩 플러그가 제거되도록 주변 회로 영역의 메탈 콘택홀들을 형성하는 단계;전면에 제 2 메탈 콘택 마스크를 형성하고 이를 이용하여 셀 영역의 메탈 콘택홀들을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, including forming transistors in a cell region and a peripheral circuit region, forming a first insulating layer on a front surface, and forming a landing plug contact region; Depositing and planarizing a layer of plug forming material to form a landing plug in a cell region and a dummy landing plug in a peripheral circuit region; a bit line contact pad forming a second insulating layer on the front surface and contacting a landing plug on one side of the transistor; Forming a bit line; forming a third and fourth insulating layers on the front surface, forming an upper plug contacting the landing plug on the other side of the transistor, and forming a fifth insulating layer on the front surface; Defining a capacitor formation region and forming a lower electrode, a dielectric layer, and an upper electrode; a sixth insulating layer on the front side Forming and forming metal contact holes in the peripheral circuit region to remove the dummy landing plugs using the first metal contact mask; forming a second metal contact mask on the front surface and forming metal contact holes in the cell region using the first metal contact mask. Characterized in that comprises a step.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 메모리 소자의 제조 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1g는 본 발명에 따른 반도체 소자의 형성을 위한 공정 단면도이다.1A to 1G are cross-sectional views of a process for forming a semiconductor device according to the present invention.
본 발명은 기판의 표면에 질화막을 이용한 베리어층을 형성하지 않고 셀 영역과 동일한 공정으로 주변 회로 영역에 더미 랜딩 플러그를 형성하여 셀 영역의 랜딩 플러그 콘택을 위한 CMP 공정시에 주변 회로 영역의 디싱 현상을 억제하기 위한 것이다.According to the present invention, a dummy landing plug is formed in the peripheral circuit region in the same process as the cell region without forming a barrier layer using a nitride film on the surface of the substrate, and dishing of the peripheral circuit region is performed during the CMP process for landing plug contact of the cell region. It is to suppress.
이러한 더미 랜딩 플러그는 메탈 콘택홀 형성시에 제거되어 메탈 콘택층이기판에 직접 접촉되도록 하여 트랜지스터에 영향을 주지 않는다.Such a dummy landing plug is removed at the time of forming the metal contact hole to be in direct contact with the metal contact layer substrate, thereby not affecting the transistor.
먼저, 도 1a에서와 같이, 반도체 기판(11)의 소자 격리 영역에 소자 격리층(12)을 형성하여 활성 영역을 정의한다.First, as shown in FIG. 1A, the device isolation layer 12 is formed in the device isolation region of the semiconductor substrate 11 to define an active region.
그리고 셀 영역과 주변 회로 영역에 셀 트랜지스터(13)들을 형성하고 전면에 제 1 절연층(14)을 형성한다.Cell transistors 13 are formed in the cell region and the peripheral circuit region, and the first insulating layer 14 is formed on the entire surface.
여기서, 제 1 절연층(14)은 BPSG(Boron Phosphorus Silicate Glass),USG(Undoped Silicate Glass),PSG(Phoporus Silicate Glass),SOG(Spin On Glass),LPTEOS(Low Presure Tetra-Ethyl-Ortho-Silicate),PE(Plasma Enhanced)TEOS,HDP(High Density Plasma)등의 물질을 사용하고 필요하다면 CMP(Chemical Mechanical Polishing)공정으로 평탄화를 하여 형성한다.Here, the first insulating layer 14 may be formed of boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), hoprous silicate glass (PSG), spin on glass (SOG), low presure tetra-eth-yl-ortho-silicate (LPTEOS). ), PE (Plasma Enhanced) TEOS, HDP (High Density Plasma) and other materials are used, and if necessary, planarized by CMP (Chemical Mechanical Polishing) process.
이어, 도 1b에서와 같이, 제 1 절연층(14)상에 랜딩 플러그 콘택 마스크층(15)을 형성한후에 셀 영역과 주변 회로 영역 모두에 랜딩 플러그 콘택 영역(16)(17)을 형성한다.Subsequently, as shown in FIG. 1B, after the landing plug contact mask layer 15 is formed on the first insulating layer 14, the landing plug contact regions 16 and 17 are formed in both the cell region and the peripheral circuit region.
그리고 도 1c에서와 같이, 상기 랜딩 플러그 콘택 영역(16)(17)을 포함하는 전면에 랜딩 플러그 형성용 물질층을 증착하고 CMP 공정으로 평탄화하여 게이트 전극들을 경계로하여 격리되는 셀 영역의 랜딩 플러그(18)와 주변 회로 영역의 더미 랜딩 플러그(19)를 형성한다.As shown in FIG. 1C, a landing plug forming material layer is deposited on the entire surface including the landing plug contact regions 16 and 17 and planarized by a CMP process. 18 and the dummy landing plug 19 of the peripheral circuit area are formed.
이어, 셀 영역의 랜딩 플러그(18)와 주변 회로 영역의 더미 랜딩 플러그(19)를를 포함하는 전면에 제 2 절연층(20)을 형성한다.Next, a second insulating layer 20 is formed on the entire surface including the landing plug 18 in the cell region and the dummy landing plug 19 in the peripheral circuit region.
그리고 도 1d에서와 같이, 셀 트랜지스터의 일측 랜딩 플러그(18)에 콘택되는 비트 라인 콘택 패드(21) 및 비트 라인(도면에 도시되지 않음)을 형성한후 전면에 제 3,4, 절연층(22)(23)을 형성한다.As shown in FIG. 1D, after forming the bit line contact pad 21 and the bit line (not shown) contacting the one landing plug 18 of the cell transistor, the third and fourth insulating layers ( 22) 23 are formed.
이어, 셀 트랜지스터의 타측의 랜딩 플러그(18)에 콘택되는 상부 플러그(18a)를 형성하고 전면에 제 5 절연층(27)을 형성한다.Subsequently, an upper plug 18a that contacts the landing plug 18 on the other side of the cell transistor is formed, and a fifth insulating layer 27 is formed on the entire surface.
그리고 상기 제 5 절연층(27)을 선택적으로 식각하여 상기 상부 플러그(18a)가 노출되도록 커패시터 형성 영역을 정의하고 하부 전극(24), 유전층(25), 상부 전극(26)을 형성한다.The fifth insulating layer 27 is selectively etched to define a capacitor formation region to expose the upper plug 18a and to form a lower electrode 24, a dielectric layer 25, and an upper electrode 26.
이어, 도 1e에서와 같이, 상기 상부 전극(26)을 포함하는 전면에 제 6 절연층(28)을 형성하고 제 6 절연층(28)상에 주변 회로 영역의 액티브 일부 및 워드 라인, 비트 라인의 상부가 각각 오픈되는 제 1 메탈 콘택 마스크(29)층을 형성한다.Subsequently, as shown in FIG. 1E, a sixth insulating layer 28 is formed on the entire surface including the upper electrode 26, and an active part and a word line and a bit line of the peripheral circuit region are formed on the sixth insulating layer 28. The first metal contact masks 29 are formed to have upper portions of the first metal contact masks 29 open.
그리고 상기 제 1 메탈 콘택 마스크(29)를 이용하여 주변 회로 영역의 액티브 일부 및 워드 라인, 비트 라인의 상부에 적층된 절연층들을 선택적으로 식각하여 주변 회로 영역의 메탈 콘택홀(30)(31)(32)을 형성한다.The metal contact holes 30 and 31 of the peripheral circuit region may be selectively etched by selectively etching the active portions of the peripheral circuit region and the insulating layers stacked on the word lines and the bit lines using the first metal contact mask 29. To form 32.
여기서, 주변 회로 영역의 메탈 콘택홀(30)을 형성하는 공정시에 더미 랜딩 플러그(19)는 제거된다.Here, the dummy landing plug 19 is removed in the process of forming the metal contact hole 30 in the peripheral circuit region.
이어, 도 1f에서와 같이, 상기 주변 회로 영역의 메탈 콘택홀(30)(31)(32)을 포함하는 전면에 제 2 메탈 콘택 마스크(33)를 형성한다.Subsequently, as shown in FIG. 1F, a second metal contact mask 33 is formed on the entire surface including the metal contact holes 30, 31, and 32 of the peripheral circuit region.
상기 제 2 메탈 콘택 마스크(33)는 셀 영역의 커패시터 상부 전극(26)의 일부 영역상이 오픈된다.The second metal contact mask 33 is opened on a portion of the capacitor upper electrode 26 in the cell region.
그리고 상기 제 2 메탈 콘택 마스크(33)를 이용하여 제 6 절연층(28)을 선택적으로 식각하여 셀 영역의 메탈 콘택홀(34)을 형성한다.The sixth insulating layer 28 is selectively etched using the second metal contact mask 33 to form the metal contact hole 34 in the cell region.
이어, 도 1g에서와 같이, 상기 메탈 콘택홀(34)(30)(31)(32)의 표면에 메탈 베리어층(35a)을 형성하고 메탈 콘택홀(34)(30)(31)(32)이 매립되도록 메탈 배선을 형성한다.Subsequently, as shown in FIG. 1G, the metal barrier layer 35a is formed on the surfaces of the metal contact holes 34, 30, 31, and 32, and the metal contact holes 34, 30, 31, and 32 are formed. Metal wires are formed to fill the gaps.
이와 같은 본 발명에 따른 반도체 메모리 소자의 제조 방법은 셀 영역과 동일한 공정으로 주변 회로 영역에 더미 랜딩 플러그를 형성하여 셀 영역의 랜딩 플러그 콘택을 위한 CMP 공정시에 주변 회로 영역의 디싱 현상을 억제하고, 후속되는 메탈 콘택홀 형성시에 제거되어 트랜지스터에 영향을 주지 않는다.Such a method of manufacturing a semiconductor memory device according to the present invention suppresses dishing phenomenon in the peripheral circuit region during the CMP process for landing plug contact of the cell region by forming a dummy landing plug in the peripheral circuit region in the same process as the cell region. It is removed during subsequent metal contact hole formation and does not affect the transistor.
이와 같은 본 발명에 따른 반도체 메모리 소자의 제조 방법은 다음과 같은 효과가 있다.Such a method of manufacturing a semiconductor memory device according to the present invention has the following effects.
첫째, 주변 회로 영역의 메탈 콘택의 베리어층으로 질화막을 사용하지 않고 더미 랜딩 플러그를 사용하기 때문에 질화막 자체의 컴프레스 스트레스에 의한 결함 발생을 억제한다.First, since the dummy landing plug is used instead of the nitride film as the barrier layer of the metal contact in the peripheral circuit area, defect generation due to the compression stress of the nitride film itself is suppressed.
이는 디바이스의 동작 특성을 향상시킨다.This improves the operating characteristics of the device.
둘째, 더미 랜딩 플러그의 사용으로 CMP 공정시에 주변 회로 영역의 디싱을 억제할 수 있고 셀 영역과 주변 회로 영역간의 스텝 커버리지를 충분히 확보할 수 있어 수율을 향상시키는 효과가 있다.Second, the use of the dummy landing plug can suppress dishing of the peripheral circuit region during the CMP process and can sufficiently secure the step coverage between the cell region and the peripheral circuit region, thereby improving the yield.
Claims (4)
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| KR100427718B1 (en) * | 2002-06-29 | 2004-04-28 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| CN110265402B (en) * | 2019-06-27 | 2020-09-18 | 长江存储科技有限责任公司 | 3D NAND memory device and manufacturing method thereof |
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| JPH10189770A (en) * | 1996-12-25 | 1998-07-21 | Nec Corp | Semiconductor device |
| KR19980084296A (en) * | 1997-05-22 | 1998-12-05 | 윤종용 | Deep contact formation method of semiconductor device |
| JPH11289064A (en) * | 1998-04-01 | 1999-10-19 | Nec Corp | Semiconductor storage device and manufacture of the same |
| US6060349A (en) * | 1998-06-04 | 2000-05-09 | United Microelectronics Corp. | Planarization on an embedded dynamic random access memory |
| KR20000056158A (en) * | 1999-02-13 | 2000-09-15 | 윤종용 | Semiconductor memory device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH10189770A (en) * | 1996-12-25 | 1998-07-21 | Nec Corp | Semiconductor device |
| KR19980084296A (en) * | 1997-05-22 | 1998-12-05 | 윤종용 | Deep contact formation method of semiconductor device |
| JPH11289064A (en) * | 1998-04-01 | 1999-10-19 | Nec Corp | Semiconductor storage device and manufacture of the same |
| US6060349A (en) * | 1998-06-04 | 2000-05-09 | United Microelectronics Corp. | Planarization on an embedded dynamic random access memory |
| KR20000056158A (en) * | 1999-02-13 | 2000-09-15 | 윤종용 | Semiconductor memory device and method of fabricating the same |
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| KR100720261B1 (en) | 2006-01-26 | 2007-05-23 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
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