KR100361210B1 - Method of forming a contact hole in a semiconductor device - Google Patents
Method of forming a contact hole in a semiconductor device Download PDFInfo
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- KR100361210B1 KR100361210B1 KR1019990063913A KR19990063913A KR100361210B1 KR 100361210 B1 KR100361210 B1 KR 100361210B1 KR 1019990063913 A KR1019990063913 A KR 1019990063913A KR 19990063913 A KR19990063913 A KR 19990063913A KR 100361210 B1 KR100361210 B1 KR 100361210B1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 자기정렬 콘택(Self Align Contact; SAC) 식각 공정을 콘택홀을 형성하는 경우 콘택 사이즈가 증가하고 식각 장벽층의 손실로 인해 소자간 단락이 발생하는 문제점을 해결하기 위하여, SAC 식각 공정시 식각 선택비가 우수한 폴리실리콘을 식각 장벽층으로 활용하므로써, 식각 장벽층의 손실을 최소화하여 콘택과 하부 도전층과의 단락을 방지할 수 있고 더욱 미세한 콘택을 안정적으로 형성할 수 있도록 한 반도체 소자의 콘택홀 형성방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In the case of forming a contact hole in a Self Align Contact (SAC) etching process, a contact size increases and a short circuit occurs between devices due to loss of an etching barrier layer. In order to solve the problem, by using polysilicon having an excellent etching selectivity as an etching barrier layer in the SAC etching process, the loss of the etching barrier layer can be minimized to prevent short-circuit between the contact and the lower conductive layer. Disclosed is a method of forming a contact hole in a semiconductor device capable of forming it stably.
Description
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 자기정렬 콘택(Self Align Contact) 공정에 의해 소자간 상호 연결을 위한 콘택홀을 형성할 때, 콘택과 하부 도전층 간의 단락을 방지하고 콘택홀의 크기를 세밀화할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, when forming a contact hole for interconnection between devices by a self alignment contact process, a short circuit between a contact and a lower conductive layer is prevented and the contact is prevented. The present invention relates to a method for forming a contact hole in a semiconductor device capable of miniaturizing the size of a hole.
일반적으로, 소자간 상호 연결에 사용되는 콘택홀은 포토레지스트막을 마스크로 하는 직접 콘택 식각 방법에 의해 형성하거나, 포토레지스트 패턴 및 질화막 스페이서를 이용한 자기 정렬 콘택 공정에 의해 형성한다. 그러면, 종래 반도체 소자의 콘택홀 형성방법을 도 1을 참조하여 설명하면 다음과 같다.In general, contact holes used for interconnection between devices are formed by a direct contact etching method using a photoresist film as a mask or a self-aligned contact process using a photoresist pattern and a nitride film spacer. Next, a method of forming a contact hole of a conventional semiconductor device will be described with reference to FIG. 1.
도 1은 종래 반도체 소자의 콘택홀 형성방법을 설명하기 위해 도시한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of forming a contact hole in a conventional semiconductor device.
도시된 바와 같이, 반도체 기판(11) 상에 터널 산화막, 게이트 전극(12), 탑 산화막(130이 적층된 게이트 전극 패턴을 형성하고, 전체구조 상에 질화물질을 형성한 다음 스페이서 식각 공정을 실시하여 게이트 전극 패턴 측벽에 스페이서 질화막(14)을 형성한다. 이후, 전체구조 상에 층간 절연막(15)을 형성하고 콘택 마스크를 이용한 사진 및 식각 공정으로 층간 절연막(15) 상에 포토레지스트 패턴(16)을 형성한다. 그리고 포토레지스트 패턴(16)을 이용한 자기정렬 콘택(Self Align Contact; SAC) 식각 공정으로 층간 절연막(15)을 식각하여 콘택홀을 형성한다. 이자기정렬 콘택 식각 공정시에는 게이트 전극 패턴 측벽에 형성된 스페이서 질화막(14)이 식각 장벽층의 역할을 하게 된다.As illustrated, a gate electrode pattern in which the tunnel oxide film, the gate electrode 12, and the top oxide film 130 are stacked is formed on the semiconductor substrate 11, a nitride material is formed on the entire structure, and then a spacer etching process is performed. The spacer nitride film 14 is formed on the sidewalls of the gate electrode pattern, and then the interlayer insulating film 15 is formed on the entire structure, and the photoresist pattern 16 is formed on the interlayer insulating film 15 by a photo and etching process using a contact mask. And forming a contact hole by etching the interlayer insulating layer 15 by a Self Align Contact (SAC) etching process using the photoresist pattern 16. In the magnetic alignment contact etching process, a gate is formed. The spacer nitride layer 14 formed on the sidewalls of the electrode pattern serves as an etch barrier layer.
그런데, 이와 같은 콘택홀 형성 공정에서는 포토레지스트 패턴(16)의 손실로 인해 콘택홀 상부의 임계 치수(D1)가 하부의 임계 치수(D2)보다 커지는 현상이 발생하기 때문에 원하는 만큼의 작은 크기로 콘택홀의 임계치수를 제어하기 어렵게 된다. 이와 같이, 원하지 않게 콘택홀의 크기가 커짐에 따라 콘택간의 간격을 충분히 확보해야 하며, 이에 따라 레이아웃 사이즈를 크게 해야 하는 문제점이 있다.However, in such a contact hole forming process, a phenomenon in which the critical dimension D1 of the upper contact hole becomes larger than the critical dimension D2 of the lower part due to the loss of the photoresist pattern 16 causes the contact to be as small as desired. It is difficult to control the critical dimension of the hole. As such, as the size of the contact hole is undesirably large, the gap between the contacts must be sufficiently secured, thereby increasing the layout size.
또한, 자기정렬 콘택 식각 공정시 식각 장벽층으로 사용되는 스페이서 질화막(14)은 층간 절연막(15)인 산화막 식각시 식각 선택비가 상대적으로 우수하지 못하여 자기정렬 콘택 식각 공정시 스페이서 질화막(14)이 손실되게 된다. 이에 따라 게이트 전극 패턴이 노출되게 되어 소자간 단락이 발생하는 등 소자의 전기적 특성이 저하되게 된다. 이러한 문제를 해결하기 위하여 선택비를 높이는 식각 레시피를 진행하고 있으나, 식각 프로파일상 기울기(slope)가 심하여 콘택홀 상부에 비해 콘택홀 하부의 임계치수가 매우 작아지게 되어, 미세한 콘택홀을 형성할 수 없게 되는 단점이 있다.In addition, the spacer nitride layer 14 used as an etch barrier layer during the self-aligned contact etching process has a relatively poor etching selectivity during the oxide layer etching, which is the interlayer insulating layer 15, and thus the spacer nitride layer 14 is lost during the self-aligned contact etching process. Will be. As a result, the gate electrode pattern is exposed, thereby causing a short circuit between the devices, thereby deteriorating the electrical characteristics of the device. In order to solve this problem, an etching recipe for increasing the selectivity is being carried out. However, since the slope in the etching profile is severe, the critical dimension of the contact hole lower than that of the contact hole is very small, so that a fine contact hole cannot be formed. There is a disadvantage.
따라서, 본 발명은 폴리실리콘을 하드 마스크로 이용한 자기정렬 콘택 식각 방법으로 콘택홀을 형성하므로써, 소자간의 단락을 방지하고 패턴 크기의 손실 없이 더욱 미세한 콘택을 안정적으로 형성할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a contact hole by a self-aligned contact etching method using polysilicon as a hard mask, thereby preventing contact between devices and stably forming finer contacts without losing a pattern size. The purpose is to provide a formation method.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택홀 형성방법은 반도체 기판 상에 게이트 산화막, 게이트 전극 및 탑 산화막을 순차적으로 형성하는 단계; 상기 탑 산화막 상에 제 1 식각 장벽층을 형성하는 단계; 게이트 마스크를 이용한 식각 공정으로 상기 제 1 식각 장벽층, 탑 산화막, 게이트 전극 및 게이트 산화막을 순차적으로 식각하여 게이트 전극 패턴을 형성한 후 전체구조 상에 질화물질을 형성하고 스페이서 식각 공정을 실시하여, 상기 게이트 전극 패턴 양측부에 스페이서 질화막을 형성하는 단계; 전체구조 상에 층간 절연막을 형성하고 화학적 기계적 연마 공정을 실시하는 단계; 상기 층간 절연막 상에 제 2 식각 장벽층을 형성하는 단계; 및 상기 제 2 식각 장벽층 상에 포토레지스트 패턴을 형성하고 제 2 식각 장벽층을 패터닝한 후, 상기 패터닝된 제 2 식각 장벽층을 마스크로 이용하여 상기 반도체 기판이 노출되도록 상기 층간 절연막을 식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: sequentially forming a gate oxide film, a gate electrode, and a top oxide film on a semiconductor substrate; Forming a first etching barrier layer on the top oxide layer; In the etching process using a gate mask, the first etching barrier layer, the top oxide layer, the gate electrode, and the gate oxide layer are sequentially etched to form a gate electrode pattern, a nitride material is formed on the entire structure, and a spacer etching process is performed. Forming a spacer nitride film on both sides of the gate electrode pattern; Forming an interlayer insulating film on the entire structure and performing a chemical mechanical polishing process; Forming a second etching barrier layer on the interlayer insulating film; And forming a photoresist pattern on the second etch barrier layer and patterning a second etch barrier layer, and then etching the interlayer insulating layer to expose the semiconductor substrate using the patterned second etch barrier layer as a mask. Characterized in that comprises a step.
도 1은 종래 반도체 소자의 콘택홀 형성방법을 설명하기 위해 도시한 소자의 단면도.1 is a cross-sectional view of a device illustrated to explain a method for forming a contact hole in a conventional semiconductor device.
도 2a 내지 2c는 본 발명에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.2A to 2C are cross-sectional views of devices sequentially shown to explain a method for forming a contact hole in a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11, 21 : 반도체 기판 12, 22 : 게이트 전극11 and 21: semiconductor substrate 12 and 22: gate electrode
13, 23 : 탑 산화막 14, 25 : 스페이서 질화막13, 23: top oxide film 14, 25: spacer nitride film
15, 27 : 층간 절연막 16, 29 : 포토레지스트 패턴15, 27: interlayer insulating film 16, 29: photoresist pattern
24 : 제 1 식각 장벽층 26 : 게이트 전극 패턴24: first etching barrier layer 26: gate electrode pattern
28 : 제 2 식각 장벽층 30 : 폴리실리콘 플러그28: second etching barrier layer 30: polysilicon plug
31 ; 배선31; Wiring
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 2a 내지 2c는 본 발명에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.2A through 2C are cross-sectional views of devices sequentially illustrated to explain a method for forming contact holes in a semiconductor device according to the present invention.
도 2a를 참조하여, 반도체 기판(21) 상에 게이트 산화막, 게이트 전극(22)및 탑 산화막(23)을 순차적으로 형성한 후, 탑 산화막(23) 상에 후속 자기정렬 콘택 식각 공정시 식각 장벽층으로 사용될 제 1 식각 장벽층(24)을 형성한다. 여기에서, 제 1 식각 장벽층은 폴리실리콘을 100 내지 1000Å의 두께로 증착하여 형성한다. 이후, 게이트 마스크를 이용한 식각 공정으로 제 1 식각 장벽층(24), 탑 산화막(23), 게이트 전극(22) 및 게이트 산화막을 순차적으로 식각하며, 이로 인하여 게이트 전극 패턴(26)이 형성된다. 다음에, 전체구조 상에 질화물질을 형성한 후 스페이서 식각 공정을 실시하여, 게이트 전극 패턴(26) 양측부에 스페이서 질화막(25)을 형성한다.Referring to FIG. 2A, after the gate oxide layer, the gate electrode 22, and the top oxide layer 23 are sequentially formed on the semiconductor substrate 21, an etch barrier during the subsequent self-aligned contact etching process on the top oxide layer 23 is performed. A first etch barrier layer 24 to be used as the layer is formed. Here, the first etching barrier layer is formed by depositing polysilicon to a thickness of 100 to 1000 kPa. Thereafter, the first etching barrier layer 24, the top oxide layer 23, the gate electrode 22, and the gate oxide layer are sequentially etched by an etching process using a gate mask, thereby forming the gate electrode pattern 26. Next, after the nitride material is formed on the entire structure, a spacer etching process is performed to form the spacer nitride layer 25 on both sides of the gate electrode pattern 26.
도 2b를 참조하여, 스페이서 질화막(25)이 형성된 게이트 전극 패턴(25)을 포함하는 전체구조 상에 층간 절연막(27)을 형성하고 게이트 전극 패턴(26) 상부의 제 1 식각 장벽층(24)이 손상을 입지 않을 정도의 타겟으로 화학적 기계적 연마(CMP) 공정을 실시한 후, 층간 절연막(27) 상에 후속 자기정렬 콘택 식각 공정시 식각 장벽층으로 사용하기 위한 제 2 식각 장벽층(28)을 형성한다. 여기에서, 제 2 식각 장벽층(28)은 폴리실리콘을 100 내지 1000Å의 두께로 증착하여 형성한다. 이후, 콘택 마스크를 이용한 사진 및 식각 공정으로 제 2 식각 장벽층(28) 상에 포토레지스트 패턴(29)을 형성한다. 이 포토레지스트 패턴(29)을 마스크로 이용하여 제 2 식각 장벽층(28)을 패터닝한 후, 패터닝된 제 2 식각 장벽층(28)을 식각 장벽층으로 이용하여 층간 절연막(27)을 식각하므로써, 원하는 콘택홀을 형성한다. 이 식각 공정시 제 2 식각 장벽층(28) 및 하드 마스크로서의 제 1 식각 장벽층(24)이 자기정렬 콘택 식각 공정시의 식각 장벽층으로서 작용한다. 또한, 제 1 및 제 2식각 장벽층(24, 28)으로 사용되는 폴리실리콘과 층간 절연막(27)으로 사용되는 산화막과의 식각 선택비가 높기 때문에 자기정렬 콘택 식각 공정 후 콘택홀 상부의 치수가 원하는 크기보다 증가하는 현상을 방지할 수 있다. 그리고, 제 1 식각 장벽층(24)이 하드 마스크로 작용하기 때문에 스페이서 질화막(25)의 손실을 최소화할 수 있다.Referring to FIG. 2B, an interlayer insulating layer 27 is formed on the entire structure including the gate electrode pattern 25 on which the spacer nitride layer 25 is formed, and the first etching barrier layer 24 on the gate electrode pattern 26 is formed. After the chemical mechanical polishing (CMP) process is performed on the target that is not damaged, the second etching barrier layer 28 is used on the interlayer insulating layer 27 as an etching barrier layer in the subsequent self-aligned contact etching process. Form. Here, the second etching barrier layer 28 is formed by depositing polysilicon to a thickness of 100 to 1000 GPa. Thereafter, the photoresist pattern 29 is formed on the second etching barrier layer 28 by a photolithography and an etching process using a contact mask. After patterning the second etch barrier layer 28 using the photoresist pattern 29 as a mask, the interlayer insulating film 27 is etched by using the patterned second etch barrier layer 28 as the etch barrier layer. , To form a desired contact hole. In this etching process, the second etching barrier layer 28 and the first etching barrier layer 24 as a hard mask serve as an etching barrier layer in the self-aligned contact etching process. In addition, since the etch selectivity between the polysilicon used as the first and second etch barrier layers 24 and 28 and the oxide film used as the interlayer insulating film 27 is high, the dimension of the upper contact hole after the self-aligned contact etching process is desired. It is possible to prevent the phenomenon of increasing in size. In addition, since the first etching barrier layer 24 serves as a hard mask, loss of the spacer nitride layer 25 may be minimized.
도 2c를 참조하여, 포토레지스트 패턴(29) 및 제 2 식각 장벽층(28)을 순차적으로 제거한 후, 콘택홀이 매립되도록 폴리실리콘을 증착하고, 제 1 식각 장벽층(24)까지 제거될 수 있는 타겟으로 연마 공정을 진행하며 이로 인하여, 폴리실리콘 플러그(30)가 형성된다. 이후, 각 단위소자를 연결하기 위한 도전층을 증착하고 패터닝하여 배선(31)을 형성한다.Referring to FIG. 2C, after the photoresist pattern 29 and the second etch barrier layer 28 are sequentially removed, polysilicon may be deposited to fill the contact holes, and the first etch barrier layer 24 may be removed. The polishing process proceeds to the target, whereby the polysilicon plug 30 is formed. Thereafter, a conductive layer for connecting each unit device is deposited and patterned to form a wiring 31.
이와 같이 본 발명은 종래 자기정렬 콘택 식각 공정의 부족한 마진 문제를 해결하기 위하여 층간 절연막 식각시 식각 선택비가 우수한 폴리실리콘을 식각 장벽층으로 활용하여 자기정렬 콘택 식각 공정시 식각 장벽층의 손실을 최소화하여 콘택과 하부 도전층과의 단락을 방지할 수 있다. 또한, 폴리실리콘을 장기정렬 콘택 식각 공정의 마스크로 활용하므로써 포로레지스트로 폴리실리콘 패턴을 형성하고 그 폴리실리콘을 마스크로 이용하여 식각 공정을 진행하므로써, 포토레지스트 패턴이 손실되더라도 추가적인 패턴 크기의 손실 없이 콘택을 형성할 수 있게 되어 더욱 미세한 콘택을 안정적으로 형성할 수 있다.As such, the present invention minimizes the loss of the etch barrier layer during the self-aligned contact etching process by using polysilicon having an excellent etching selectivity during the interlayer insulation layer etching as an etch barrier layer to solve the problem of insufficient margin of the conventional self-aligned contact etching process. Short circuit between the contact and the lower conductive layer can be prevented. In addition, by using polysilicon as a mask for a long-term alignment contact etching process, a polysilicon pattern is formed with a photoresist and the etching process is performed using the polysilicon as a mask, so that even if the photoresist pattern is lost, no additional pattern size is lost. It is possible to form a contact, it is possible to form a finer contact stably.
상술한 바와 같이 본 발명은 자기정렬 콘택(Self Align Contact; SAC) 식각 공정을 이용하여 콘택홀을 형성할 때 폴리실리콘을 식각 장벽층으로 활용하므로써, SAC 식각 공정시 식각 장벽층의 손실을 최소화하여 콘택과 하부 도전층과의 단락을 방지할 수 있고, 더욱 미세한 크기의 콘택을 형성할 수 있다. 이에 따라 더욱 작은 미세 패턴의 형성이 가능하게 되어 양산공정 마진을 충분히 확보할 수 있고 제품의 추가적인 소형화가 가능하게 된다.As described above, the present invention utilizes polysilicon as an etch barrier layer when forming a contact hole using a Self Align Contact (SAC) etching process, thereby minimizing the loss of the etch barrier layer during the SAC etching process. It is possible to prevent a short circuit between the contact and the lower conductive layer, and to form a contact having a finer size. Accordingly, it is possible to form a smaller fine pattern to ensure a sufficient mass production process margin and further miniaturization of the product.
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| JPH09199589A (en) * | 1996-01-18 | 1997-07-31 | Sony Corp | Wiring pattern formation |
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| JPH09199589A (en) * | 1996-01-18 | 1997-07-31 | Sony Corp | Wiring pattern formation |
| JPH1041505A (en) * | 1996-07-24 | 1998-02-13 | Sony Corp | Manufacture of semiconductor device |
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