KR20040059900A - Method for making deep detail contact plug in semiconductor - Google Patents

Method for making deep detail contact plug in semiconductor Download PDF

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KR20040059900A
KR20040059900A KR1020020086405A KR20020086405A KR20040059900A KR 20040059900 A KR20040059900 A KR 20040059900A KR 1020020086405 A KR1020020086405 A KR 1020020086405A KR 20020086405 A KR20020086405 A KR 20020086405A KR 20040059900 A KR20040059900 A KR 20040059900A
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South Korea
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contact
hard mask
contact plug
forming
film
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KR1020020086405A
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Korean (ko)
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KR100641491B1 (en
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박철수
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동부전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming an ultra-fine contact plug of a semiconductor device is provided to prevent short between the second conductor and a contact plug by using a hard mask spacer. CONSTITUTION: The first planarization insulating layer(10), the first conductor(20), the second planarization insulating layer(30), the second conductor(40), the third planarization insulating layer(50) and a nitride layer as a hard mask are sequentially formed on a silicon substrate. The nitride layer and the third planarization insulating layer are selectively etched to form a contact forming region by using a photoresist pattern as an etching mask. A hard mask spacer(80) for reducing the size of contact is formed at sidewalls of the contact forming region. The first conductor is partially exposed by forming a contact hole under the contact forming region using the spacer as an etching mask. A contact plug(90) is entirely filled in the contact hole and the contact forming region.

Description

반도체의 극 미세 컨택 플러그 형성방법{METHOD FOR MAKING DEEP DETAIL CONTACT PLUG IN SEMICONDUCTOR}METHOD FOR MAKING DEEP DETAIL CONTACT PLUG IN SEMICONDUCTOR}

본 발명은 반도체의 극 미세 컨택 플러그 형성방법에 관한 것으로, 특히 스택 비아(stacked via)를 5개 이하까지 줄여 비아 저항을 감소시킬 수 있으며, 미스어라인 마진(misalign margin)을 개선할 수 있도록 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an extremely fine contact plug of a semiconductor, and in particular, reduces via resistance by reducing the number of stacked vias to five or less, and improves misalign margins. It is about a method.

통상적으로, 반도체의 집적도가 증가함에 따라 로직 기술(logic technology)은 0.09㎛ 기술에서 최대 메탈 계층(maximum metal layer) 수만도 9층 메탈 계층이다.Typically, as the degree of integration of semiconductors increases, the logic technology is a 9-layer metal layer with tens of thousands of maximum metal layers in a 0.09 μm technology.

즉, 스택 비아가 최대 9개까지 생성되어 비아 저항이 매우 증가하게 되는 단점이 있으며, 또한 미스 어라인 마진도 제로(zero) 이하임에 따라 회로 구성상 많은 압력을 받게 되며, 리소그래피 측면에서도 전도체 간에 쇼트(short) 현상이 발생하게 되는 문제점이 있다.In other words, up to nine stack vias are generated, which greatly increases via resistance. Also, the misalignment margin is less than zero, which results in a large pressure on the circuit configuration. There is a problem that a short phenomenon occurs.

따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로서, 그 목적은 스택 비아(stacked via)를 5개 이하까지 줄여 비아 저항을 감소시킬 수 있으며, 미스어라인 마진(misalign margin)을 개선하여 전도체 간에 쇼트 현상을 방지할 수 있도록 하는 반도체의 극 미세 컨택 플러그 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems, the object of which is to reduce the via resistance by reducing the number of stacked vias to five or less, and to improve the misalign margin It is an object of the present invention to provide a method for forming an extremely fine contact plug of a semiconductor which can prevent a short phenomenon between conductors.

상술한 목적을 달성하기 위한 본 발명에서 반도체의 극 미세 컨택 플러그 형성방법은 실리콘 기판 상에 제1 평탄화 절연막, 제1 전도체, 제2 평탄화 절연막, 제2 전도체를 순차적으로 형성하며, 그 상부에 제3 평탄화 절연막, 하드 마스크용 질화막을 순차적으로 적층하는 단계; 적층된 하드 마스크용 질화막 상에 컨택 형성용 감광막을 패터닝(patterning)하여 제거하고, 노출된 하드 마스크용 질화막 및 제3 평탄화 절연막을 식각하는 단계; 컨택 형성용 감광막이 제거된 상태에서, 컨택 크기를 축소하기 위해 하드 마스크 스페이서를 제3 평탄화 절연막 상부에 증착하고, 블랭킷 식각백(blanket etch back)을 수행하여 하드 마스크 스페이서를 완성하는 단계; 하드 마스크용 질화막과 콘택 크기 축소를 위한 하드 마스크 스페이서를마스크(mask)하여 노출된 제3 평탄화 절연막을 건식 식각하여 제1 전도체가 노출되도록 한 다음에 컨택 플러그용 막을 그 상부에 적층 매립하고, CMP 평탄화를 통해 컨택 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.In the present invention for achieving the above object, the method for forming an extremely fine contact plug of a semiconductor sequentially forms a first planarization insulating film, a first conductor, a second planarization insulating film, and a second conductor on a silicon substrate, and Sequentially stacking a planarization insulating film and a nitride film for a hard mask; Patterning and removing the contact forming photoresist on the stacked hard mask nitride films, and etching the exposed hard mask nitride film and the third planarization insulating film; Depositing a hard mask spacer on the third planarization insulating layer to reduce the contact size in a state where the contact forming photoresist film is removed, and performing a blanket etch back to complete the hard mask spacer; Masking the nitride film for hard mask and the hard mask spacer for reducing the contact size to dry-etch the exposed third planarization insulating film so that the first conductor is exposed, and then the contact plug film is buried on top of the CMP. Forming a contact plug through planarization.

도 1a 내지 도 1b는 본 발명에 따른 반도체의 극 미세 컨택 플러그 형성을 위한 공정과정에 대하여 도시한 단면도이다.1A to 1B are cross-sectional views illustrating a process for forming an extremely fine contact plug of a semiconductor according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 제1 평탄화 절연막 20 : 제1 전도체10: first planarization insulating film 20: first conductor

30 : 제2 평탄화 절연막 40 : 제2 전도체30 second planarization insulating film 40 second conductor

50 : 제3 평탄화 절연막 60 : 하드 마스크용 질화막50: third planarization insulating film 60: nitride film for hard mask

70 : 컨택 형성용 감광막 80 : 하드 마스크 스페이서70 photosensitive film for contact formation 80 hard mask spacer

90 : 컨택 플러그90: contact plug

이하, 첨부된 도면을 참조하여 본 발명에 따른 일 실시 예를 상세하게 설명하기로 한다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1b는 본 발명에 따른 반도체의 극 미세 컨택 플러그 형성을 위한 공정과정에 대하여 도시한 단면도이다.1A to 1B are cross-sectional views illustrating a process for forming an extremely fine contact plug of a semiconductor according to the present invention.

즉, 도 1a를 참조하면, 실리콘 기판 상에 제1 평탄화 절연막(10), 제1 전도체(20), 제2 평탄화 절연막(30), 제2 전도체(40)를 순차적으로 형성한다. 그리고 그 상부에 제3 평탄화 절연막(50), 하드 마스크용 질화막(60)을 순차적으로 적층한다.That is, referring to FIG. 1A, a first planarization insulating film 10, a first conductor 20, a second planarization insulating film 30, and a second conductor 40 are sequentially formed on a silicon substrate. Then, the third planarization insulating film 50 and the hard mask nitride film 60 are sequentially stacked thereon.

이후, 적층된 하드 마스크용 질화막(60) 상에 컨택 형성용 감광막(70)을 패터닝(patterning)하여 제거하고, 노출된 하드 마스크용 질화막(60)을 식각하고, 이어서 소정의 깊이로 제3 평탄화 절연막(50)을 식각한다.Thereafter, the contact forming photoresist film 70 is patterned and removed on the stacked hard mask nitride film 60, and the exposed hard mask nitride film 60 is etched, and then third planarized to a predetermined depth. The insulating film 50 is etched.

이때, 제2 전도체(40)를 건너뛰어서 제1 전도체(20)가 노출되도록 식각할 경우, 제2 전도체(40)와 컨택 플러그(plug)(90)간에 쇼트(short) 현상이 발생된다.In this case, when the second conductor 40 is skipped and the first conductor 20 is etched to be exposed, a short phenomenon occurs between the second conductor 40 and the contact plug 90.

또한, 컨택 형성용 감광막(70)을 패터닝하기 위한 크기(size)를 줄이기 힘들 경우, 컨택 크기를 약간 더 크게 하고, 컨택 크기 축소용 하드 마스크 스페이서(80)를 키운다.In addition, when it is difficult to reduce the size for patterning the contact forming photoresist film 70, the contact size is slightly larger, and the hard mask spacer 80 for reducing the contact size is increased.

도 1b를 참조하면, 도 1a에서 컨택 형성용 감광막(70)이 제거된 상태에서, 컨택 크기를 축소하기 위해 하드 마스크 스페이서(80)를 제3 평탄화 절연막(50) 상부에 증착하고, 블랭킷 식각백(blanket etch back)을 수행하여 하드 마스크 스페이서(80)를 완성한다.Referring to FIG. 1B, in a state in which the contact forming photoresist layer 70 is removed in FIG. 1A, a hard mask spacer 80 is deposited on the third planarization insulating layer 50 to reduce the contact size, and the blanket etch back. Blank mask etch is performed to complete the hard mask spacer 80.

이때, 하드 마스크 스페이서(80) 재료(material)의 필요 조건은 제3 평탄화 절연막(50)을 건식 식각시, 거의 식각이 되지 않는 질화막이나, TaN 또는 TiN 혹은 블랭킷 텅스텐(blanket W)을 사용한다.In this case, the hard mask spacer 80 material may be formed of a nitride film hardly etched when the third planarization insulating film 50 is dry etched, or TaN, TiN, or blanket tungsten.

다음으로, 하드 마스크용 질화막(60)과 콘택 크기 축소를 위한 하드 마스크 스페이서(80)를 마스크로 하여 노출된 제3 평탄화 절연막(50)을 건식 식각하여 제1 전도체(20)가 노출되도록 한 다음에 컨택 플러그용 막을 그 상부에 적층 매립하고, CMP 평탄화를 하여 컨택 플러그(90)를 형성한다.Next, dry etching the exposed third planarization insulating layer 50 using the hard mask nitride layer 60 and the hard mask spacer 80 for reducing the contact size as a mask to expose the first conductor 20. The contact plug film is laminated and buried thereon, and CMP planarization is performed to form the contact plug 90.

여기서, 컨택 플러그용 막은 CVD TiN+blanket W 또는 CVD TiN+blanket W 혹은 CVD TaN 또는 CVD TiN 이다.Here, the contact plug film is CVD TiN + blanket W or CVD TiN + blanket W or CVD TaN or CVD TiN.

이에 따라, 제1 전도체, 제2 전도체, 제3 전도체,... 가 순차적으로 적층되어 있을 때, 제1 전도체와 제3 전도체를 상호 연결할 경우, 컨택 크기 축소용 하드 마스크 스페이서를 사용하여 제2 전도체와의 쇼트(short) 현상을 방지할 수 있다.Accordingly, when the first conductor, the second conductor, the third conductor, ... are sequentially stacked, when the first conductor and the third conductor are interconnected, the second mask may be formed using a hard mask spacer for reducing the contact size. Short phenomenon with the conductor can be prevented.

그러므로, 본 발명은 스택 비아(stacked via)를 5개 이하까지 줄여 비아 저항을 감소시킬 수 있으며, 미스어라인 마진(misalign margin)을 개선함으로써, 제1 전도체, 제2 전도체, 제3 전도체,... 가 순차적으로 적층되어 있을 때, 제1 전도체와 제3 전도체를 상호 연결할 경우, 컨택 크기 축소용 하드 마스크 스페이서를 사용하여 제2 전도체와의 쇼트(short) 현상을 방지할 수 있는 효과가 있다.Therefore, the present invention can reduce via resistance by reducing the number of stacked vias to five or less, and by improving the misalign margin, the first conductor, the second conductor, the third conductor,. When .. is sequentially stacked, when the first conductor and the third conductor are interconnected, a short mask with the second conductor can be prevented by using a hard mask spacer for reducing the contact size. .

Claims (10)

반도체의 컨택 플러그 형성방법에 있어서,In the method of forming a contact plug of a semiconductor, 실리콘 기판 상에 제1 평탄화 절연막, 제1 전도체, 제2 평탄화 절연막, 제2 전도체를 순차적으로 형성하며, 그 상부에 제3 평탄화 절연막, 하드 마스크용 질화막을 순차적으로 적층하는 단계;Sequentially forming a first planarization insulation film, a first conductor, a second planarization insulation film, and a second conductor on the silicon substrate, and sequentially depositing a third planarization insulation film and a nitride film for a hard mask thereon; 상기 적층된 하드 마스크용 질화막 상에 컨택 형성용 감광막을 패터닝(patterning)하여 제거하고, 상기 노출된 하드 마스크용 질화막 및 제3 평탄화 절연막을 식각하는 단계;Patterning and removing the contact forming photoresist on the stacked hard mask nitride films, and etching the exposed hard mask nitride film and the third planarization insulating film; 상기 컨택 형성용 감광막이 제거된 상태에서, 컨택 크기를 축소하기 위해 하드 마스크 스페이서를 상기 제3 평탄화 절연막 상부에 증착하고, 블랭킷 식각백(blanket etch back)을 수행하여 하드 마스크 스페이서를 완성하는 단계;Depositing a hard mask spacer on the third planarization insulating layer to reduce the size of the contact in the state in which the contact forming photoresist film is removed, and performing a blanket etch back to complete the hard mask spacer; 상기 하드 마스크용 질화막과 콘택 크기 축소를 위한 상기 하드 마스크 스페이서를 마스크(mask)하여 노출된 제3 평탄화 절연막을 건식 식각하여 상기 제1 전도체가 노출되도록 한 다음에 컨택 플러그용 막을 그 상부에 적층 매립하고, CMP 평탄화를 통해 컨택 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.Dry etching the exposed third planarization insulating layer by masking the hard mask nitride layer and the hard mask spacer for reducing the contact size so that the first conductor is exposed, and then the contact plug layer is buried thereon. And forming a contact plug through CMP planarization. 제 1 항에 있어서,The method of claim 1, 상기 컨택 형성용 감광막을 패터닝하기 위한 크기(size)를 줄이기가 힘들 경우, 컨택 크기를 약간 더 크게 하고, 컨택 크기 축소용 하드 마스크 스페이서를 키우는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.When it is difficult to reduce the size for patterning the contact forming photoresist, the contact size is slightly larger, and the method for forming a micro-fine contact plug of a semiconductor, characterized in that to increase the hard mask spacer for reducing the contact size. 제 1 항에 있어서,The method of claim 1, 상기 하드 마스크 스페이서 재료(material)의 필요 조건은 상기 제3 평탄화 절연막을 건식 식각시, 거의 식각이 되지 않는 TaN인 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.The hard mask spacer material material is TaN hardly etched when the third planarization insulating film is dry etched. 제 3 항에 있어서,The method of claim 3, wherein 상기 하드 마스크 스페이서 재료(material)는 TiN을 사용하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.And said hard mask spacer material uses TiN. 제 3 항에 있어서,The method of claim 3, wherein 상기 하드 마스크 스페이서 재료(material)는 블랭킷 텅스텐(blanket W)을 사용하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.And said hard mask spacer material uses a blanket tungsten (blanket W). 제 1 항에 있어서,The method of claim 1, 상기 컨택 플러그용 막은 CVD TiN+blanket W을 사용하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.The method of forming a contact plug of a semiconductor is characterized in that the contact plug film uses CVD TiN + blanket W. 제 6 항에 있어서,The method of claim 6, 상기 컨택 플러그용 막은 CVD TiN+blanket W를 사용하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.The method of forming a contact plug of a semiconductor is characterized in that the contact plug film uses CVD TiN + blanket W. 제 6 항에 있어서,The method of claim 6, 상기 컨택 플러그용 막은 CVD TaN 을 사용하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.The method of forming a contact plug of a semiconductor is characterized in that the contact plug film uses CVD TaN. 제 6 항에 있어서,The method of claim 6, 상기 컨택 플러그용 막은 CVD TiN 을 사용하는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.The method of forming a contact plug of a semiconductor is characterized in that the contact plug film uses CVD TiN. 제 1 항에 있어서,The method of claim 1, 상기 제1 전도체 까지 건식 식각하고 산화막 스페이서를 사용하여 쇼트를 방지할 수 있는 것을 특징으로 하는 반도체의 극 미세 컨택 플러그 형성방법.Dry etching to the first conductor and a short to prevent a short by using an oxide film spacer forming method of a semiconductor.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100776215B1 (en) * 2005-01-25 2007-11-16 삼성전자주식회사 Apparatus and method for estimating location and generating map of mobile body, using upper image, computer-readable recording media storing computer program controlling the apparatus
KR20130106917A (en) * 2012-03-21 2013-10-01 삼성전자주식회사 Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100776215B1 (en) * 2005-01-25 2007-11-16 삼성전자주식회사 Apparatus and method for estimating location and generating map of mobile body, using upper image, computer-readable recording media storing computer program controlling the apparatus
KR20130106917A (en) * 2012-03-21 2013-10-01 삼성전자주식회사 Semiconductor device and method for fabricating the same

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