KR20020046681A - method for forming contact hole semiconductor device - Google Patents
method for forming contact hole semiconductor device Download PDFInfo
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- KR20020046681A KR20020046681A KR1020000076989A KR20000076989A KR20020046681A KR 20020046681 A KR20020046681 A KR 20020046681A KR 1020000076989 A KR1020000076989 A KR 1020000076989A KR 20000076989 A KR20000076989 A KR 20000076989A KR 20020046681 A KR20020046681 A KR 20020046681A
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- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Chemical Kinetics & Catalysis (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 딥 콘택(deep contact) 형성시 탑(top) 부위의 임계치수 증가를 방지하는데 적당한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device suitable for preventing an increase in a critical dimension of a top portion when forming a deep contact.
일반적으로 에스펙트 비(aspect ratio)가 큰 딥 콘택홀 형성시에 포토 공정의 해상도 마진 확보를 위해서는 감광막의 두께를 가능한 낮추거나 하드 마스크를 사용하는 방법이 있다.In general, in order to secure the resolution margin of the photo process when forming a deep contact hole having a large aspect ratio, there is a method of reducing the thickness of the photoresist film or using a hard mask.
이하, 첨부된 도면을 참조하여 종래 기술의 반도체 소자의 콘택홀 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact hole in a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술의 반도체 소자의 콘택홀 형성방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device of the prior art.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판(11)상에 절연막(12)을 형성한다.First, as shown in FIG. 1A, an insulating film 12 is formed on the semiconductor substrate 11.
이어, 상기 절연막(12)상에 감광막(13)을 도포한 후, 노광 및 현상공정으로 패터닝(Patterning)한다.Subsequently, the photoresist film 13 is coated on the insulating film 12, and then patterned by exposure and development processes.
도 1b에 도시된 바와 같이, 상기 패터닝된 감광막(13)을 마스크로 하여 콘택식각(Etch)용 화학가스(Chemistry Gas)로 Ar 등의 불활성 기체와 CF4나 CHF3등의 혼합 화학가스를 사용해 상기 반도체 기판(11)의 표면이 노출되도록 상기 절연막(12)을 선택적으로 제거하여 콘택홀(14)을 형성한다.As shown in FIG. 1B, using the patterned photoresist 13 as a mask, an inert gas such as Ar and a mixed chemical gas such as CF 4 or CHF 3 are used as a chemical gas for contact etching. The insulating layer 12 is selectively removed to expose the surface of the semiconductor substrate 11 to form a contact hole 14.
이때, 상기 절연막(12)과 반도체 기판(11)의 선택비를 약 15 : 1정도로 한다.At this time, the selectivity between the insulating film 12 and the semiconductor substrate 11 is about 15: 1.
여기서 미설명한 "A" 부분은 콘택홀(14) 상부의 임계치수이고, "B" 부분은 콘택홀(14) 하부의 임계치수를 나타낸다.A portion "A", which is not described herein, is a critical dimension of the upper portion of the contact hole 14, and a portion "B" represents a critical dimension of the lower portion of the contact hole 14.
한편, 상기 콘택홀(14)을 형성할 때 포토 공정의 해상도 마진을 확보를 위하여 감광막(13)의 두께를 낮춤으로서 상기 절연막(12)을 식각할 때 감광막(13)의 손실이 유발되어 A부분의 임계치수는 B부분의 임계치수보다 커진다.Meanwhile, when the contact hole 14 is formed, a loss of the photoresist layer 13 is induced when the insulating layer 12 is etched by lowering the thickness of the photoresist layer 13 to secure the resolution margin of the photo process. The critical dimension of is larger than the critical dimension of the B part.
또 다른 방법은 상기 감광막(13)의 하부에 하드 마스크(도시되지 않음)를 형성한 후에 상기 반도체 기판(11)의 표면이 노출되도록 상기 절연막(12)을 선택적으로 제거하여 콘택홀(14)을 형성한다.Another method is to form a hard mask (not shown) below the photoresist layer 13, and then selectively remove the insulating layer 12 so that the surface of the semiconductor substrate 11 is exposed to remove the contact hole 14. Form.
도 1c에 도시된 바와 같이, 상기 감광막(13)을 제거하고, 상기 콘택홀(14)을 포함한 반도체 기판(11)의 전면에 플러그(plug)용 금속막을 증착한 후 에치백하여 상기 콘택홀(14)의 내부에 금속 플러그(15)를 형성한다.As shown in FIG. 1C, the photoresist film 13 is removed, a metal film for plug is deposited on the entire surface of the semiconductor substrate 11 including the contact hole 14, and then etched back to form the contact hole ( The metal plug 15 is formed inside the 14.
그러나 상기와 같은 중래 기술의 반도체 소자의 콘택홀 형성방법에 있어서 다음과 같은 문제점이 있었다.However, there have been problems in the method of forming a contact hole of a semiconductor device of the related art as described above.
첫째, 감광막 두께 감소는 콘택홀을 형성하기 위한 식각 공정시 과도한 감광막의 손실을 유발시키어 탑 부위의 임계치수가 증가하여 후속 공정시 오버랩 마진(overlap margin)의 감소를 유발한다.First, reducing the thickness of the photoresist film causes excessive loss of the photoresist film during the etching process for forming the contact hole, thereby increasing the critical dimension of the top portion, thereby reducing the overlap margin in the subsequent process.
둘째, 하드 마스크를 적용하는 경우에는 하드 마스크의 증착 공정과 콘택홀 형성후에 이를 제거하기 위한 식각 등의 추가 공정에 의해 공정이 복잡하다.Second, in the case of applying the hard mask, the process is complicated by an additional process such as an etching process for removing the hard mask and an etching to remove it after forming the contact hole.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 감광막의 과도한 식각에 의한 탑 부위의 임계치수 증가를 방지함과 동시에 공정을 단순화시키도록 한 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact hole in a semiconductor device to simplify the process while preventing the increase in the critical dimension of the top portion due to excessive etching of the photoresist. have.
도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도1A through 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도2A through 2D are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 절연막21 semiconductor substrate 22 insulating film
23 : 감광막 24 : 콘택홀23: photosensitive film 24: contact hole
25 : 금속 플러그 26 : 절연막이 제거된 부분25 metal plug 26 portion where insulating film is removed
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택홀 형성방법은 반도체 기판상에 절연막을 형성하는 단계와, 상기 절연막상에 감광막을 도포한 후 패터닝하여 콘택 영역을 정의하는 단계와, 상기 패터닝된 감광막을 마스크로 이용하여 상기 반도체 기판의 표면이 소정부분 노출되도록 콘택홀을 형성하는 단계와, 상기 감광막을 제거하고 상기 콘택홀의 내부에 금속 플러그를 형성하는 단계와, 상기 콘택홀 탑 부분의 절연막을 표면으로부터 소정 두께만큼 선택적으로 제거하여 콘택홀 탑 부분의 임계치수를 낮추는 단계를 포함하여 형성함을 특징으로 한다.The method for forming a contact hole of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an insulating film on a semiconductor substrate, applying a photosensitive film on the insulating film and then patterning to define a contact region; Forming a contact hole using the patterned photoresist as a mask to expose a surface of the semiconductor substrate, removing the photoresist, and forming a metal plug in the contact hole; And selectively removing the insulating film from the surface by a predetermined thickness to lower the critical dimension of the contact hole top portion.
이하, 첨부된 도면을 참조하여 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택흘 형성방법을 나타낸 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a contact flow of a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(21)상에 절연막(22)을 형성한다.First, as shown in FIG. 2A, an insulating film 22 is formed on the semiconductor substrate 21.
여기서 상기 절연막(22)은 HDP(High Density Plasma) 산화막, TEOS(Tetra Ethyl Ortho Silicate), HTO( High Temperature Oxide), Low-k(HOSP, PTEE, HSg, SiOF) 등의 재료를 단독 또는 복수층으로 형성하고, 그 두께는 5000 ~ 20000Å이다.Here, the insulating layer 22 may be a single layer or a plurality of materials such as HDP (High Density Plasma) oxide film, TEOS (Tetra Ethyl Ortho Silicate), HTO (High Temperature Oxide), Low-k (HOSP, PTEE, HSg, SiOF), etc. And the thickness is 5000-20000 kPa.
이어, 상기 절연막(22)상에 감광막(23)을 도포한 후, 노광 및 현상공정으로 패터닝(Patterning)한다.Subsequently, the photoresist film 23 is coated on the insulating film 22, and then patterned by exposure and development processes.
도 2b에 도시된 바와 같이, 상기 패터닝된 감광막(23)을 마스크로 하여 콘택식각(Etch)용 화학가스(Chemistry Gas)로 Ar 등의 불활성 기체와 CF4나 CHF3등의 혼합 화학가스를 사용해 상기 반도체 기판(21)의 표면이 노출되도록 상기 절연막(22)을 선택적으로 제거하여 콘택홀(24)을 형성한다.As shown in FIG. 2B, using the patterned photoresist 23 as a mask, an inert gas such as Ar and a mixed chemical gas such as CF 4 or CHF 3 are used as a chemical gas for contact etching. The insulating layer 22 is selectively removed to expose the surface of the semiconductor substrate 21 to form a contact hole 24.
이때, 상기 절연막(22)과 반도체 기판(21)의 선택비를 약 15 : 1정도로 한다.At this time, the selectivity between the insulating film 22 and the semiconductor substrate 21 is about 15: 1.
여기서 미설명한 "A" 부분은 콘택홀(24) 상부의 임계치수이고, "B" 부분은 콘택홀(14) 하부의 임계치수를 나타낸다.A portion "A", which is not described herein, is a critical dimension of the upper portion of the contact hole 24, and a portion "B" represents a critical dimension of the lower portion of the contact hole 14.
한편, 상기 콘택홀(24)을 형성할 때 포토 공정의 해상도 마진을 확보를 위하여 감광막(23)의 두께를 낮춤으로서 상기 절연막(22)을 식각할 때 감광막(23)의 손실이 유발되어 A부분의 임계치수는 B부분의 임계치수보다 커진다.Meanwhile, when forming the contact hole 24, a loss of the photoresist layer 23 is induced when the insulating layer 22 is etched by lowering the thickness of the photoresist layer 23 to secure the resolution margin of the photo process. The critical dimension of is larger than the critical dimension of the B part.
도 2c에 도시된 바와 같이, 상기 감광막(23)을 제거하고, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 플러그(plug)용 금속막을 증착한 후 에치백하여 상기 콘택홀(24)의 내부에 금속 플러그(25)를 형성한다.As shown in FIG. 2C, the photoresist film 23 is removed, a metal film for plug is deposited on the entire surface of the semiconductor substrate 21 including the contact hole 24, and then etched back to contact the contact hole ( The metal plug 25 is formed inside the 24.
여기서 상기 금속막은 W, TiN, Ti, WN 중 임의의 하나 물질을 CVD법으로 증착하여 형성한다.The metal film is formed by depositing any one of W, TiN, Ti, and WN by CVD.
도 2d에 도시된 바와 같이, 상기 콘택홀(24)의 탑 임계치수가 커진 부분의 절연막(22)을 CMP(Chemical Mechanical Polishing) 또는 플라즈마 식각법으로 이용하여 임계치수가 커진 A부분을 제거하여 B 부분의 임계치수와 동일하게 한다.As shown in FIG. 2D, the insulating layer 22 of the portion where the top critical dimension of the contact hole 24 is increased is removed by using CMP (Chemical Mechanical Polishing) or plasma etching to remove the portion A having the larger critical dimension, thereby removing the portion B of the portion B. FIG. It is equal to the critical dimension.
여기서 상기 절연막(22)의 식각 두께는 절연막(22)의 두께를 기준으로 하여 30 ~ 35% 이내로 하고, 미설명한 26은 상기 절연막(22)이 제거된 부분이다.Here, the etching thickness of the insulating film 22 is within 30 to 35% based on the thickness of the insulating film 22, and 26, which is not described, is a portion where the insulating film 22 is removed.
한편, 본 발명은 상기 CMP 공정시 정확한 두께 제어를 위해 에치 스톱(etch stop)층을 사용하는 경우 또는 사용하지 않는 경우 모두를 포함하고, 상기 에치 스톱층을 사용하는 경우 SiON 또는 폴리 실리콘을 1000 ~ 3000Å 두께로 형성할 수도 있다.Meanwhile, the present invention includes both the case of using an etch stop layer or the case of not using the etch stop layer for accurate thickness control during the CMP process. It may be formed to a thickness of 3000 kPa.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택홀 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a contact hole in a semiconductor device according to the present invention has the following effects.
즉, 콘택홀 탑 부위의 임계치수 증가로 인한 후속 공정 진행시 오버랩 마진의 감소문제를 하드 마스크 등의 적용 없이 에치백시 타켓의 변경을 통해 개선함으로서 공정을 단순화시킬 수 있고, 전기적 특성 및 신뢰성을 향상시킬 수 있다.In other words, the problem of reducing the overlap margin in the subsequent process due to the increase of the critical dimension of the contact hole top part can be simplified by changing the target during etch back without applying a hard mask, thereby simplifying the process, and improving electrical characteristics and reliability. Can be improved.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100732309B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
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| KR100732309B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
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