KR100527572B1 - Method for forming contact hole - Google Patents
Method for forming contact hole Download PDFInfo
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- KR100527572B1 KR100527572B1 KR10-2000-0083793A KR20000083793A KR100527572B1 KR 100527572 B1 KR100527572 B1 KR 100527572B1 KR 20000083793 A KR20000083793 A KR 20000083793A KR 100527572 B1 KR100527572 B1 KR 100527572B1
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- film
- interlayer insulating
- insulating film
- contact hole
- layer
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 62
- 239000010410 layer Substances 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 18
- 238000004804 winding Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 콘택홀 형성 방법에 관한 것으로, 특히 제 1, 제 2 층간 절연막과 반사방지막을 형성한 후 콘택홀 형성을 위한 감광막 패턴(Pattern)을 형성하므로, 콘택홀 형성 공정시 콘택 탑 CD 와이더닝(Contact Top CD Widening)이 발생되는 상기 제 2 층간 절연막을 희생 절연막으로 제거하여 후속 공정에서 형성될 비트라인(Bit line)이 상기 콘택홀을 커버(Cover)하므로 쇼트(Short) 방지 및 소자의 수율 및 신뢰성을 향상시키는 특징이 있다.The present invention relates to a method for forming a contact hole, and in particular, after forming the first and second interlayer insulating films and the anti-reflection film, a photoresist pattern (Pattern) is formed to form contact holes. (Bit line) to be formed in a subsequent process by removing the second interlayer insulating layer where Contact Top CD Widening is generated as a sacrificial insulating layer covers the contact hole, thereby preventing short and yield of devices. And improved reliability.
Description
본 발명은 콘택홀 형성 방법에 관한 것으로, 특히 희생 절연막으로 층간 절연막을 형성하여 쇼트(Short) 방지 및 소자의 수율 및 신뢰성을 향상시키는 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole, and more particularly, to a method of forming a contact hole for forming an interlayer insulating film with a sacrificial insulating film to prevent short and improve yield and reliability of a device.
종래의 콘택홀 형성 방법은 도 1a에서와 같이, 반도체 기판(11) 상에 다수개의 워드 라인(Word line)(12)들을 형성한다.The conventional contact hole forming method forms a plurality of word lines 12 on the semiconductor substrate 11 as shown in FIG. 1A.
그리고, 상기 워드 라인(12)들을 포함한 전면에 질화막(13)을 형성한 후, 상기 질화막(13) 상에 비피에스지(Boron Phosphor Silicate Glass: BPSG)막으로 구비된 제 1 층간 절연막(14)을 형성한다.After the nitride film 13 is formed on the entire surface including the word lines 12, the first interlayer insulating film 14 provided with a boron Phosphor Silicate Glass (BPSG) film is formed on the nitride film 13. Form.
도 1b에서와 같이, 상기 제 1 층간절연막(14)상에 제 1 감광막을 도포하고, 상기 제 1 감광막을 비트 라인(Bit line) 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1B, a first photosensitive film is coated on the first interlayer insulating film 14, and the first photosensitive film is selectively exposed and developed so as to be removed only at a portion where a bit line contact is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 층간절연막(14)을 선택 식각한 후, 상기 제 1 감광막을 제거한다.The first interlayer dielectric layer 14 is selectively etched using the selectively exposed and developed first photoresist layer, and then the first photoresist layer is removed.
이어, 상기 제 1 층간절연막(14)을 마스크로 상기 질화막(13)을 에치백(Etch-back)하여 제 1 콘택홀(15)을 형성하고 상기 노출된 워드 라인(12) 일측의 반도체 기판(11) 상에 질화막 스페이서(13a)를 형성한다.Subsequently, the nitride layer 13 is etched back using the first interlayer insulating layer 14 as a mask to form a first contact hole 15, and the semiconductor substrate on one side of the exposed word line 12 ( 11) The nitride film spacer 13a is formed on it.
도 1c에서와 같이, 상기 제 1 콘택홀(15)을 포함한 전면에 다결정 실리콘층을 형성한 후, 상기 제 1 층간절연막(14)을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 다결정 실리콘층을 평탄 식각하여 플러그층(16)을 형성한다.As shown in FIG. 1C, after the polycrystalline silicon layer is formed on the entire surface including the first contact hole 15, the polycrystalline silicon layer is flattened by a chemical mechanical polishing method using the first interlayer dielectric layer 14 as an etching end point. By etching, the plug layer 16 is formed.
도 1d에서와 같이, 상기 워드 라인(12)들을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 질화막(13), 제 1 층간절연막(14) 및 플러그층(16)을 평탄 식각한다.As shown in FIG. 1D, the nitride layer 13, the first interlayer insulating layer 14, and the plug layer 16 are etched flat by the chemical mechanical polishing method with the word lines 12 as an etching end point.
그리고, 전면에 제 2 층간절연막(17), 반사방지막(18) 및 제 2 감광막(19)을 순차적으로 형성하고, 상기 제 2 감광막(19)을 비트 라인 콘택이 형성될 부위에민 남도록 선택적으로 노광 및 현상한다.A second interlayer insulating film 17, an antireflection film 18, and a second photosensitive film 19 are sequentially formed on the entire surface, and the second photosensitive film 19 is selectively left to remain at a portion where a bit line contact is to be formed. Exposure and development.
도 1e에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(19)을 마스크로 상기 반사방지막(18)을 선택 식각한다.As shown in FIG. 1E, the anti-reflection film 18 is selectively etched using the selectively exposed and developed second photosensitive film 19 as a mask.
이때 상기 반사방지막(18)의 식각 공정시, 상기 제 2 감광막(19)은 반사방지막(18)과의 식각 선택비가 없기 때문에 상기 제 2 감광막(19)도 식각되어 탑 CD 와이더닝(Top CD Widening)이 발생된다.At this time, during the etching process of the anti-reflection film 18, since the second photosensitive film 19 has no etching selectivity with the anti-reflection film 18, the second photosensitive film 19 is also etched to Top CD Widening ) Is generated.
그리고, 상기 제 2 감광막(19)과 반사방지막(18)을 마스크로 상기 제 2 층간절연막(17)을 선택 식각하여 제 2 콘택홀(20)을 형성한 다음, 상기 제 2 감광막(19)과 반사방지막(18)을 제거한다.The second interlayer dielectric layer 17 is selectively etched using the second photoresist layer 19 and the antireflection layer 18 as a mask to form a second contact hole 20, and then the second photoresist layer 19 The antireflection film 18 is removed.
여기서, 상기 제 2 콘택홀(20) 형성 공정시 상기 제 2 감광막(19)과 반사방지막(18)의 프로파일(Profile)에 영향을 받아 상기 제 2 층간절연막(17)에 콘택 탑 CD 와이더닝(Contact Top CD Widening)이 발생된다.Here, in the process of forming the second contact hole 20, a contact top CD winding on the second interlayer insulating layer 17 may be influenced by the profile of the second photoresist 19 and the anti-reflection film 18. Contact Top CD Widening occurs.
도 2a에서와 같이, 상기 제 2 콘택홀(20)에 콘택 탑 CD 와이더닝이 발생되어 도 2b에서와 같이, 후속 공정에서 형성될 비트 라인(B)이 상기 제 2 콘택홀(20)을 커버(Cover)하지 못한다.As shown in FIG. 2A, a contact top CD widing is generated in the second contact hole 20 so that the bit line B to be formed in a subsequent process as shown in FIG. 2B covers the second contact hole 20. Can't Cover
그러나 종래의 콘택홀 형성 방법은 한 층의 층간 절연막과 반사방지막을 형성한 후 콘택홀 형성을 위한 감광막 패턴을 형성하므로, 콘택홀 형성 공정시 상기 층간 절연막에 콘택 탑 CD 와이더닝이 발생되어 상기 콘택홀의 면적이 증가하기 때문에, 후속 공정에서 형성될 비트라인이 상기 콘택홀을 커버(Cover)하지 못하여 쇼트 발생 및 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.However, the conventional contact hole forming method forms a photoresist pattern for forming a contact hole after forming a layer interlayer insulating film and an antireflection film, and thus, contact top CD widing occurs in the interlayer insulating film during the contact hole forming process. Since the area of the hole increases, the bit line to be formed in a subsequent process does not cover the contact hole, causing short-circuit and yield and reliability of the device.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 제 1, 제 2 층간 절연막과 반사방지막을 형성한 후 콘택홀 형성을 위한 감광막 패턴을 형성하므로, 콘택홀 형성 공정시 콘택 탑 CD 와이더닝이 발생되는 상기 제 2 층간 절연막을 희생 절연막으로 제거하여 후속 공정에서 형성될 비트라인이 상기 콘택홀을 커버하는 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and after forming the first and second interlayer insulating film and the anti-reflective film to form a photoresist pattern for forming a contact hole, a contact top CD winding occurs during the contact hole forming process. It is an object of the present invention to provide a method for forming a contact hole in which a bit line to be formed in a subsequent process is removed by removing the second interlayer insulating layer to be a sacrificial insulating layer.
본 발명의 콘택홀 형성 방법은 플러그층을 갖는 하부 구조물상에 제 1 층간 절연막, 제 2 층간 절연막, 반사방지막 및 감광막을 순차적으로 형성하는 단계, 상기 플러그층 상측의 감광막을 현상하는 단계, 상기 감광막을 마스크로 반사방지막, 제 2 층간 절연막 및 제 1 층간 절연막을 선택 식각하여 상기 제 2 층간 절연막에 콘택 탑 CD 와이더닝이 발생된 콘택홀을 형성하는 단계 및 상기 감광막, 반사방지막 및 제 2 층간 절연막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.The method for forming a contact hole according to the present invention includes sequentially forming a first interlayer insulating film, a second interlayer insulating film, an antireflection film, and a photoresist film on a lower structure having a plug layer, developing the photoresist film on the plug layer, and the photoresist film. Selectively etching the antireflection film, the second interlayer insulating film, and the first interlayer insulating film to form a contact hole in which the contact top CD winding is generated in the second interlayer insulating film; and the photoresist, antireflection film, and second interlayer insulating film Characterized in that it comprises a step of removing.
상기와 같은 본 발명에 따른 콘택홀 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for forming a contact hole according to the present invention as follows.
도 3a 내지 도 3f는 본 발명의 실시 예에 따른 콘택홀 형성 방법을 나타낸 공정 단면도이고, 도 4a와 도 4b는 본 발명의 실시 예에 따른 콘택홀과 비트 라인을 나타낸 사진도이다.3A to 3F are cross-sectional views illustrating a method of forming a contact hole according to an exemplary embodiment of the present invention, and FIGS. 4A and 4B are photographs illustrating a contact hole and a bit line according to an exemplary embodiment of the present invention.
본 발명의 실시 예에 따른 콘택홀 형성 방법은 도 3a에서와 같이, 반도체 기판(31) 상에 다수개의 워드 라인(32)들을 형성한다.In the method for forming a contact hole according to the embodiment of the present invention, as shown in FIG. 3A, a plurality of word lines 32 are formed on the semiconductor substrate 31.
그리고, 상기 워드 라인(32)들을 포함한 전면에 질화막(33)을 형성한 후, 상기 질화막(33)상에 층간 절연막인 제 1 층간절연막(34)을 형성한다.After the nitride film 33 is formed on the entire surface including the word lines 32, a first interlayer insulating film 34, which is an interlayer insulating film, is formed on the nitride film 33.
도 3b에서와 같이, 상기 제 1 층간절연막(34)상에 제 1 감광막을 도포하고, 상기 제 1 감광막을 비트 라인 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 3B, a first photosensitive film is coated on the first interlayer insulating film 34, and the first photosensitive film is selectively exposed and developed so as to be removed only at a portion where a bit line contact is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 층간절연막(34)을 선택 식각한 후, 상기 제 1 감광막을 제거한다.The first interlayer insulating layer 34 is selectively etched using the selectively exposed and developed first photoresist layer, and then the first photoresist layer is removed.
이어, 상기 제 1 층간절연막(34)을 마스크로 상기 질화막(33)을 에치백(Etch-back)하여 제 1 콘택홀(35)을 형성하고 상기 노출된 워드 라인(32) 일측의 반도체 기판(31) 상에 질화막 스페이서(33a)를 형성한다.Subsequently, the nitride layer 33 is etched back using the first interlayer insulating layer 34 as a mask to form a first contact hole 35 and the semiconductor substrate on one side of the exposed word line 32 ( 31 is formed on the nitride film spacer 33a.
도 3c에서와 같이, 상기 제 1 콘택홀(35)을 포함한 전면에 다결정 실리콘층을 형성한 후, 상기 제 1 층간절연막(34)을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 다결정 실리콘층을 평탄 식각하여 플러그층(36)을 형성한다.As shown in FIG. 3C, after the polycrystalline silicon layer is formed on the entire surface including the first contact hole 35, the polycrystalline silicon layer is flattened by a chemical mechanical polishing method using the first interlayer dielectric layer 34 as an etching end point. By etching, the plug layer 36 is formed.
도 3d에서와 같이, 상기 워드 라인(32)들을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 질화막(33), 제 1 층간절연막(34) 및 플러그층(35)을 평탄 식각한다.As shown in FIG. 3D, the nitride layer 33, the first interlayer insulating layer 34, and the plug layer 35 are etched flat by the chemical mechanical polishing method with the word lines 32 as the etching end point.
그리고, 전면에 제 2 층간절연막(37), 제 3 층간절연막(38), 반사방지막(39) 및 제 2 감광막(40)을 순차적으로 형성하고, 상기 제 2 감광막(40)을 비트 라인 콘택이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.A second interlayer insulating film 37, a third interlayer insulating film 38, an antireflection film 39, and a second photosensitive film 40 are sequentially formed on the entire surface, and the second photosensitive film 40 is formed with a bit line contact. It is selectively exposed and developed to remain only in the site to be formed.
여기서, 상기 제 1 층간절연막(34), 제 2 층간절연막(37) 및 제 3 층간절연막(38)은 비피에스지(Boron Phosphor Silicate Glass : BPSG)막, 유에스지(Undoped Silicate Glass: USG)막, 에이치디피(High Density Plasma: HDP)막, 피에스지(Phosphor Silicate Glass: PSG)막 및 실리안(Silian)막 중 선택된 어느 하나를 이용하여 형성할 수 있다.Here, the first interlayer insulating film 34, the second interlayer insulating film 37, and the third interlayer insulating film 38 may include a boron Phosphor Silicate Glass (BPSG) film, an Undoped Silicate Glass (USG) film, It may be formed using any one selected from an HD Density Plasma (HDP) film, a Phosphor Silicate Glass (PSG) film, and a Silian film.
도 3e에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(40)을 마스크로 상기 반사방지막(39)을 30 ∼ 70mT의 압력과 1000 ∼ 2000W의 전원 조건하에 O2, CO 또는 Ar 가스를 사용하여 선택 식각한다.As shown in FIG. 3E, the anti-reflection film 39 is subjected to O 2 , CO, or Ar gas under a pressure of 30 to 70 mT and a power source of 1000 to 2000 W using the selectively exposed and developed second photosensitive film 40 as a mask. Using selective etching.
이때 상기 반사방지막(39)의 식각 공정시, 상기 제 2 감광막(40)은 반사방지막(39)과의 식각 선택비가 없기 때문에 상기 제 2 감광막(40)도 식각되어 탑 CD 와이더닝이 발생된다.At this time, during the etching process of the anti-reflection film 39, since the second photosensitive film 40 has no etching selectivity with the anti-reflection film 39, the second photosensitive film 40 is also etched to generate top CD widing.
그리고, 상기 제 2 감광막(40)과 반사방지막(39)을 마스크로 상기 제 3 층간절연막(38)과 제 2 층간절연막(37)을 선택 식각하여 제 2 콘택홀(41)을 형성한 다음, 상기 제 2 감광막(40)과 반사방지막(39)을 제거한다.Then, the third interlayer insulating film 38 and the second interlayer insulating film 37 are selectively etched using the second photoresist film 40 and the antireflection film 39 to form a second contact hole 41. The second photoresist film 40 and the anti-reflection film 39 are removed.
여기서, 상기 제 3 층간절연막(38)과 제 2 층간절연막(37)을 20 ∼ 70mT의 압력과 1000 ∼ 2000W의 전원 조건하에 C4F8, CH2F2, CO 또는 Ar 가스를 사용하여 식각한다.Here, the third interlayer insulating film 38 and the second interlayer insulating film 37 are etched using C 4 F 8 , CH 2 F 2 , CO, or Ar gas under a pressure of 20 to 70 mT and a power supply condition of 1000 to 2000 W. do.
상기 제 2 콘택홀(41) 형성 공정시 상기 제 2 감광막(40)과 반사방지막(39)의 프로파일에 영향을 받아 상기 제 3 층간절연막(38)에 콘택 탑 CD 와이더닝이 발생된다.In the process of forming the second contact hole 41, the contact top CD widing is generated in the third interlayer insulating film 38 due to the profile of the second photoresist film 40 and the anti-reflection film 39.
도 3f에서와 같이, 상기 제 3 층간절연막(38)을 8 ∼ 10:1의 비를 갖는 NH4F와 순수 HF 혼합액으로 희석된 BOE 용액으로 습식 식각하여 제거한다.As shown in FIG. 3F, the third interlayer insulating film 38 is removed by wet etching with a BOE solution diluted with a mixture of NH 4 F and pure HF having a ratio of 8 to 10: 1.
여기서, 상기 제 3 층간절연막(38)의 습식 식각 공정시 상기 제 3 층간절연막(38)과 제 2 층간절연막(37)과의 식각 비율은 각각 3 ∼ 7 : 1이다.Here, in the wet etching process of the third interlayer insulating film 38, the etching ratio between the third interlayer insulating film 38 and the second interlayer insulating film 37 is 3 to 7: 1, respectively.
상기 제 3 층간절연막(38)의 제거 공정으로 도 4a에서와 같이, 상기 제 2 콘택홀(40)의 콘택 탑 CD 와이더닝이 발생된 부위가 식각되어 도 4b에서와 같이, 후속 공정에서 형성될 비트 라인(B)이 상기 제 2 콘택홀(41)을 커버한다.As a result of removing the third interlayer insulating film 38, as shown in FIG. 4A, a portion where the contact top CD widing occurs in the second contact hole 40 is etched to be formed in a subsequent process as shown in FIG. 4B. The bit line B covers the second contact hole 41.
본 발명의 콘택홀 형성 방법은 제 1, 제 2 층간 절연막과 반사방지막을 형성한 후 콘택홀 형성을 위한 감광막 패턴(Pattern)을 형성하므로, 콘택홀 형성 공정시 콘택 탑 CD 와이더닝이 발생되는 상기 제 2 층간 절연막을 희생 절연막으로 제거하여 후속 공정에서 형성될 비트라인이 상기 콘택홀을 커버하므로 쇼트 방지 및 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the method for forming a contact hole according to the present invention, since the first and second interlayer insulating films and the anti-reflection film are formed, a photoresist pattern is formed to form contact holes. Therefore, the contact top CD widing occurs during the contact hole forming process. Since the bit line to be formed in a subsequent process by removing the second interlayer insulating film with the sacrificial insulating film covers the contact hole, there is an effect of preventing the short and improving the yield and reliability of the device.
도 1a 내지 도 1e는 종래의 콘택홀 형성 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a conventional method for forming a contact hole.
도 2a와 도 2b는 종래의 콘택홀과 비트 라인을 나타낸 사진도2A and 2B are photographic views showing a conventional contact hole and bit line
도 3a 내지 도 3f는 본 발명의 실시 예에 따른 콘택홀 형성 방법을 나타낸 공정 단면도3A to 3F are cross-sectional views illustrating a method of forming a contact hole according to an exemplary embodiment of the present invention.
도 4a와 도 4b는 본 발명의 실시 예에 따른 콘택홀과 비트 라인을 나타낸 사진도4A and 4B are photographic views illustrating contact holes and bit lines according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11, 31 : 반도체 기판 12, 32 : 워드 라인11 and 31: semiconductor substrate 12 and 32: word line
13, 33 : 질화막 13a, 33a : 질화막 스페이서13, 33: nitride film 13a, 33a: nitride film spacer
14, 34 : 제 1 층간절연막 15, 35 : 제 1 콘택홀14, 34: first interlayer insulating film 15, 35: first contact hole
16, 36 : 플러그층 17, 37 : 제 2 층간절연막16, 36: plug layer 17, 37: second interlayer insulating film
18, 39 : 반사방지막 38 : 제 3 층간절연막18, 39: antireflection film 38: third interlayer insulating film
19, 40 : 제 2 감광막 20, 41 : 제 2 콘택홀19, 40: second photosensitive film 20, 41: second contact hole
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