KR100365557B1 - Method for forming plug of semiconductor device - Google Patents
Method for forming plug of semiconductor device Download PDFInfo
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- KR100365557B1 KR100365557B1 KR1020000083840A KR20000083840A KR100365557B1 KR 100365557 B1 KR100365557 B1 KR 100365557B1 KR 1020000083840 A KR1020000083840 A KR 1020000083840A KR 20000083840 A KR20000083840 A KR 20000083840A KR 100365557 B1 KR100365557 B1 KR 100365557B1
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- layer
- forming
- etching
- polycrystalline silicon
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 80
- 238000005530 etching Methods 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims description 17
- 239000011261 inert gas Substances 0.000 claims description 3
- YPSXFMHXRZAGTG-UHFFFAOYSA-N 4-methoxy-2-[2-(5-methoxy-2-nitrosophenyl)ethyl]-1-nitrosobenzene Chemical compound COC1=CC=C(N=O)C(CCC=2C(=CC=C(OC)C=2)N=O)=C1 YPSXFMHXRZAGTG-UHFFFAOYSA-N 0.000 claims description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052736 halogen Inorganic materials 0.000 claims description 2
- 150000002367 halogens Chemical class 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 플러그(Plug) 형성 방법에 관한 것으로, 특히 희생 다결정 실리콘층을 식각하여 콘택홀을 형성하므로, 콘택홀을 형성하기 위한 층간 산화막 식각 공정시 발생되는 워드 라인의 하드 마스크층 손상을 방지하고 플러그 바닥 면적의 감소를 방지하며, 또한 반도체 기판 손상을 방지하여 콘택 저항을 감소시키고 접합 누설 전류를 방지하여 소자의 수율 및 신뢰성을 향상시키는 특징이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a plug of a semiconductor device. In particular, since a contact hole is formed by etching a sacrificial polycrystalline silicon layer, damage to a hard mask layer of a word line generated during an interlayer oxide etching process for forming a contact hole is performed. And the reduction of the plug bottom area, and also to prevent damage to the semiconductor substrate to reduce contact resistance and prevent junction leakage current to improve the yield and reliability of the device.
Description
본 발명은 반도체 소자의 플러그(Plug) 형성 방법에 관한 것으로, 특히 희생 다결정 실리콘층을 식각하여 콘택홀을 형성하므로 소자의 수율 및 신뢰성을 향상시키는 반도체 소자의 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a plug of a semiconductor device, and more particularly, to a method of forming a plug of a semiconductor device to improve contact yield and reliability by forming a contact hole by etching a sacrificial polycrystalline silicon layer.
종래 기술에 따른 반도체 소자의 플러그 형성 방법은 도 1a에서와 같이, 반도체 기판(11)상에 제 1 산화막, 제 1 다결정 실리콘층, 하드 마스크(Hard mask)층인 제 1 질화막(15) 및 제 1 감광막(도시하지 않음)을 순차적으로 형성한다.The plug forming method of the semiconductor device according to the related art is, as shown in FIG. 1A, on the semiconductor substrate 11, the first nitride film 15 and the first nitride film 15, which are a first oxide film, a first polycrystalline silicon layer, and a hard mask layer. A photosensitive film (not shown) is formed sequentially.
그 후, 상기 제 1 감광막을 워드 라인(Word line)이 형성될 부위에만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 질화막(15), 제 1 다결정 실리콘층 및 제 1 산화막을 선택 식각하여 상기 반도체 기판(11)상에 게이트 절연막을 개재한 워드 라인(13)을 형성한 후, 상기 제 1 감광막을 제거한다.Thereafter, the first photoresist film is selectively exposed and developed to remain only in a portion where a word line is to be formed, and then the first nitride film 15 and the first photoresist film are selectively exposed and developed. After the first polycrystalline silicon layer and the first oxide film are selectively etched to form a word line 13 with a gate insulating film on the semiconductor substrate 11, the first photosensitive film is removed.
그리고, 전면에 제 2 질화막을 형성한 후, 상기 제 2 질화막을 에치백(Etch-back)하여 상기 워드 라인(13) 양측의 반도체 기판(11) 상에 제 2 질화막 스페이서(17)를 형성한다.After the second nitride film is formed on the entire surface, the second nitride film is etched back to form a second nitride film spacer 17 on the semiconductor substrate 11 on both sides of the word line 13. .
도 1b에서와 같이, 상기 워드 라인(13)들을 포함한 전면에 층간 산화막(19)을 형성한다.As shown in FIG. 1B, an interlayer oxide film 19 is formed on the entire surface including the word lines 13.
도 1c에서와 같이, 상기 층간 산화막(19)상에 제 2 감광막(21)을 도포한 다음, 상기 제 2 감광막(21)을 비트 라인(Bit line) 콘택과 캐패시터의 하부전극 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1C, after the second photoresist layer 21 is coated on the interlayer oxide layer 19, the second photoresist layer 21 may be a bit line contact and a lower electrode contact of the capacitor. Selectively exposed and developed so as to be removed only.
여기서, 상기 선택적으로 노광 및 현상된 제 2 감광막(21)은 라인 타입(Line type) 자기 정렬 콘택 마스크(Mask) 역할을 한다.Here, the selectively exposed and developed second photoresist layer 21 serves as a line type self-aligned contact mask.
도 1d에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(21)을 마스크로 상기 층간 산화막(19)을 선택 식각하여 다수개의 콘택홀들을 형성한 후, 상기 제 2 감광막(21)을 제거한다.As shown in FIG. 1D, the interlayer oxide layer 19 is selectively etched using the selectively exposed and developed second photoresist 21 to form a plurality of contact holes, and then the second photoresist 21 is removed. do.
도 1e에서와 같이, 상기 콘택홀들을 포함한 전면에 다결정 실리콘층을 형성한다.As shown in FIG. 1E, a polycrystalline silicon layer is formed on the entire surface including the contact holes.
그 후, 상기 제 1 질화막(15)을 식각 종말점으로 상기 층간 산화막(19)과 다결정 실리콘층을 화학 기계 연마 방법에 의해 평탄화하여 플러그층(23)을 형성한다.Thereafter, the interlayer oxide film 19 and the polycrystalline silicon layer are planarized by the chemical mechanical polishing method to form the plug layer 23 at the etching end point of the first nitride film 15.
그러나 종래의 반도체 소자의 플러그 형성 방법은 다음과 같은 이유에 의해 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.However, the plug forming method of the conventional semiconductor device has a problem that the yield and reliability of the device is lowered for the following reasons.
첫째, 콘택홀 형성 공정시 반도체 기판 상측까지 층간 산화막 식각 공정을 진행하므로 워드 라인의 하드 마스크층이 손상된다.First, during the contact hole forming process, the interlayer oxide layer etching process is performed to the upper side of the semiconductor substrate, thereby damaging the hard mask layer of the word line.
둘째, 콘택홀 형성을 위한 층간 산화막 식각 공정시 식각 경사로 플러그 바닥 면적이 줄어 콘택 저항이 크고 상기 플러그 물질인 다결정 실리콘층의 형성 공정시 보이드(Void)가 발생된다.Second, in the interlayer oxide etching process for forming the contact hole, the plug bottom area of the etch ramp is reduced, so that the contact resistance is large and voids are generated during the process of forming the polycrystalline silicon layer, which is the plug material.
셋째, 콘택홀 형성을 위한 층간 산화막 식각 공정시 식각 방지막인 질화막의 손상으로 반도체 기판도 손상되어 콘택 저항이 증가되고 접합 누설 전류가 발생된다.Third, during the interlayer oxide etching process for forming the contact hole, the semiconductor substrate is also damaged by the damage of the nitride film, which is an etch stop layer, thereby increasing the contact resistance and generating a junction leakage current.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 희생 다결정 실리콘층을 식각하여 콘택홀을 형성하므로, 콘택홀을 형성하기 위한 층간 산화막 식각공정시 발생되는 워드 라인의 하드 마스크층 손상을 방지하고 플러그 바닥 면적의 감소를 방지하며, 또한 반도체 기판 손상을 방지하는 반도체 소자의 플러그 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, so that the contact hole is formed by etching the sacrificial polycrystalline silicon layer, thereby preventing damage to the hard mask layer of the word line generated during the interlayer oxide etching process for forming the contact hole and It is an object of the present invention to provide a method for forming a plug of a semiconductor device which prevents the reduction of the floor area and also prevents damage to the semiconductor substrate.
도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 플러그 형성 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to the related art.
도 2a 내지 도 2f는 본 발명의 실시 예에 따른 반도체 소자의 플러그 형성 방법을 나타낸 공정 단면도2A to 2F are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 31 : 반도체 기판 13, 33 : 워드 라인11 and 31: semiconductor substrate 13 and 33: word line
15, 35 : 제 1 질화막 17 : 제 2 질화막 측벽15, 35: first nitride film 17: second nitride film sidewall
37 : 제 2 질화막 39 : 제 2 다결정 실리콘층37: second nitride film 39: second polycrystalline silicon layer
21, 41 : 제 2 감광막 19, 43 : 층간 산화막21, 41: second photosensitive film 19, 43: interlayer oxide film
23, 45 : 플러그층23, 45: plug layer
본 발명의 반도체 소자의 플러그 형성 방법은 기판 상에 하드 마스크층이 구비되는 다수개의 워드 라인들을 형성하는 단계, 전면에 식각 방지막과 희생 도전층을 순차적으로 형성하는 단계, 상기 희생 도전층을 선택 식각하여 콘택홀이 형성될 부위를 정의하는 단계, 전면에 층간 절연막을 형성하고, 상기 희생 도전층을 식각 종말점으로 상기 층간 절연막을 전면 식각하는 단계, 상기 희생 도전층을 제거하고, 상기 식각 방지막을 에치백하여 콘택홀을 형성하는 단계, 상기 콘택홀을 포함한 전면에 도전층을 형성하는 단계 및 상기 하드 마스크층을 식각 종말점으로 평탄화 공정을 진행하여 플러그층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of forming a plug of a semiconductor device according to an embodiment of the present invention, the method may include forming a plurality of word lines having a hard mask layer on a substrate, sequentially forming an etch stop layer and a sacrificial conductive layer on an entire surface thereof, and selectively etching the sacrificial conductive layer. Defining a region where a contact hole is to be formed, forming an interlayer insulating film on the entire surface, etching the entire interlayer insulating film with the sacrificial conductive layer as an etching endpoint, removing the sacrificial conductive layer, and removing the etch stop layer. Forming a contact layer by forming a plug layer by forming a plug layer by forming a contact layer by forming a contact layer, forming a conductive layer on the entire surface including the contact hole, and planarizing the hard mask layer to an etching end point. .
상기와 같은 본 발명에 따른 반도체 소자의 플러그 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the plug forming method of the semiconductor device according to the present invention as described above will be described in detail with reference to the accompanying drawings.
본 발명의 실시 예에 따른 반도체 소자의 플러그 형성 방법은 도 2a에서와 같이, 소자분리 영역에 소자분리막(32)이 형성되고 주변 영역이 정의된 반도체 기판(31)상에 제 1 산화막, 제 1 다결정 실리콘층, 하드 마스크층인 제 1 질화막(35) 및 제 1 감광막(도시하지 않음)을 순차적으로 형성한다.In the method of forming a plug of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, a first oxide film and a first oxide film are formed on a semiconductor substrate 31 on which a device isolation film 32 is formed in a device isolation region and a peripheral region is defined. A polycrystalline silicon layer, a first nitride film 35 which is a hard mask layer, and a first photosensitive film (not shown) are sequentially formed.
그 후, 상기 제 1 감광막을 워드 라인이 형성될 부위에만 남도록 선택적으로노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 질화막(35), 제 1 다결정 실리콘층 및 제 1 산화막을 선택 식각하여 상기 반도체 기판(31)상에 게이트 절연막을 개재한 워드 라인(33)을 형성한 후, 상기 제 1 감광막을 제거한다.Thereafter, the first photoresist film is selectively exposed and developed to remain only at the site where the word line is to be formed, and then the first nitride film 35 and the first polycrystalline silicon layer are formed using the selectively exposed and developed first photoresist film as a mask. And selectively etching the first oxide layer to form a word line 33 on the semiconductor substrate 31 with a gate insulating layer thereon, and then removing the first photosensitive layer.
그리고, 전면에 제 2 질화막(37)을 형성한다.Then, the second nitride film 37 is formed on the entire surface.
도 2b에서와 같이, 상기 제 2 질화막(37)상에 제 2 다결정 실리콘층(39)을 형성한다.As shown in FIG. 2B, a second polycrystalline silicon layer 39 is formed on the second nitride film 37.
도 2c에서와 같이, 상기 제 2 다결정 실리콘층(39)상에 제 2 감광막(41)을 도포하고, 상기 제 2 감광막(41)을 비트 라인 콘택과 캐패시터의 하부 전극 콘택이 형성될 부위 그리고 주변 영역에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 2C, a second photoresist layer 41 is coated on the second polycrystalline silicon layer 39, and the second photoresist layer 41 is formed around the bit line contact and the lower electrode contact of the capacitor. It is selectively exposed and developed to remain only in the area.
여기서, 상기 선택적으로 노광 및 현상된 제 2 감광막(41)은 라인 타입 마스크 역할을 한다.Here, the selectively exposed and developed second photoresist layer 41 serves as a line type mask.
그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막(41)을 마스크로 상기 제 2 다결정 실리콘층(39)을 선택 식각한다.The second polycrystalline silicon layer 39 is selectively etched using the selectively exposed and developed second photosensitive film 41 as a mask.
도 2d에서와 같이, 상기 제 2 감광막(41)을 제거하고, 상기 제 2 다결정 실리콘층(39)을 포함한 전면에 층간 절연막(43)을 형성한다.As shown in FIG. 2D, the second photosensitive film 41 is removed, and an interlayer insulating film 43 is formed on the entire surface including the second polycrystalline silicon layer 39.
그리고, 상기 제 2 다결정 실리콘층(39)을 식각 종말점으로 상기 층간 절연막(43)을 에치백한다.The interlayer insulating layer 43 is etched back using the second polycrystalline silicon layer 39 as an etching end point.
도 2e에서와 같이, 상기 제 2 다결정 실리콘층(39)을 제거한다.As shown in FIG. 2E, the second polycrystalline silicon layer 39 is removed.
여기서, 상기 제 2 다결정 실리콘층(39)을 Cl2, BCl2, HCl 또는 HBr의 할로겐 가스를 포함하는 가스를 제 1 식각 가스로 사용하여 식각하거나, O2, CO, CO2, NO, NO2또는 SO2의 산소(O)를 포함하는 가스를 제 2 식각 가스로 사용하여 식각한다.Here, the second polycrystalline silicon layer 39 is etched using a gas containing a halogen gas of Cl 2 , BCl 2 , HCl or HBr as the first etching gas, or O 2 , CO, CO 2 , NO, NO Etching is performed using a gas containing oxygen (O) of 2 or SO 2 as the second etching gas.
또한, 상기 제 2 다결정 실리콘층(39)을 NH3, N2H2, C2H2, CH4, C2H4또는 H2의 수소를 포함하는 가스또는 N2가스를 제 3 식각 가스로 사용하거나 불활성 가스를 혼합한 제 4 식각 가스를 사용하여 식각하거나, 또한 상기 제 1, 제 2, 제 3 , 제 4 식각 가스를 혼합한 가스를 사용하여 식각한다.In addition, the second polycrystalline silicon layer 39 may include NH 3 , N 2 H 2 , C 2 H 2 , CH 4 , C 2 H 4, or a gas containing hydrogen of H 2 , or a N 2 gas as a third etching gas. Etching may be performed using a fourth etching gas containing a mixture of inert gases or an inert gas, or using a gas mixture of the first, second, third and fourth etching gases.
도 2f에서와 같이, 상기 제 2 질화막(37)을 에치백하여 콘택홀을 형성하고 상기 노출된 워드 라인(33) 측벽의 반도체 기판(31)상에 제 2 질화막 스페이서(37a)를 형성한다.As shown in FIG. 2F, the second nitride layer 37 is etched back to form a contact hole, and a second nitride layer spacer 37a is formed on the semiconductor substrate 31 on the exposed sidewall of the word line 33.
그리고, 상기 콘택홀을 포함한 전면에 제 3 다결정 실리콘층을 형성하고, 상기 제 1 질화막(35)을 식각 종말점으로 상기 제 3 다결정 실리콘층, 층간 산화막(43) 및 제 2 질화막(37)을 화학 기계 연마 방법 또는 에치백 공정에 의해 평탄화하여 플러그층(45)을 형성한다.A third polycrystalline silicon layer is formed on the entire surface including the contact hole, and the third polycrystalline silicon layer, the interlayer oxide layer 43, and the second nitride layer 37 are chemically formed using the first nitride layer 35 as an etch endpoint. The plug layer 45 is formed by planarization by a mechanical polishing method or an etch back process.
본 발명의 반도체 소자의 플러그 형성 방법은 희생 다결정 실리콘층을 식각하여 콘택홀을 형성하므로 다음과 같은 이유에 의해 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.The plug forming method of the semiconductor device of the present invention forms contact holes by etching the sacrificial polycrystalline silicon layer, thereby improving the yield and reliability of the device due to the following reasons.
첫째, 콘택홀을 형성하기 위한 층간 산화막 식각 공정시 발생되는 워드 라인의 하드 마스크층 손상을 방지한다.First, the damage of the hard mask layer of the word line generated during the interlayer oxide etching process for forming the contact hole is prevented.
둘째, 콘택홀 형성을 위한 층간 산화막 식각 공정시 발생되는 플러그 바닥 면적의 감소를 방지한다.Second, the plug bottom area generated during the interlayer oxide etching process for forming the contact hole is prevented from being reduced.
셋째, 반도체 기판 손상을 방지하여 콘택 저항을 감소시키고 접합 누설 전류를 방지한다.Third, it prevents damage to the semiconductor substrate to reduce contact resistance and prevent junction leakage current.
Claims (6)
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