KR100474541B1 - Bit line formation method of semiconductor device - Google Patents
Bit line formation method of semiconductor device Download PDFInfo
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- KR100474541B1 KR100474541B1 KR1019970081332A KR19970081332A KR100474541B1 KR 100474541 B1 KR100474541 B1 KR 100474541B1 KR 1019970081332 A KR1019970081332 A KR 1019970081332A KR 19970081332 A KR19970081332 A KR 19970081332A KR 100474541 B1 KR100474541 B1 KR 100474541B1
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 24
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
본 발명은 반도체소자의 비트라인 형성방법에 관한 것으로, 하부절연층이 형성된 반도체기판 상부에 비트라인용 도전체와 텅스텐 실리사이드막의 적층구조를 형성하고 상기 텅스텐 실리사이드막 상부에 하드마스크용 절연막을 형성한 다음, 상기 절연막 상부에 비트라인용 감광막패턴을 형성하고 상기 감광막패턴을 마스크로하여 상기 절연막을 식각함으로써 하드마스크를 형성한 다음, 상기 감광막패턴을 마스크로하여 텅스텐 실리사이드막을 제1등방성식각하고 상기 감광막패턴을 제거한 다음, 상기 하드마스크를 마스크로 하여 상기 도전체를 제2등방성식각함으로써 비트라인을 형성하여 후속공정으로 형성되는 저장전극 콘택과의 마진을 증가시킬 수 있어 소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다. The present invention relates to a method for forming a bit line of a semiconductor device, comprising forming a laminate structure of a bit line conductor and a tungsten silicide layer on a semiconductor substrate on which a lower insulating layer is formed, and forming an insulating film for a hard mask on the tungsten silicide layer. Next, a bit line photoresist pattern is formed on the insulating layer, and a hard mask is formed by etching the insulating layer using the photoresist pattern as a mask, and then a tungsten silicide layer is first isotropically etched using the photoresist pattern as a mask and the photoresist is formed. After removing the pattern, the second mask isotropically etched using the hard mask as a mask to form a bit line to increase a margin with a storage electrode contact formed in a subsequent process, thereby improving device characteristics and reliability. It is a technology that can.
Description
본 발명은 반도체소자의 비트라인 형성방법에 관한 것으로, 특히 감광막을 이용하지 않고 절연막을 하드마스크 ( hard mask ) 로 형성한 다음, 이를 이용하여 등방성식각공정을 형성하는 공정으로 비트라인을 형성하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a bit line of a semiconductor device. In particular, a technique of forming a bit line by forming an insulating film as a hard mask without using a photoresist film and then forming an isotropic etching process using the same as a hard mask. It is about.
고집적화되는 반도체 메모리 소자의 제조공정시 저장전극과 비트라인의 접속으로 인한 소자의 특성 저하를 방지하기 위하여 저장전극 콘택과 비트라인의 중첩마진을 확보할 필요성이 있다.In the manufacturing process of highly integrated semiconductor memory devices, there is a need to secure overlapping margins between the storage electrode contacts and the bit lines in order to prevent deterioration of device characteristics due to the connection between the storage electrodes and the bit lines.
일반적으로, 중첩마진을 확보하기 위하여 실시되는 공정은, 리소그래피 ( lithography ) 에서 중첩마진을 업그레이트 ( upgrade ) 하거나 새로운 정렬키 리딩 ( align key reading ) 방법을 개방하는 방법이 있으나, 그 한계가 이미 노출되어 있다. In general, the process performed to secure the overlap margin includes a method of upgrading the overlap margin in lithography or opening a new align key reading method, but the limitation is already exposed. It is.
또한, 비트라인을 질화막으로 캐핑 ( capping ) 하여 질화막 대 산화막의 고선택비 기술을 이용하는 저장전극 콘택방법 역시 비트라인에 적용된 하드 마스크의 수직 식각파일을 얻기가 어렵고, 얻는다 해도 기본적으로 비트라인 끝부분과 저장전극 콘택과의 거리가 매우 가깝기 때문에 비트라인과 저장전극 콘택에 쇼트될 수 있어 반도체소자의 절연특성 및 동작 특성이 열화되어 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.In addition, the storage electrode contact method using a high selectivity technique of nitride to oxide film by capping the bit line with the nitride film is also difficult to obtain a vertical etching file of the hard mask applied to the bit line. Since the distance between the storage electrode contact and the storage electrode contact is very close, it may short-circuit to the bit line and the storage electrode contact, thereby deteriorating insulation and operating characteristics of the semiconductor device, making it difficult to integrate the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 비트라인의 끝부분과 저장전극 콘택과의 거리를 증가시켜 저장전극과의 접속을 방지하여 소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 비트라인 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by increasing the distance between the end of the bit line and the storage electrode contact to prevent the connection of the storage electrode to improve the characteristics and reliability of the device It is an object of the present invention to provide a bit line forming method.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 비트라인 형성방법은, In order to achieve the above object, a method of forming a bit line of a semiconductor device according to the present invention,
하부절연층이 형성된 반도체기판 상부에 비트라인용 도전체와 텅스텐 실리사이드막의 적층구조를 형성하는 공정과,Forming a stacked structure of a bit line conductor and a tungsten silicide film on the semiconductor substrate on which the lower insulating layer is formed;
상기 텅스텐 실리사이드막 상부에 하드마스크용 절연막을 형성하는 공정과,Forming an insulating film for a hard mask on the tungsten silicide film;
비트라인 마스크를 이용하여 상기 비트라인용 도전체, 텅스텐 실리사이드막, 하드마스크 및 감과막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of the bit line conductor, the tungsten silicide layer, the hard mask, and the photosensitive film pattern using a bit line mask;
상기 감광막패턴 및 하드마스크를 마스크로 하여 상기 텅스텐 실리사이드막을 제1등방성식각하는 공정과,First isotropically etching the tungsten silicide layer using the photoresist pattern and the hard mask as masks;
상기 감광막패턴을 제거하고 상기 하드마스크를 마스크로 하여 상기 도전체를 제2등방성식각하는 공정을 포함하는 것을 특징으로 한다.And removing the photoresist pattern and performing a second isotropic etching of the conductor using the hard mask as a mask.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, On the other hand, the principle of the present invention for achieving the above object,
비트라인용 도전체와 텅스텐 실리사이드막의 적층구조 상부에 산화막이나 질화막으로 하드마스크를 형성하고 이를 이용한 제1등방성식각공정과 제2등방성식각공정으로 상기 적층구조를 식각하여 후속 공정으로 형성되는 저장전극 콘택플러그과의 절연마진을 확보할 수 있는 비트라인을 형성할 수 있도록 하는 것이다.A storage electrode contact is formed by forming a hard mask on the stacked structure of the bit line conductor and the tungsten silicide layer using an oxide film or a nitride film and etching the stacked structure by using a first isotropic etching process and a second isotropic etching process using the same. It is to be able to form a bit line to secure the insulation margin with the plug.
여기서, 상기 제1등방성식각공정은 염소가스와 산소가스를 이용하여 텅스텐 실리사이드막을 식각하되, 상기 산소가스의 부분압력이 높을수록 텅스텐 실리사이드막의 식각비가 무한대적으로 증가하는 반면에 다결정실리콘막의 식각비가 급격하게 감소되는 현상을 이용하여 실시하고,Here, in the first isotropic etching process, the tungsten silicide layer is etched using chlorine gas and oxygen gas, but as the partial pressure of the oxygen gas increases, the etching ratio of the tungsten silicide layer is infinitely increased while the etching ratio of the polysilicon film is rapidly increased. Using a phenomenon that is reduced to
상기 제2등방성식각공정은 염소가스와 HBr 가스를 이용하여 다결정실리콘막을 식각하되, 상기 HBr 가스의 부분 압력이 증가할 수록 텅스텐 실리사이드막의 식각비는 급격히 감소되는 반면에 다결정실리콘막의 식각비가 무한대적으로 증가하는 현상을 이용하여 실시하는 것이다. The second isotropic etching process uses the chlorine gas and the HBr gas to etch the polysilicon film, and as the partial pressure of the HBr gas increases, the etching ratio of the tungsten silicide film is rapidly decreased while the etching ratio of the polysilicon film is infinite. This is done by using an increasing phenomenon.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4 는 본 발명의 실시예에 따른 반도체소자의 비트라인 형성방법을 도시한 단면도이다.1 to 4 are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(도시안됨) 상부에 소자분리막 및 워드라인을 형성하고 그 상부를 평탄화시키는 하부절연층(11)을 형성한다.First, a device isolation layer and a word line are formed on a semiconductor substrate (not shown), and a lower
이때, 상기 하부절연층(11)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 와 같이 유동성이 우수한 절연물질로 형성한다.In this case, the lower
그 다음에, 상기 하부절연층(11) 상부에 다결정실리콘막(13)과 실리사이드막(15)을 순차적으로 적층한다. 여기서, 상기 실리사이드막(15)은 텅스텐 실리사이드를 말한다.Next, the
그리고, 상기 실리사이드막(15) 상부에 하드 마스크로 사용될 산화막(17)을 일정두께 형성한다. 이때, 상기 산화막(17)은 질화막으로 형성할 수도 있다. (도 1)In addition, an
그 다음에, 비트라인 마스크(도시안됨)를 이용한 노광 및 현상공정으로 상기 산화막(17) 상부에 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 상기 산화막(17)을 패터닝하여 산화막(17)패턴, 즉 하드마스크를 형성한다. 이때, 상기 산화막(17)의 패터닝공정은 CF4, CHF3 등의 가스를 이용하여 실시한다. (도 2)Subsequently, a photoresist pattern (not shown) is formed on the
그 다음에, 상기 감광막패턴과 산화막(17)패턴을 마스크로하여 상기 실리사이드막(15)을 제1등방성식각하여 상기 하드마스크인 산화막(17) 패턴의 하부로 언더컷(19)을 형성한다.Next, the
이때, 상기 제1등방성식각공정은 Cl2, O2 가스를 이용하여 실시하되, O2 부분 압력이 5 % 이상인 가스 캐미스트리를 이용하고 래디칼 밀도 ( radical density ) 를 증가시키기 위하여 소오스 전력 ( source power ) 을 최고치의 30 ∼ 80 % 정도로 하여 실시한다.In this case, the first isotropic etching process is performed using Cl 2 , O 2 gas, source gas (source power) in order to increase the radical density using a gas chemistry with O 2 partial pressure of 5% or more ) To about 30 to 80% of the highest value.
그 다음에, 상기 감광막패턴을 제거한다. (도 3)Then, the photosensitive film pattern is removed. (Figure 3)
그리고, 상기 하드마스크인 산화막(17)패턴을 마스크로하여 상기 다결정실리콘막(13)을 제2등방성식각공정을 실시한다. 이때, 제2등방성식각공정은, 염소가스와 HBr 가스를 사용하여 실시하되, 상기 텅스텐 실리사이드막(15)의 식각없이 실시하기 위하여 HBr 의 부분 압력을 5 % 이상으로 유지하여 실시한다. (도 4)The
후속공정으로 상기 하드마스크인 산화막(17)패턴을 제거하여 비트라인(21)을 형성한다.Subsequently, the
여기서, 상기 산화막(17)패턴을 제거하기 않고 후속공정을 실시할 수도 있다.Here, the subsequent process may be performed without removing the
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 비트라인 형성방법은, 비트라인의 폭을 감소시켜 후속공정으로 형성되는 저장전극 콘택공정시 상기 비트라인과의 접속을 방지할 수 있도록 마진을 확보함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다. As described above, in the method of forming a bit line of a semiconductor device according to the present invention, a margin is prevented so as to prevent the connection with the bit line during the storage electrode contact process formed in a subsequent process by reducing the width of the bit line. There is an effect that can improve the characteristics and reliability of the semiconductor device.
도 1 내지 도 4 는 본 발명의 실시예에 반도체소자의 비트라인 형성방법을 도시한 단면도.1 to 4 are cross-sectional views showing a method for forming a bit line of a semiconductor device in an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 하부절연층 13 : 다결정실리콘11: lower insulating layer 13: polysilicon
15 : 실리사이드막 17 : 하드마스크15: silicide film 17: hard mask
19 : 언더컷 ( under cut ) 21 : 비트라인19: under cut 21: bit line
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| KR100629269B1 (en) | 2004-11-05 | 2006-09-29 | 삼성전자주식회사 | Semiconductor devices having a trench in a side portion of a line pattern and methods of forming thereof |
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