KR100403328B1 - Forming method for self aligned contact of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a self-aligned contact of a semiconductor device,

A gate electrode including a first mask oxide layer and an insulating layer spacer is formed on a semiconductor substrate, an organic low-k layer is formed on an entire surface, and a second mask oxide layer is formed on the organic low-k layer. And forming a contact hole by plasma etching the second mask oxide layer and the organic low dielectric layer using a contact mask exposing a predetermined region of the semiconductor substrate, and forming an undercut under the second mask oxide layer. A contact pad is formed by a planar etching process in which a polysilicon for embedding contact pad is formed on the entire surface and the organic low dielectric layer is exposed, and then the interlayer insulating layer which removes the organic low dielectric layer and exposes a predetermined region of the contact pad. High etching selectivity as contact margin can be easily secured during contact process It is a technology that can easily perform the process without requiring a difference, thereby improving the productivity of the semiconductor device.

Description

Forming method for self aligned contact of semiconductor device

The present invention relates to a method for forming a self-aligned contact of a semiconductor device, and in particular, to form a contact pad easily using an organic low-k dielectric layer and to facilitate the contact process in a subsequent process accordingly, thereby improving productivity of the semiconductor device. It is about technology that can be improved.

In general, a refresh time, which is an important characteristic of a memory device, is mainly determined by a leakage current generated by damaging the drain during a storage electrode contact process connecting the storage electrode node and the drain of the transistor.

In the current exposure technology, when forming a contact hole up to 16 M DRAM, a device can be formed without a poor insulation with the conductive layer of the sidewall of the contact hole. However, as the device is highly integrated, the unit cell size is reduced. As a result, the gap between the contact hole and the conductive layer is narrowed.

In order to form a narrowed contact hole as described above, the size of the contact should be reduced, and for this purpose, it was solved to some extent by changing the exposure method or changing the mask. In addition, self-aligned contact (hereafter referred to as SAC) was solved.

On the other hand, the most popular among the SAC process is a self-aligned contact (nitride barrier SAC, hereinafter referred to as NBSAC) process using a nitride film as an etching barrier during the oxide film etching process.

The NBSAC process is roughly classified into an oxide layer etching process and a nitride layer etching process.

In the oxide film etching process, a large amount of C ₃ F ₈ or C ₄ F ₈ gas, which is a polymer induced gas, is used to obtain a high etching selectivity with respect to the nitride film. The C ₃ F ₈ or C ₄ F ₈ gas may induce a large number of polymers to secure an etching selectivity for the nitride film, but there is a problem that the etch stop is not completely removed in the contact hole.

Here, the selectivity and the etch stop with respect to the nitride film are opposite to each other, which causes the process window to be narrowed and the reproducibility deteriorates.

In order to extend the flow window, a condition in which polymer is generated is used. In this case, the thickness of the nitride film must be increased. However, if the thickness of the nitride film is increased, the contact area is reduced, so that the nitride film should be isotropically etched to compensate for this.

In addition, since the oxide layer under the nitride layer is used as an electrical insulating layer, the nitride layer has to be as little as possible to damage the oxide layer. A high etching selectivity difference with respect to the oxide layer is required, and the portion where the semiconductor substrate is exposed when the oxide layer is etched in the peripheral circuit area is required. There is a need for a condition that minimizes the etching of the semiconductor substrate.

However, ion induced etcher, which is one of the conventional nitride film etching equipments, cannot obtain high etching selectivity for isotropic etching and oxide film.

In addition, the radical etcher, which has recently been in the spotlight, uses gases such as NF ₃ , CF ₄ , SF _6, etc., so it is possible to secure a high etching selectivity for isotropic etching and oxide films, but silicon as a semiconductor substrate It is not possible to secure high etch selectivity.

Because the most influential factor for etching is etchant, but in the case where the main etchant is a fluorine series such as NF ₃ , CF ₄ , SF _6, etc., the radical etching equipment is an oxide film or a nitride film. Since both silicon and silicon can be etched, the bonding force of the thin film determines the etching rate. That is, when the bonding force is in the order of oxide film> nitride film> silicon, since the etching of silicon proceeds fastest, it is impossible to secure a high etching selectivity with respect to silicon during the nitride film etching process.

As a result, the NBSAC process according to the prior art has a problem that it is difficult to proceed the process in terms of securing high selectivity, and even if the selectivity is secured, it is difficult to secure the process margin and thus it is difficult to apply to the actual production process.

In order to solve the above problems of the prior art, by performing a pad poly SAC process by using an organic low-k layer instead of the conventional SAC process using a nitride layer as an etch barrier layer. It is an object of the present invention to provide a self-aligned contact method of a semiconductor device capable of easily mass-producing a SAC process.

1A to 1C are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11: semiconductor substrate 13: conductor

15: first mask oxide film 17: insulating film spacer

19 organic low dielectric layer 21 second mask oxide film

23 photosensitive film pattern 25: undercut

27: contact pad 29: interlayer insulating film

50: first contact hole 60: second contact hole

Self-aligned contact forming method of a semiconductor device according to the present invention to achieve the above object,

Forming a gate electrode having a first mask oxide film and an insulating film spacer on the semiconductor substrate;

Forming an organic low dielectric layer over the entire surface,

Forming a second mask oxide film on the organic low dielectric layer;

Forming a contact hole by plasma etching the second mask oxide layer and the organic low dielectric layer using a contact mask exposing a predetermined region of the semiconductor substrate, and forming an undercut under the second mask oxide layer;

Forming a contact pad for embedding the undercut on the entire surface thereof;

Forming a contact pad by a planarization etching process exposing the organic low dielectric layer;

And removing the organic low dielectric layer and forming an interlayer insulating film exposing a predetermined region of the contact pad.

On the other hand, the principle of the self-aligned contact forming method of a semiconductor device for achieving the above object,

In the organic low dielectric layer etching process, a lateral under cut is formed, polysilicon is deposited, a CMP process is performed, the organic low dielectric layer, a mask oxide layer is removed, an ILD oxide layer is removed, and a SAC process is performed to obtain a pad poly SAC. In the SAC process formed on the pad poly, the lithography process margin is secured by the length of the side undercut formed during the organic low dielectric layer etching process.

In addition, by controlling the process conditions during the organic low-k dielectric layer etching process to control the depth of the undercut to facilitate the subsequent process margin.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of forming self-aligned contacts in a semiconductor device according to an embodiment of the present invention.

First, a conductor 13 for a gate electrode is formed on the semiconductor substrate 11, and a first mask oxide film 15 is formed on the semiconductor substrate 11.

The first mask oxide film 15 and the conductor 13 are etched by a photolithography process using a gate electrode mask to etch the conductor 13 and the first mask oxide film on the active region of the semiconductor substrate 11. A laminated pattern of 15 is formed.

Next, an insulating film spacer 17 is formed on the stacked pattern sidewalls. In this case, the insulating film spacers 17 are formed by depositing an insulating film having a predetermined thickness on the entire surface and anisotropically etching it by the deposited thickness.

Then, an organic low dielectric layer 19 is formed on the entire surface and planarized.

In this case, the organic low dielectric layer 19 is a material having a polymer form and having a lower dielectric constant than the oxide film, and may withstand high temperatures at which the semiconductor manufacturing process may be performed, have high affinity with the oxide film, and have excellent thermal stability. . Examples of the organic low dielectric layer 19 may include materials having trade names such as flare and silk, and etching may be better than that of the first and second mask oxide layers 15 and 21 and the insulating layer spacer 17. Has characteristics.

Next, a second mask oxide film 21 is formed on the organic low dielectric layer 19 at a predetermined thickness.

The photoresist pattern 23 is formed on the second mask oxide layer 21. In this case, the photoresist pattern 23 is formed by an exposure and development process using a contact mask (not shown). (FIG. 1A)

Subsequently, the second mask oxide layer 21 and the organic low dielectric layer 19 are etched by an isotropic etching process using the photoresist pattern 23 as a mask to form a lower portion of the second mask oxide layer 21 under the second mask oxide layer 21. An undercut 25 is formed between the oxide film 21 and the first mask oxide film 15, and a first contact hole 50 exposing a predetermined region of the semiconductor substrate 11 is formed.

In this case, the isotropic etching process may be performed by a plasma etching process using oxygen and nitrogen gas, but the etching process of the organic low dielectric layer 19 may be performed by using an inert gas such as argon or helium to improve the stability of the plasma. have.

Here, the undercut may be formed by adjusting the conditions using the anisotropic etching process instead of the anisotropic etching process.

Meanwhile, the photoresist pattern 23 may be removed during the plasma etching process of the organic low dielectric layer 19, and may be removed by a separate etching process if remaining. (FIG. 1B)

Then, polysilicon filling the first contact hole 50 is formed on the entire surface and etched until the organic low dielectric layer 19 is exposed to secure a wider margin than the first contact hole 50. The contact pad 27 which can be formed is formed.

In this case, the polysilicon may be carried out in an in-shute process to facilitate doping.

Then, the second pad oxide layer 21 and the contact pad polysilicon deposited thereon are planarized and etched until the organic low dielectric layer 19 is exposed, and then contact pads are connected to predetermined regions of the semiconductor substrate 11. (27) is formed.

In this case, the planarization etching process is performed by a CMP process or an etch back process.

Then, an interlayer insulating film 29 is formed over the entire surface and planarized.

Next, the second insulating hole 60 exposing the contact pad 27 is formed by etching the interlayer insulating layer 29 by a photolithography process using the contact mask.

The polymer formed in the second contact hole 60 is removed using dry plasma. (FIG. 1C)

As described above, in the self-aligned contact forming method of a semiconductor device according to the present invention, a contact pad is easily formed using an organic low dielectric layer and a contact process is performed in a subsequent process to minimize damage to a semiconductor substrate and to facilitate the contact process. The contact process can be performed to increase the productivity of the semiconductor device.

Claims (6)

Forming a gate electrode having a first mask oxide film and an insulating film spacer on the semiconductor substrate; Forming an organic low dielectric layer over the entire surface, Forming a second mask oxide film on the organic low dielectric layer; Forming a contact hole by plasma etching the second mask oxide layer and the organic low dielectric layer using a contact mask exposing a predetermined region of the semiconductor substrate, and forming an undercut under the second mask oxide layer; Forming a contact pad for embedding the undercut on the entire surface thereof; Forming a contact pad by a planarization etching process exposing the organic low dielectric layer; Removing the organic low dielectric layer and forming an interlayer insulating film exposing a predetermined region of the contact pad. The method of claim 1, The plasma etching process may be performed using a plasma formed of oxygen gas and nitrogen gas during the etching process of the second mask oxide layer and using an inert gas such as argon or helium during the etching process of the organic low dielectric layer. Self-aligned contact forming method of a semiconductor device. The method according to claim 1 or 2, The etching process of the organic low dielectric layer is an isotropic etching process is a self-aligned contact forming method of a semiconductor device. The method of claim 3, wherein The method of forming a self-aligned contact of a semiconductor device, characterized in that to adjust the depth of the undercut by adjusting the etching conditions during the etching process of the organic low-k dielectric layer to adjust the contact margin of the subsequent contact process. The method of claim 1, The method of forming a self-aligned contact of a semiconductor device, characterized in that to adjust the depth of the undercut by adjusting the etching conditions during the etching process of the organic low-k dielectric layer to adjust the contact margin of the subsequent contact process. The method of claim 1, And the planarization etching process is performed by a CMP process or an etch back process.